source: trunk/platforms/tsar_generic_leti/top.cpp@ 800

Last change on this file since 800 was 796, checked in by cfuguet, 12 years ago

tsar_generic_leti, tsar_boot: used USE_IOC_RDK instead of USE_RAMDISK

  • This is the name of the constant generated by the genmap tool into the hard_config.h file.
  • Instantiating the block device in the arch.py file only when the ramdisk is not used (GIET-VM supports only one IO controller)
File size: 55.6 KB
Line 
1/////////////////////////////////////////////////////////////////////////
2// File: top.cpp (for tsar_generic_leti)
3// Author: Alain Greiner
4// Copyright: UPMC/LIP6
5// Date : february 2014
6// This program is released under the GNU public license
7/////////////////////////////////////////////////////////////////////////
8// This file define a generic TSAR architecture, fully compatible
9// with the VLSI Hardware prototype developped by CEA-LETI and LIP6
10// in the framework of the SHARP project.
11//
12// The processor is a MIPS32 processor wrapped in a GDB server
13// (this is defined in the tsar_xbar_cluster).
14//
15// It does not use an external ROM, as the boot code is (pre)loaded
16// in cluster (0,0) memory at address 0x0.
17//
18// The physical address space is 40 bits.
19// The 8 address MSB bits define the cluster index.
20//
21// The main hardware parameters are the mesh size (X_SIZE & Y_SIZE),
22// and the number of processors per cluster (NB_PROCS_MAX).
23// The number of clusters cannot be larger than 128.
24// The number of processors per cluster cannot be larger than 4.
25//
26// Each cluster contains:
27// - 5 dspin_local_crossbar (local interconnect)
28// - 5 dspin_router (global interconnect)
29// - up to 4 vci_cc_vcache wrapping a MIPS32 processor
30// - 1 vci_mem_cache
31// - 1 vci_xicu
32// - 1 vci_simple_ram (to model the L3 cache).
33//
34// Each processor receives 4 consecutive IRQ lines from the local XICU.
35//
36// In all clusters, the MEMC IRQ line (signaling a late write error)
37// is connected to XICU HWI[8]
38// The cluster (0,0) contains two "backup" peripherals:
39// - one block device controller, whose IRQ is connected to XICU HWI[9].
40// - one single channel TTY controller, whose IRQ is connected to XICU HWI[10].
41//
42// The cluster internal architecture is defined in file tsar_leti_cluster,
43// that must be considered as an extension of this top.cpp file.
44//
45// Besides the hardware components in clusters, "external" peripherals
46// are connected to an external IO bus (implemented as a vci_local_crossbar):
47// - one disk controller
48// - one multi-channel ethernet controller
49// - one multi-channel chained buffer dma controller
50// - one multi-channel tty controller
51// - one frame buffer controller
52// - one 32 channels iopic controller
53//
54// This IOBUS is connected to the north port of the DIR_CMD
55// and DIR_RSP routers, in cluster(X_SIZE-1, Y_SIZE-1).
56// For all external peripherals, the hardware interrupts (HWI) are
57// translated to write interrupts (WTI) by the iopic component:
58// - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0]
59// - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0]
60// - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]]
61// - IOPIC HWI[8] connected to IRQ_BDEV
62// - IOPIC HWI[15:9] unused (grounded)
63// - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0]]
64// - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0]]
65////////////////////////////////////////////////////////////////////////////
66// The following parameters must be defined in the hard_config.h file :
67// - X_WIDTH : number of bits for x coordinate (must be 4)
68// - Y_WIDTH : number of bits for y coordinate (must be 4)
69// - X_SIZE : number of clusters in a row (1,2,4,8,16)
70// - Y_SIZE : number of clusters in a column (1,2,4,8)
71// - NB_PROCS_MAX : number of processors per cluster (1, 2 or 4)
72// - NB_CMA_CHANNELS : number of CMA channels in I/0 cluster (4 max)
73// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (8 max)
74// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (2 max)
75//
76// Some other hardware parameters are not used when compiling the OS,
77// and are only defined in this top.cpp file:
78// - XRAM_LATENCY : external ram latency
79// - MEMC_WAYS : L2 cache number of ways
80// - MEMC_SETS : L2 cache number of sets
81// - L1_IWAYS : L1 cache instruction number of ways
82// - L1_ISETS : L1 cache instruction number of sets
83// - L1_DWAYS : L1 cache data number of ways
84// - L1_DSETS : L1 cache data number of sets
85// - FBUF_X_SIZE : width of frame buffer (pixels)
86// - FBUF_Y_SIZE : heigth of frame buffer (lines)
87// - BDEV_IMAGE_NAME : file pathname for block device
88// - NIC_RX_NAME : file pathname for NIC received packets
89// - NIC_TX_NAME : file pathname for NIC transmited packets
90// - NIC_MAC4 : MAC address
91// - NIC_MAC2 : MAC address
92/////////////////////////////////////////////////////////////////////////
93// General policy for 40 bits physical address decoding:
94// All physical segments base addresses are multiple of 1 Mbytes
95// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
96// The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define
97// the cluster index, and the LADR bits define the local index:
98// |X_ID|Y_ID| LADR | OFFSET |
99// | 4 | 4 | 8 | 24 |
100/////////////////////////////////////////////////////////////////////////
101// General policy for 14 bits SRCID decoding:
102// Each component is identified by (x_id, y_id, l_id) tuple.
103// |X_ID|Y_ID| L_ID |
104// | 4 | 4 | 6 |
105/////////////////////////////////////////////////////////////////////////
106
107#include <systemc>
108#include <sys/time.h>
109#include <iostream>
110#include <sstream>
111#include <cstdlib>
112#include <cstdarg>
113#include <stdint.h>
114
115#include "gdbserver.h"
116#include "mapping_table.h"
117#include "tsar_leti_cluster.h"
118#include "vci_local_crossbar.h"
119#include "vci_dspin_initiator_wrapper.h"
120#include "vci_dspin_target_wrapper.h"
121#include "vci_multi_tty.h"
122#include "vci_multi_nic.h"
123#include "vci_chbuf_dma.h"
124#include "vci_block_device_tsar.h"
125#include "vci_framebuffer.h"
126#include "vci_iopic.h"
127#include "alloc_elems.h"
128
129#include "hard_config.h"
130
131///////////////////////////////////////////////////
132// Parallelisation
133///////////////////////////////////////////////////
134#define USE_OPENMP _OPENMP
135
136#if USE_OPENMP
137#include <omp.h>
138#endif
139
140///////////////////////////////////////////////////
141// cluster index (from x,y coordinates)
142///////////////////////////////////////////////////
143
144#define cluster(x,y) ((y) + ((x) << Y_WIDTH))
145
146///////////////////////////////////////////////////////////
147// DSPIN parameters
148///////////////////////////////////////////////////////////
149
150#define dspin_cmd_width 39
151#define dspin_rsp_width 32
152
153///////////////////////////////////////////////////////////
154// VCI parameters
155///////////////////////////////////////////////////////////
156
157#define vci_cell_width_int 4
158#define vci_cell_width_ext 8
159#define vci_address_width 40
160#define vci_plen_width 8
161#define vci_rerror_width 1
162#define vci_clen_width 1
163#define vci_rflag_width 1
164#define vci_srcid_width 14
165#define vci_pktid_width 4
166#define vci_trdid_width 4
167#define vci_wrplen_width 1
168
169
170/////////////////////////////////////////////////////////////////////////////////////////
171// Secondary Hardware Parameters
172/////////////////////////////////////////////////////////////////////////////////////////
173
174#define MAX_TTY_CHANNELS 8
175#define MAX_CMA_CHANNELS 4
176#define MAX_NIC_CHANNELS 2
177
178#define XRAM_LATENCY 0
179
180#define MEMC_WAYS 16
181#define MEMC_SETS 256
182
183#define L1_IWAYS 4
184#define L1_ISETS 64
185
186#define L1_DWAYS 4
187#define L1_DSETS 64
188
189#define NIC_MAC4 0XBABEF00D
190#define NIC_MAC2 0xBEEF
191#define NIC_RX_NAME "/dev/null"
192#define NIC_TX_NAME "/dev/null"
193
194#define NORTH 0
195#define SOUTH 1
196#define EAST 2
197#define WEST 3
198
199///////////////////////////////////////////////////////////////////////////////////////
200// DEBUG Parameters default values
201///////////////////////////////////////////////////////////////////////////////////////
202
203#define MAX_FROZEN_CYCLES 500000
204
205///////////////////////////////////////////////////////////////////////////////////////
206// LOCAL TGTID & SRCID definition
207// For all components: global TGTID = global SRCID = cluster_index
208///////////////////////////////////////////////////////////////////////////////////////
209
210#define MEMC_TGTID 0
211#define XICU_TGTID 1
212#define MTTY_TGTID 2
213#define BDEV_TGTID 3
214#define FBUF_TGTID 4
215#define MNIC_TGTID 5
216#define CDMA_TGTID 6
217#define IOPI_TGTID 7
218
219#define BDEV_SRCID NB_PROCS_MAX
220#define CDMA_SRCID NB_PROCS_MAX + 1
221#define IOPI_SRCID NB_PROCS_MAX + 2
222
223bool stop_called = false;
224
225/////////////////////////////////
226int _main(int argc, char *argv[])
227{
228 using namespace sc_core;
229 using namespace soclib::caba;
230 using namespace soclib::common;
231
232 uint32_t ncycles = 0xFFFFFFFF; // max simulated cycles
233 size_t threads = 1; // simulator's threads number
234 bool trace_ok = false; // trace activated
235 uint32_t trace_from = 0; // trace start cycle
236 bool trace_proc_ok = false; // detailed proc trace activated
237 size_t trace_memc_ok = false; // detailed memc trace activated
238 size_t trace_memc_id = 0; // index of memc to be traced
239 size_t trace_proc_id = 0; // index of proc to be traced
240 uint32_t frozen_cycles = MAX_FROZEN_CYCLES;
241 char soft_name[256] = "soft.elf";
242 char disk_name[256] = "disk.img";
243 struct timeval t1,t2;
244 uint64_t ms1,ms2;
245
246 ////////////// command line arguments //////////////////////
247 if (argc > 1)
248 {
249 for (int n = 1; n < argc; n = n + 2)
250 {
251 if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc))
252 {
253 ncycles = (uint64_t) strtol(argv[n + 1], NULL, 0);
254 }
255 else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc))
256 {
257 trace_ok = true;
258 trace_from = (uint32_t) strtol(argv[n + 1], NULL, 0);
259 }
260 else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc))
261 {
262 trace_memc_ok = true;
263 trace_memc_id = (size_t) strtol(argv[n + 1], NULL, 0);
264 size_t x = trace_memc_id >> Y_WIDTH;
265 size_t y = trace_memc_id & ((1<<Y_WIDTH)-1);
266
267 assert( (x < X_SIZE) and (y < (Y_SIZE)) and
268 "MEMCID parameter refers a not valid memory cache");
269 }
270 else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc))
271 {
272 trace_proc_ok = true;
273 trace_proc_id = (size_t) strtol(argv[n + 1], NULL, 0);
274 size_t cluster_xy = trace_proc_id / NB_PROCS_MAX ;
275 size_t x = cluster_xy >> Y_WIDTH;
276 size_t y = cluster_xy & ((1<<Y_WIDTH)-1);
277 size_t l = trace_proc_id % NB_PROCS_MAX ;
278
279 assert( (x < X_SIZE) and (y < Y_SIZE) and (l < NB_PROCS_MAX) and
280 "PROCID parameter refers a not valid processor");
281 }
282 else if ((strcmp(argv[n], "-SOFT") == 0) && ((n + 1) < argc))
283 {
284 strcpy(soft_name, argv[n + 1]);
285 }
286 else if ((strcmp(argv[n], "-DISK") == 0) && ((n + 1) < argc))
287 {
288 strcpy(disk_name, argv[n + 1]);
289 }
290 else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc))
291 {
292 threads = (size_t) strtol(argv[n + 1], NULL, 0);
293 threads = (threads < 1) ? 1 : threads;
294 }
295 else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc))
296 {
297 frozen_cycles = (uint32_t) strtol(argv[n + 1], NULL, 0);
298 }
299 else
300 {
301 std::cout << " Arguments are (key,value) couples." << std::endl;
302 std::cout << " The order is not important." << std::endl;
303 std::cout << " Accepted arguments are :" << std::endl << std::endl;
304 std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
305 std::cout << " -DEBUG debug_start_cycle" << std::endl;
306 std::cout << " -SOFT path to soft" << std::endl;
307 std::cout << " -DISK path to disk image" << std::endl;
308 std::cout << " -THREADS simulator's threads number" << std::endl;
309 std::cout << " -FROZEN max_number_of_lines" << std::endl;
310 std::cout << " -PERIOD number_of_cycles between trace" << std::endl;
311 std::cout << " -MEMCID index_memc_to_be_traced" << std::endl;
312 std::cout << " -PROCID index_proc_to_be_traced" << std::endl;
313 exit(0);
314 }
315 }
316 }
317
318 // checking hardware parameters
319 assert( ((X_SIZE==1) or (X_SIZE==2) or (X_SIZE==4) or (X_SIZE==8) or
320 (X_SIZE==16)) and
321 "Illegal X_SIZE parameter" );
322
323 assert( ((Y_SIZE==1) or (Y_SIZE==2) or (Y_SIZE==4) or (Y_SIZE==8)) and
324 "Illegal Y_SIZE parameter" );
325
326 assert( (NB_PROCS_MAX <= 4) and
327 "Illegal NB_PROCS_MAX parameter" );
328
329 assert( (NB_CMA_CHANNELS <= MAX_CMA_CHANNELS) and
330 "The NB_CMA_CHANNELS parameter cannot be larger than 4" );
331
332 assert( (NB_TTY_CHANNELS <= MAX_TTY_CHANNELS) and
333 "The NB_TTY_CHANNELS parameter cannot be larger than 8" );
334
335 assert( (NB_NIC_CHANNELS <= MAX_NIC_CHANNELS) and
336 "The NB_NIC_CHANNELS parameter cannot be larger than 2" );
337
338 assert( (vci_address_width == 40) and
339 "VCI address width with the GIET must be 40 bits" );
340
341 assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and
342 "ERROR: you must have X_WIDTH == Y_WIDTH == 4");
343
344 std::cout << std::endl;
345
346 std::cout << " - X_SIZE = " << X_SIZE << std::endl;
347 std::cout << " - Y_SIZE = " << Y_SIZE << std::endl;
348 std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl;
349 std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl;
350 std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl;
351 std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl;
352 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;
353 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;
354 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;
355 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;
356 std::cout << " - MAX_CYCLES = " << ncycles << std::endl;
357 std::cout << " - RESET_ADDRESS = " << RESET_ADDRESS << std::endl;
358 std::cout << " - SOFT_FILENAME = " << soft_name << std::endl;
359 std::cout << " - DISK_IMAGENAME = " << disk_name << std::endl;
360 std::cout << " - OPENMP THREADS = " << threads << std::endl;
361
362 std::cout << std::endl;
363
364 // Internal and External VCI parameters definition
365 typedef soclib::caba::VciParams<vci_cell_width_int,
366 vci_plen_width,
367 vci_address_width,
368 vci_rerror_width,
369 vci_clen_width,
370 vci_rflag_width,
371 vci_srcid_width,
372 vci_pktid_width,
373 vci_trdid_width,
374 vci_wrplen_width> vci_param_int;
375
376 typedef soclib::caba::VciParams<vci_cell_width_ext,
377 vci_plen_width,
378 vci_address_width,
379 vci_rerror_width,
380 vci_clen_width,
381 vci_rflag_width,
382 vci_srcid_width,
383 vci_pktid_width,
384 vci_trdid_width,
385 vci_wrplen_width> vci_param_ext;
386
387#if USE_OPENMP
388 omp_set_dynamic(false);
389 omp_set_num_threads(threads);
390 std::cerr << "Built with openmp version " << _OPENMP << std::endl;
391#endif
392
393
394 ///////////////////////////////////////
395 // Direct Network Mapping Table
396 ///////////////////////////////////////
397
398 MappingTable maptabd(vci_address_width,
399 IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
400 IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
401 0x00FF000000ULL);
402
403 // replicated segments
404 for (size_t x = 0; x < X_SIZE; x++)
405 {
406 for (size_t y = 0; y < (Y_SIZE) ; y++)
407 {
408 sc_uint<vci_address_width> offset;
409 offset = ((sc_uint<vci_address_width>)cluster(x,y)) << 32;
410
411 std::ostringstream si;
412 si << "seg_xicu_" << x << "_" << y;
413 maptabd.add(Segment(si.str(), SEG_XCU_BASE + offset, SEG_XCU_SIZE,
414 IntTab(cluster(x,y),XICU_TGTID), false));
415
416 std::ostringstream sd;
417 sd << "seg_mcfg_" << x << "_" << y;
418 maptabd.add(Segment(sd.str(), SEG_MMC_BASE + offset, SEG_MMC_SIZE,
419 IntTab(cluster(x,y),MEMC_TGTID), false));
420
421 std::ostringstream sh;
422 sh << "seg_memc_" << x << "_" << y;
423 maptabd.add(Segment(sh.str(), SEG_RAM_BASE + offset, SEG_RAM_SIZE,
424 IntTab(cluster(x,y),MEMC_TGTID), true));
425 }
426 }
427
428 // segments for peripherals in cluster(0,0)
429 maptabd.add(Segment("seg_tty0", SEG_TTY_BASE, SEG_TTY_SIZE,
430 IntTab(cluster(0,0),MTTY_TGTID), false));
431
432 maptabd.add(Segment("seg_ioc0", SEG_IOC_BASE, SEG_IOC_SIZE,
433 IntTab(cluster(0,0),BDEV_TGTID), false));
434
435 // segments for peripherals in cluster_io (X_SIZE-1,Y_SIZE)
436 sc_uint<vci_address_width> offset;
437 offset = ((sc_uint<vci_address_width>)cluster(X_SIZE-1,Y_SIZE)) << 32;
438
439 maptabd.add(Segment("seg_mtty", SEG_TTY_BASE + offset, SEG_TTY_SIZE,
440 IntTab(cluster(X_SIZE-1, Y_SIZE),MTTY_TGTID), false));
441
442 maptabd.add(Segment("seg_fbuf", SEG_FBF_BASE + offset, SEG_FBF_SIZE,
443 IntTab(cluster(X_SIZE-1, Y_SIZE),FBUF_TGTID), false));
444
445 maptabd.add(Segment("seg_bdev", SEG_IOC_BASE + offset, SEG_IOC_SIZE,
446 IntTab(cluster(X_SIZE-1, Y_SIZE),BDEV_TGTID), false));
447
448 maptabd.add(Segment("seg_mnic", SEG_NIC_BASE + offset, SEG_NIC_SIZE,
449 IntTab(cluster(X_SIZE-1, Y_SIZE),MNIC_TGTID), false));
450
451 maptabd.add(Segment("seg_cdma", SEG_CMA_BASE + offset, SEG_CMA_SIZE,
452 IntTab(cluster(X_SIZE-1, Y_SIZE),CDMA_TGTID), false));
453
454 maptabd.add(Segment("seg_iopi", SEG_PIC_BASE + offset, SEG_PIC_SIZE,
455 IntTab(cluster(X_SIZE-1, Y_SIZE),IOPI_TGTID), false));
456
457 std::cout << maptabd << std::endl;
458
459 /////////////////////////////////////////////////
460 // Ram network mapping table
461 /////////////////////////////////////////////////
462
463 MappingTable maptabx(vci_address_width,
464 IntTab(X_WIDTH+Y_WIDTH),
465 IntTab(X_WIDTH+Y_WIDTH),
466 0x00FF000000ULL);
467
468 for (size_t x = 0; x < X_SIZE; x++)
469 {
470 for (size_t y = 0; y < (Y_SIZE) ; y++)
471 {
472 sc_uint<vci_address_width> offset;
473 offset = (sc_uint<vci_address_width>)cluster(x,y)
474 << (vci_address_width-X_WIDTH-Y_WIDTH);
475
476 std::ostringstream sh;
477 sh << "x_seg_memc_" << x << "_" << y;
478
479 maptabx.add(Segment(sh.str(), SEG_RAM_BASE + offset,
480 SEG_RAM_SIZE, IntTab(cluster(x,y)), false));
481 }
482 }
483 std::cout << maptabx << std::endl;
484
485 ////////////////////
486 // Signals
487 ///////////////////
488
489 sc_clock signal_clk("clk");
490 sc_signal<bool> signal_resetn("resetn");
491
492 // IRQs from external peripherals
493 sc_signal<bool> signal_irq_bdev;
494 sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS];
495 sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS];
496 sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS];
497// sc_signal<bool> signal_irq_mtty_tx[NB_TTY_CHANNELS];
498 sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS];
499 sc_signal<bool> signal_irq_false;
500
501 // Horizontal inter-clusters DSPIN signals
502 DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc =
503 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE);
504 DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec =
505 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE);
506
507 DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc =
508 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE);
509 DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec =
510 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE);
511
512 DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc =
513 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", X_SIZE-1, Y_SIZE);
514 DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec =
515 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", X_SIZE-1, Y_SIZE);
516
517 DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc =
518 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", X_SIZE-1, Y_SIZE);
519 DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec =
520 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", X_SIZE-1, Y_SIZE);
521
522 DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc =
523 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", X_SIZE-1, Y_SIZE);
524 DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec =
525 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", X_SIZE-1, Y_SIZE);
526
527 // Vertical inter-clusters DSPIN signals
528 DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc =
529 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-1);
530 DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec =
531 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-1);
532
533 DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc =
534 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-1);
535 DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec =
536 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-1);
537
538 DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc =
539 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", X_SIZE, Y_SIZE-1);
540 DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec =
541 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", X_SIZE, Y_SIZE-1);
542
543 DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc =
544 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", X_SIZE, Y_SIZE-1);
545 DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec =
546 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", X_SIZE, Y_SIZE-1);
547
548 DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc =
549 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", X_SIZE, Y_SIZE-1);
550 DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec =
551 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", X_SIZE, Y_SIZE-1);
552
553 // Mesh boundaries DSPIN signals (Most of those signals are not used...)
554 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in =
555 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , X_SIZE, Y_SIZE, 4);
556 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out =
557 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", X_SIZE, Y_SIZE, 4);
558
559 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in =
560 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , X_SIZE, Y_SIZE, 4);
561 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out =
562 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", X_SIZE, Y_SIZE, 4);
563
564 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in =
565 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , X_SIZE, Y_SIZE, 4);
566 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out =
567 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", X_SIZE, Y_SIZE, 4);
568
569 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in =
570 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , X_SIZE, Y_SIZE, 4);
571 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out =
572 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", X_SIZE, Y_SIZE, 4);
573
574 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in =
575 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , X_SIZE, Y_SIZE, 4);
576 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out =
577 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", X_SIZE, Y_SIZE, 4);
578
579 // VCI signals for iobus and peripherals
580 VciSignals<vci_param_int> signal_vci_ini_bdev("signal_vci_ini_bdev");
581 VciSignals<vci_param_int> signal_vci_ini_cdma("signal_vci_ini_cdma");
582 VciSignals<vci_param_int> signal_vci_ini_iopi("signal_vci_ini_iopi");
583
584 VciSignals<vci_param_int>* signal_vci_ini_proc =
585 alloc_elems<VciSignals<vci_param_int> >("signal_vci_ini_proc", NB_PROCS_MAX );
586
587 VciSignals<vci_param_int> signal_vci_tgt_memc("signal_vci_tgt_memc");
588 VciSignals<vci_param_int> signal_vci_tgt_xicu("signal_vci_tgt_xicu");
589 VciSignals<vci_param_int> signal_vci_tgt_bdev("signal_vci_tgt_bdev");
590 VciSignals<vci_param_int> signal_vci_tgt_mtty("signal_vci_tgt_mtty");
591 VciSignals<vci_param_int> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf");
592 VciSignals<vci_param_int> signal_vci_tgt_mnic("signal_vci_tgt_mnic");
593 VciSignals<vci_param_int> signal_vci_tgt_cdma("signal_vci_tgt_cdma");
594 VciSignals<vci_param_int> signal_vci_tgt_iopi("signal_vci_tgt_iopi");
595
596 VciSignals<vci_param_int> signal_vci_cmd_to_noc("signal_vci_cmd_to_noc");
597 VciSignals<vci_param_int> signal_vci_cmd_from_noc("signal_vci_cmd_from_noc");
598
599 ////////////////////////////
600 // Loader
601 ////////////////////////////
602
603#if USE_IOC_RDK
604 std::ostringstream ramdisk_name;
605 ramdisk_name << disk_name << "@" << std::hex << SEG_RDK_BASE << ":";
606 soclib::common::Loader loader( soft_name, ramdisk_name.str().c_str() );
607#else
608 soclib::common::Loader loader( soft_name );
609#endif
610 loader.memory_default(0xAA);
611
612 ///////////////////////////
613 // processor iss
614 ///////////////////////////
615
616 typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
617 proc_iss::set_loader( loader );
618
619 //////////////////////////////////////////////////////////////
620 // mesh construction: only (X_SIZE) * (Y_SIZE) clusters
621 //////////////////////////////////////////////////////////////
622
623 TsarLetiCluster<dspin_cmd_width,
624 dspin_rsp_width,
625 vci_param_int,
626 vci_param_ext>* clusters[X_SIZE][Y_SIZE];
627
628#if USE_OPENMP
629#pragma omp parallel
630 {
631#pragma omp for
632#endif
633 for (size_t i = 0; i < (X_SIZE * (Y_SIZE)); i++)
634 {
635 size_t x = i / (Y_SIZE);
636 size_t y = i % (Y_SIZE);
637
638#if USE_OPENMP
639#pragma omp critical
640 {
641#endif
642 std::cout << std::endl;
643 std::cout << "Cluster_" << std::dec << x << "_" << y
644 << " with cluster_xy = " << std::hex << cluster(x,y) << std::endl;
645 std::cout << std::endl;
646
647 std::ostringstream cluster_name;
648 cluster_name << "cluster_" << std::dec << x << "_" << y;
649
650 clusters[x][y] = new TsarLetiCluster<dspin_cmd_width,
651 dspin_rsp_width,
652 vci_param_int,
653 vci_param_ext>
654 (
655 cluster_name.str().c_str(),
656 NB_PROCS_MAX,
657 x,
658 y,
659 cluster(x,y),
660 maptabd,
661 maptabx,
662 RESET_ADDRESS,
663 X_WIDTH,
664 Y_WIDTH,
665 vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width,
666 MEMC_TGTID,
667 XICU_TGTID,
668 MTTY_TGTID,
669 BDEV_TGTID,
670 disk_name,
671 MEMC_WAYS,
672 MEMC_SETS,
673 L1_IWAYS,
674 L1_ISETS,
675 L1_DWAYS,
676 L1_DSETS,
677 XRAM_LATENCY,
678 loader,
679 frozen_cycles,
680 trace_from,
681 trace_proc_ok,
682 trace_proc_id,
683 trace_memc_ok,
684 trace_memc_id
685 );
686
687#if USE_OPENMP
688 } // end critical
689#endif
690 } // end for
691#if USE_OPENMP
692 }
693#endif
694
695 //////////////////////////////////////////////////////////////////
696 // IO bus and external peripherals in cluster[X_SIZE-1,Y_SIZE]
697 // - 6 local targets : FBF, TTY, CMA, NIC, PIC, IOC
698 // - 3 local initiators : IOC, CMA, PIC
699 // There is no PROC, no MEMC and no XICU in this cluster,
700 // but the crossbar has (NB_PROCS_MAX + 3) intiators and
701 // 8 targets, in order to use the same SRCID and TGTID space
702 // (same mapping table for the internal components,
703 // and for the external peripherals)
704 //////////////////////////////////////////////////////////////////
705
706 std::cout << std::endl;
707 std::cout << " Building IO cluster (external peripherals)" << std::endl;
708 std::cout << std::endl;
709
710 size_t cluster_io = cluster(X_SIZE-1, Y_SIZE);
711
712 //////////// vci_local_crossbar
713 VciLocalCrossbar<vci_param_int>*
714 iobus = new VciLocalCrossbar<vci_param_int>(
715 "iobus",
716 maptabd, // mapping table
717 cluster_io, // cluster_xy
718 NB_PROCS_MAX + 3, // number of local initiators
719 8, // number of local targets
720 BDEV_TGTID ); // default target index
721
722 //////////// vci_framebuffer
723 VciFrameBuffer<vci_param_int>*
724 fbuf = new VciFrameBuffer<vci_param_int>(
725 "fbuf",
726 IntTab(cluster_io, FBUF_TGTID),
727 maptabd,
728 FBUF_X_SIZE, FBUF_Y_SIZE );
729
730 //////////// vci_block_device
731 VciBlockDeviceTsar<vci_param_int>*
732 bdev = new VciBlockDeviceTsar<vci_param_int>(
733 "bdev",
734 maptabd,
735 IntTab(cluster_io, BDEV_SRCID),
736 IntTab(cluster_io, BDEV_TGTID),
737 disk_name,
738 512, // block size
739 64 ); // burst size
740
741 //////////// vci_multi_nic
742 VciMultiNic<vci_param_int>*
743 mnic = new VciMultiNic<vci_param_int>(
744 "mnic",
745 IntTab(cluster_io, MNIC_TGTID),
746 maptabd,
747 NB_NIC_CHANNELS,
748 NIC_MAC4,
749 NIC_MAC2,
750 NIC_RX_NAME,
751 NIC_TX_NAME );
752
753 ///////////// vci_chbuf_dma
754 VciChbufDma<vci_param_int>*
755 cdma = new VciChbufDma<vci_param_int>(
756 "cdma",
757 maptabd,
758 IntTab(cluster_io, CDMA_SRCID),
759 IntTab(cluster_io, CDMA_TGTID),
760 64, // burst size
761 NB_CMA_CHANNELS );
762
763 ////////////// vci_multi_tty
764 std::vector<std::string> vect_names;
765 for (size_t id = 0; id < NB_TTY_CHANNELS; id++)
766 {
767 std::ostringstream term_name;
768 term_name << "ext_" << id;
769 vect_names.push_back(term_name.str().c_str());
770 }
771
772 VciMultiTty<vci_param_int>*
773 mtty = new VciMultiTty<vci_param_int>(
774 "mtty",
775 IntTab(cluster_io, MTTY_TGTID),
776 maptabd,
777 vect_names );
778
779 ///////////// vci_iopic
780 VciIopic<vci_param_int>*
781 iopic = new VciIopic<vci_param_int>(
782 "iopic",
783 maptabd,
784 IntTab(cluster_io, IOPI_SRCID),
785 IntTab(cluster_io, IOPI_TGTID),
786 32 );
787
788 ////////////// vci_dspin wrappers
789 VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
790 wt_iobus = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
791 "wt_bdev",
792 vci_srcid_width );
793
794 VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
795 wi_iobus = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
796 "wi_bdev",
797 vci_srcid_width );
798
799 ///////////////////////////////////////////////////////////////
800 // Net-list
801 ///////////////////////////////////////////////////////////////
802
803 // iobus
804 iobus->p_clk (signal_clk);
805 iobus->p_resetn (signal_resetn);
806
807 iobus->p_target_to_up (signal_vci_cmd_from_noc);
808 iobus->p_initiator_to_up (signal_vci_cmd_to_noc);
809
810 iobus->p_to_target[MEMC_TGTID] (signal_vci_tgt_memc);
811 iobus->p_to_target[XICU_TGTID] (signal_vci_tgt_xicu);
812 iobus->p_to_target[MTTY_TGTID] (signal_vci_tgt_mtty);
813 iobus->p_to_target[FBUF_TGTID] (signal_vci_tgt_fbuf);
814 iobus->p_to_target[MNIC_TGTID] (signal_vci_tgt_mnic);
815 iobus->p_to_target[BDEV_TGTID] (signal_vci_tgt_bdev);
816 iobus->p_to_target[CDMA_TGTID] (signal_vci_tgt_cdma);
817 iobus->p_to_target[IOPI_TGTID] (signal_vci_tgt_iopi);
818
819 for( size_t p=0 ; p<NB_PROCS_MAX ; p++ )
820 {
821 iobus->p_to_initiator[p] (signal_vci_ini_proc[p]);
822 }
823 iobus->p_to_initiator[BDEV_SRCID] (signal_vci_ini_bdev);
824 iobus->p_to_initiator[CDMA_SRCID] (signal_vci_ini_cdma);
825 iobus->p_to_initiator[IOPI_SRCID] (signal_vci_ini_iopi);
826
827 std::cout << " - IOBUS connected" << std::endl;
828
829 // block_device
830 bdev->p_clk (signal_clk);
831 bdev->p_resetn (signal_resetn);
832 bdev->p_vci_target (signal_vci_tgt_bdev);
833 bdev->p_vci_initiator (signal_vci_ini_bdev);
834 bdev->p_irq (signal_irq_bdev);
835
836 std::cout << " - BDEV connected" << std::endl;
837
838 // frame_buffer
839 fbuf->p_clk (signal_clk);
840 fbuf->p_resetn (signal_resetn);
841 fbuf->p_vci (signal_vci_tgt_fbuf);
842
843 std::cout << " - FBUF connected" << std::endl;
844
845 // multi_nic
846 mnic->p_clk (signal_clk);
847 mnic->p_resetn (signal_resetn);
848 mnic->p_vci (signal_vci_tgt_mnic);
849 for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ )
850 {
851 mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
852 mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
853 }
854
855 std::cout << " - MNIC connected" << std::endl;
856
857 // chbuf_dma
858 cdma->p_clk (signal_clk);
859 cdma->p_resetn (signal_resetn);
860 cdma->p_vci_target (signal_vci_tgt_cdma);
861 cdma->p_vci_initiator (signal_vci_ini_cdma);
862 for ( size_t i=0 ; i<NB_CMA_CHANNELS ; i++)
863 {
864 cdma->p_irq[i] (signal_irq_cdma[i]);
865 }
866
867 std::cout << " - CDMA connected" << std::endl;
868
869 // multi_tty
870 mtty->p_clk (signal_clk);
871 mtty->p_resetn (signal_resetn);
872 mtty->p_vci (signal_vci_tgt_mtty);
873 for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ )
874 {
875 mtty->p_irq[i] (signal_irq_mtty_rx[i]);
876 }
877
878 std::cout << " - MTTY connected" << std::endl;
879
880 // iopic
881 // NB_NIC_CHANNELS <= 2
882 // NB_CMA_CHANNELS <= 4
883 // NB_TTY_CHANNELS <= 8
884 iopic->p_clk (signal_clk);
885 iopic->p_resetn (signal_resetn);
886 iopic->p_vci_target (signal_vci_tgt_iopi);
887 iopic->p_vci_initiator (signal_vci_ini_iopi);
888 for ( size_t i=0 ; i<32 ; i++)
889 {
890 if (i < NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_rx[i]);
891 else if(i < 2 ) iopic->p_hwi[i] (signal_irq_false);
892 else if(i < 2+NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_tx[i-2]);
893 else if(i < 4 ) iopic->p_hwi[i] (signal_irq_false);
894 else if(i < 4+NB_CMA_CHANNELS) iopic->p_hwi[i] (signal_irq_cdma[i-4]);
895 else if(i < 8) iopic->p_hwi[i] (signal_irq_false);
896 else if(i == 8) iopic->p_hwi[i] (signal_irq_bdev);
897 else if(i < 16) iopic->p_hwi[i] (signal_irq_false);
898 else if(i < 16+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_rx[i-16]);
899 else if(i < 24) iopic->p_hwi[i] (signal_irq_false);
900 else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_false);
901// else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_tx[i-24]);
902 else iopic->p_hwi[i] (signal_irq_false);
903 }
904
905 std::cout << " - IOPIC connected" << std::endl;
906
907 // vci/dspin wrappers
908 wi_iobus->p_clk (signal_clk);
909 wi_iobus->p_resetn (signal_resetn);
910 wi_iobus->p_vci (signal_vci_cmd_to_noc);
911 wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[X_SIZE-1][Y_SIZE-1][NORTH]);
912 wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[X_SIZE-1][Y_SIZE-1][NORTH]);
913
914 // vci/dspin wrappers
915 wt_iobus->p_clk (signal_clk);
916 wt_iobus->p_resetn (signal_resetn);
917 wt_iobus->p_vci (signal_vci_cmd_from_noc);
918 wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[X_SIZE-1][Y_SIZE-1][NORTH]);
919 wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[X_SIZE-1][Y_SIZE-1][NORTH]);
920
921 // Clock & RESET for clusters
922 for (size_t x = 0; x < (X_SIZE); x++)
923 {
924 for (size_t y = 0; y < (Y_SIZE); y++)
925 {
926 clusters[x][y]->p_clk (signal_clk);
927 clusters[x][y]->p_resetn (signal_resetn);
928 }
929 }
930
931 // Inter Clusters horizontal connections
932 if (X_SIZE > 1)
933 {
934 for (size_t x = 0; x < (X_SIZE-1); x++)
935 {
936 for (size_t y = 0; y < (Y_SIZE); y++)
937 {
938 clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]);
939 clusters[x+1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]);
940 clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]);
941 clusters[x+1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]);
942
943 clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]);
944 clusters[x+1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]);
945 clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]);
946 clusters[x+1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]);
947
948 clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]);
949 clusters[x+1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]);
950 clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]);
951 clusters[x+1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]);
952
953 clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]);
954 clusters[x+1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]);
955 clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]);
956 clusters[x+1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]);
957
958 clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]);
959 clusters[x+1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]);
960 clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]);
961 clusters[x+1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]);
962 }
963 }
964 }
965 std::cout << std::endl << "Horizontal connections done" << std::endl;
966
967 // Inter Clusters vertical connections
968 if (Y_SIZE > 1)
969 {
970 for (size_t y = 0; y < (Y_SIZE-1); y++)
971 {
972 for (size_t x = 0; x < X_SIZE; x++)
973 {
974 clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]);
975 clusters[x][y+1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]);
976 clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]);
977 clusters[x][y+1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]);
978
979 clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]);
980 clusters[x][y+1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]);
981 clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]);
982 clusters[x][y+1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]);
983
984 clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]);
985 clusters[x][y+1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]);
986 clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]);
987 clusters[x][y+1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]);
988
989 clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]);
990 clusters[x][y+1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]);
991 clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]);
992 clusters[x][y+1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]);
993
994 clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]);
995 clusters[x][y+1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]);
996 clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]);
997 clusters[x][y+1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]);
998 }
999 }
1000 }
1001 std::cout << std::endl << "Vertical connections done" << std::endl;
1002
1003 // East & West boundary cluster connections
1004 for (size_t y = 0; y < (Y_SIZE); y++)
1005 {
1006 clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]);
1007 clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]);
1008 clusters[X_SIZE-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[X_SIZE-1][y][EAST]);
1009 clusters[X_SIZE-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[X_SIZE-1][y][EAST]);
1010
1011 clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]);
1012 clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]);
1013 clusters[X_SIZE-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[X_SIZE-1][y][EAST]);
1014 clusters[X_SIZE-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[X_SIZE-1][y][EAST]);
1015
1016 clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]);
1017 clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]);
1018 clusters[X_SIZE-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[X_SIZE-1][y][EAST]);
1019 clusters[X_SIZE-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[X_SIZE-1][y][EAST]);
1020
1021 clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]);
1022 clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]);
1023 clusters[X_SIZE-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[X_SIZE-1][y][EAST]);
1024 clusters[X_SIZE-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[X_SIZE-1][y][EAST]);
1025
1026 clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]);
1027 clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]);
1028 clusters[X_SIZE-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[X_SIZE-1][y][EAST]);
1029 clusters[X_SIZE-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[X_SIZE-1][y][EAST]);
1030 }
1031
1032 std::cout << std::endl << "West & East boundaries connections done" << std::endl;
1033
1034 // North & South boundary clusters connections
1035 for (size_t x = 0; x < X_SIZE; x++)
1036 {
1037 clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]);
1038 clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]);
1039 clusters[x][Y_SIZE-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][Y_SIZE-1][NORTH]);
1040 clusters[x][Y_SIZE-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][Y_SIZE-1][NORTH]);
1041
1042 clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]);
1043 clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]);
1044 clusters[x][Y_SIZE-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][Y_SIZE-1][NORTH]);
1045 clusters[x][Y_SIZE-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][Y_SIZE-1][NORTH]);
1046
1047 clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]);
1048 clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]);
1049 clusters[x][Y_SIZE-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][Y_SIZE-1][NORTH]);
1050 clusters[x][Y_SIZE-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][Y_SIZE-1][NORTH]);
1051
1052 clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]);
1053 clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]);
1054 clusters[x][Y_SIZE-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][Y_SIZE-1][NORTH]);
1055 clusters[x][Y_SIZE-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][Y_SIZE-1][NORTH]);
1056
1057 clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]);
1058 clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]);
1059 clusters[x][Y_SIZE-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][Y_SIZE-1][NORTH]);
1060 clusters[x][Y_SIZE-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][Y_SIZE-1][NORTH]);
1061 }
1062
1063 std::cout << std::endl << "North & South boundaries connections done" << std::endl;
1064
1065 std::cout << std::endl;
1066
1067 ////////////////////////////////////////////////////////
1068 // Simulation
1069 ///////////////////////////////////////////////////////
1070
1071 sc_start(sc_core::sc_time(0, SC_NS));
1072 signal_resetn = false;
1073 signal_irq_false = false;
1074
1075 // set network boundaries signals default values
1076 // for all boundary clusters but the IO cluster
1077 for (size_t x = 0; x < X_SIZE ; x++)
1078 {
1079 for (size_t y = 0; y < Y_SIZE ; y++)
1080 {
1081 for (size_t face = 0; face < 4; face++)
1082 {
1083 if ( (x != X_SIZE-1) or (y != Y_SIZE-1) or (face != NORTH) )
1084 {
1085 signal_dspin_bound_cmd_in [x][y][face].write = false;
1086 signal_dspin_bound_cmd_in [x][y][face].read = true;
1087 signal_dspin_bound_cmd_out[x][y][face].write = false;
1088 signal_dspin_bound_cmd_out[x][y][face].read = true;
1089
1090 signal_dspin_bound_rsp_in [x][y][face].write = false;
1091 signal_dspin_bound_rsp_in [x][y][face].read = true;
1092 signal_dspin_bound_rsp_out[x][y][face].write = false;
1093 signal_dspin_bound_rsp_out[x][y][face].read = true;
1094 }
1095
1096 signal_dspin_bound_m2p_in [x][y][face].write = false;
1097 signal_dspin_bound_m2p_in [x][y][face].read = true;
1098 signal_dspin_bound_m2p_out[x][y][face].write = false;
1099 signal_dspin_bound_m2p_out[x][y][face].read = true;
1100
1101 signal_dspin_bound_p2m_in [x][y][face].write = false;
1102 signal_dspin_bound_p2m_in [x][y][face].read = true;
1103 signal_dspin_bound_p2m_out[x][y][face].write = false;
1104 signal_dspin_bound_p2m_out[x][y][face].read = true;
1105
1106 signal_dspin_bound_cla_in [x][y][face].write = false;
1107 signal_dspin_bound_cla_in [x][y][face].read = true;
1108 signal_dspin_bound_cla_out[x][y][face].write = false;
1109 signal_dspin_bound_cla_out[x][y][face].read = true;
1110 }
1111 }
1112 }
1113
1114 // set default values for VCI signals connected to unused ports on iobus
1115 signal_vci_tgt_memc.rspval = false;
1116 signal_vci_tgt_xicu.rspval = false;
1117 for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) signal_vci_ini_proc[p].cmdval = false;
1118
1119 sc_start(sc_core::sc_time(1, SC_NS));
1120 signal_resetn = true;
1121
1122 if (gettimeofday(&t1, NULL) != 0)
1123 {
1124 perror("gettimeofday");
1125 return EXIT_FAILURE;
1126 }
1127
1128 // variable used for IRQ trace
1129 bool prev_irq_bdev = false;
1130 bool prev_irq_mtty_rx[8];
1131 bool prev_irq_proc[16][16][4];
1132
1133 for( size_t x = 0 ; x<8 ; x++ ) prev_irq_mtty_rx[x] = false;
1134
1135 for( size_t x = 0 ; x<16 ; x++ )
1136 for( size_t y = 0 ; y<16 ; y++ )
1137 for( size_t i = 0 ; i<4 ; i++ ) prev_irq_proc[x][y][i] = false;
1138
1139 for (uint64_t n = 1; n < ncycles && !stop_called; n++)
1140 {
1141 // Monitor a specific address for L1 & L2 caches
1142 // clusters[0][0]->proc[0]->cache_monitor(0x110002C078ULL);
1143 // clusters[1][1]->memc->cache_monitor(0x110002c078ULL);
1144
1145 // stats display
1146 if( (n % 5000000) == 0)
1147 {
1148
1149 if (gettimeofday(&t2, NULL) != 0)
1150 {
1151 perror("gettimeofday");
1152 return EXIT_FAILURE;
1153 }
1154
1155 ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000;
1156 ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000;
1157 std::cerr << "platform clock frequency "
1158 << (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl;
1159
1160 if (gettimeofday(&t1, NULL) != 0)
1161 {
1162 perror("gettimeofday");
1163 return EXIT_FAILURE;
1164 }
1165 }
1166
1167 // trace display
1168 if ( trace_ok and (n > trace_from) )
1169 {
1170 std::cout << "****************** cycle " << std::dec << n ;
1171 std::cout << " ************************************************" << std::endl;
1172
1173 size_t l = 0;
1174 size_t x = 0;
1175 size_t y = 0;
1176
1177 if ( trace_proc_ok )
1178 {
1179 l = trace_proc_id % NB_PROCS_MAX ;
1180 x = (trace_proc_id / NB_PROCS_MAX) >> Y_WIDTH ;
1181 y = (trace_proc_id / NB_PROCS_MAX) & ((1<<Y_WIDTH) - 1);
1182
1183 std::ostringstream proc_signame;
1184 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
1185 clusters[x][y]->proc[l]->print_trace(1);
1186 clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str());
1187
1188 std::ostringstream xicu_signame;
1189 xicu_signame << "[SIG]XICU_" << x << "_" << y ;
1190 clusters[x][y]->xicu->print_trace(0);
1191 clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str());
1192 }
1193
1194 if ( trace_memc_ok )
1195 {
1196 x = trace_memc_id >> Y_WIDTH;
1197 y = trace_memc_id & ((1<<Y_WIDTH) - 1);
1198
1199 std::ostringstream smemc;
1200 smemc << "[SIG]MEMC_" << x << "_" << y;
1201 std::ostringstream sxram;
1202 sxram << "[SIG]XRAM_" << x << "_" << y;
1203
1204 clusters[x][y]->memc->print_trace();
1205 clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
1206 clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
1207 }
1208
1209 // trace coherence signals
1210 // clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_0]");
1211 // clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_1]");
1212 // clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_0]");
1213 // clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_1]");
1214
1215 // clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_0]");
1216 // clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_1]");
1217 // clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_0]");
1218 // clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_1]");
1219
1220 // trace xbar(s) m2p
1221 // clusters[0][0]->xbar_m2p->print_trace();
1222 // clusters[1][0]->xbar_m2p->print_trace();
1223 // clusters[0][1]->xbar_m2p->print_trace();
1224 // clusters[1][1]->xbar_m2p->print_trace();
1225
1226 // trace router(s) m2p
1227 // clusters[0][0]->router_m2p->print_trace();
1228 // clusters[1][0]->router_m2p->print_trace();
1229 // clusters[0][1]->router_m2p->print_trace();
1230 // clusters[1][1]->router_m2p->print_trace();
1231
1232 // trace external ioc
1233 bdev->print_trace();
1234 signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT");
1235 signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI");
1236
1237 // trace external iopic
1238 iopic->print_trace();
1239 signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT");
1240 signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI");
1241
1242 // trace internal tty
1243 // clusters[0][0]->mtty->print_trace();
1244 // clusters[0][0]->signal_vci_tgt_mtty.print_trace("[SIG]MTTY");
1245
1246 } // end trace
1247
1248 if (0)
1249 {
1250 // trace BDV interrupts events
1251 if ( signal_irq_bdev.read() != prev_irq_bdev )
1252 {
1253 prev_irq_bdev = signal_irq_bdev.read();
1254 std::cout << std::dec << "@@@ IRQ_BDEV = " << signal_irq_bdev.read()
1255 << " at cycle " << n << std::endl;
1256 }
1257
1258 // trace TTY interrupts events
1259 for ( size_t x = 0 ; x < 8 ; x++ )
1260 {
1261 if ( signal_irq_mtty_rx[x].read() != prev_irq_mtty_rx[x] )
1262 {
1263 prev_irq_mtty_rx[x] = signal_irq_mtty_rx[x].read();
1264 std::cout << std::dec << "@@@ IRQ_MTTY["<<x<<"] = "
1265 << signal_irq_mtty_rx[x].read()
1266 << " at cycle " << n << std::endl;
1267 }
1268 }
1269
1270 // trace processor interrupts events
1271 for ( size_t x = 0 ; x < X_SIZE ; x++ )
1272 for ( size_t y = 0 ; y < Y_SIZE ; y++ )
1273 for ( size_t i = 0 ; i < NB_PROCS_MAX ; i++ )
1274 {
1275 if ( clusters[x][y]->signal_proc_irq[i] != prev_irq_proc[x][y][i] )
1276 {
1277 prev_irq_proc[x][y][i] = clusters[x][y]->signal_proc_irq[i];
1278 std::cout << std::dec << "@@@ IRQ_PROC["<<x<<","<<y<<","<<i<<"] = "
1279 << clusters[x][y]->signal_proc_irq[i]
1280 << " at cycle " << n << std::endl;
1281 }
1282 }
1283
1284 // trace VCI transactions on IOPIC and XCU(0,0)
1285 signal_vci_tgt_iopi.print_trace("@@@ IOPI_TGT");
1286 signal_vci_ini_iopi.print_trace("@@@ IOPI_INI");
1287 clusters[0][0]->signal_vci_tgt_xicu.print_trace("@@@ XCU_0_0");
1288 }
1289
1290 sc_start(sc_core::sc_time(1, SC_NS));
1291 }
1292 // Free memory
1293 for (size_t i = 0 ; i < (X_SIZE * Y_SIZE) ; i++)
1294 {
1295 size_t x = i / (Y_SIZE);
1296 size_t y = i % (Y_SIZE);
1297 delete clusters[x][y];
1298 }
1299
1300 return EXIT_SUCCESS;
1301}
1302
1303void handler(int dummy = 0)
1304{
1305 stop_called = true;
1306 sc_stop();
1307}
1308
1309void voidhandler(int dummy = 0) {}
1310
1311int sc_main (int argc, char *argv[])
1312{
1313 signal(SIGINT, handler);
1314 signal(SIGPIPE, voidhandler);
1315
1316 try {
1317 return _main(argc, argv);
1318 } catch (std::exception &e) {
1319 std::cout << e.what() << std::endl;
1320 } catch (...) {
1321 std::cout << "Unknown exception occured" << std::endl;
1322 throw;
1323 }
1324 return 1;
1325}
1326
1327
1328// Local Variables:
1329// tab-width: 3
1330// c-basic-offset: 3
1331// c-file-offsets:((innamespace . 0)(inline-open . 0))
1332// indent-tabs-mode: nil
1333// End:
1334
1335// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
Note: See TracBrowser for help on using the repository browser.