[621] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_leti_cluster.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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[628] | 5 | // Date : february 2014 |
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[621] | 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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| 8 | |
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| 9 | #include "../include/tsar_leti_cluster.h" |
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| 10 | |
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| 11 | namespace soclib { |
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| 12 | namespace caba { |
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| 13 | |
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| 14 | //////////////////////////////////////////////////////////////////////////////////// |
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| 15 | template<size_t dspin_cmd_width, |
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| 16 | size_t dspin_rsp_width, |
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| 17 | typename vci_param_int, |
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| 18 | typename vci_param_ext> TsarLetiCluster<dspin_cmd_width, |
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| 19 | dspin_rsp_width, |
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| 20 | vci_param_int, |
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| 21 | vci_param_ext>::TsarLetiCluster( |
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| 22 | //////////////////////////////////////////////////////////////////////////////////// |
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| 23 | sc_module_name insname, |
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| 24 | size_t nb_procs, |
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| 25 | size_t x_id, |
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| 26 | size_t y_id, |
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| 27 | size_t cluster_xy, |
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| 28 | const soclib::common::MappingTable &mtd, |
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| 29 | const soclib::common::MappingTable &mtx, |
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| 30 | uint32_t reset_address, |
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| 31 | size_t x_width, |
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| 32 | size_t y_width, |
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| 33 | size_t l_width, |
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[803] | 34 | size_t p_width, |
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[621] | 35 | size_t tgtid_memc, |
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| 36 | size_t tgtid_xicu, |
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| 37 | size_t tgtid_mtty, |
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| 38 | size_t tgtid_bdev, |
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[1029] | 39 | bool use_ramdisk, |
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[628] | 40 | const char* disk_pathname, |
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[621] | 41 | size_t memc_ways, |
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| 42 | size_t memc_sets, |
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| 43 | size_t l1_i_ways, |
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| 44 | size_t l1_i_sets, |
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| 45 | size_t l1_d_ways, |
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| 46 | size_t l1_d_sets, |
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| 47 | size_t xram_latency, |
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| 48 | const Loader &loader, |
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| 49 | uint32_t frozen_cycles, |
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| 50 | uint32_t trace_start_cycle, |
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| 51 | bool trace_proc_ok, |
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| 52 | uint32_t trace_proc_id, |
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| 53 | bool trace_memc_ok, |
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| 54 | uint32_t trace_memc_id ) |
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| 55 | : soclib::caba::BaseModule(insname), |
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[692] | 56 | m_nprocs(nb_procs), |
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[621] | 57 | p_clk("clk"), |
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| 58 | p_resetn("resetn") |
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| 59 | |
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| 60 | { |
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[628] | 61 | ///////////////////////////////////////////////////////////////////////////// |
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| 62 | // Vectors of ports definition and allocation |
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| 63 | ///////////////////////////////////////////////////////////////////////////// |
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[621] | 64 | |
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[628] | 65 | p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cmd_in", 4); |
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| 66 | p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cmd_out", 4); |
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[621] | 67 | |
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[628] | 68 | p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_rsp_in", 4); |
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| 69 | p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_rsp_out", 4); |
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[621] | 70 | |
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[628] | 71 | p_m2p_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_m2p_in", 4); |
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| 72 | p_m2p_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_m2p_out", 4); |
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| 73 | |
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| 74 | p_p2m_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_p2m_in", 4); |
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| 75 | p_p2m_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_p2m_out", 4); |
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| 76 | |
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| 77 | p_cla_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cla_in", 4); |
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| 78 | p_cla_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cla_out", 4); |
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| 79 | |
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[621] | 80 | ///////////////////////////////////////////////////////////////////////////// |
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[628] | 81 | // Components definition and allocation |
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[621] | 82 | ///////////////////////////////////////////////////////////////////////////// |
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| 83 | |
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| 84 | // The processor is a MIPS32 wrapped in the GDB server |
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| 85 | // the reset address is defined by the reset_address argument |
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| 86 | typedef GdbServer<Mips32ElIss> mips_iss; |
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| 87 | mips_iss::setResetAddress( reset_address ); |
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| 88 | |
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| 89 | for (size_t p = 0; p < nb_procs; p++) |
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| 90 | { |
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[803] | 91 | uint32_t global_proc_id = (cluster_xy << p_width) + p; |
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[621] | 92 | uint32_t global_cc_id = (cluster_xy << l_width) + p; |
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| 93 | bool trace_ok = trace_proc_ok and (trace_proc_id == global_proc_id); |
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| 94 | |
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| 95 | std::ostringstream sproc; |
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| 96 | sproc << "proc_" << x_id << "_" << y_id << "_" << p; |
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| 97 | proc[p] = new VciCcVCacheWrapper<vci_param_int, |
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| 98 | dspin_cmd_width, |
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| 99 | dspin_rsp_width, |
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| 100 | mips_iss >( |
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| 101 | sproc.str().c_str(), |
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| 102 | global_proc_id, // GLOBAL PROC_ID |
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| 103 | mtd, // Mapping Table |
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| 104 | IntTab(cluster_xy,p), // SRCID |
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| 105 | global_cc_id, // GLOBAL_CC_ID |
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| 106 | 8, // ITLB ways |
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| 107 | 8, // ITLB sets |
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| 108 | 8, // DTLB ways |
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| 109 | 8, // DTLB sets |
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| 110 | l1_i_ways,l1_i_sets, 16, // ICACHE size |
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| 111 | l1_d_ways,l1_d_sets, 16, // DCACHE size |
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| 112 | 4, // WBUF nlines |
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| 113 | 4, // WBUF nwords |
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| 114 | x_width, |
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| 115 | y_width, |
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| 116 | frozen_cycles, // max frozen cycles |
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| 117 | trace_start_cycle, |
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| 118 | trace_ok ); |
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| 119 | } |
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| 120 | |
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| 121 | ///////////////////////////////////////////////////////////////////////////// |
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| 122 | bool trace_ok = trace_memc_ok and (trace_memc_id == cluster_xy); |
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| 123 | std::ostringstream smemc; |
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| 124 | smemc << "memc_" << x_id << "_" << y_id; |
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| 125 | memc = new VciMemCache<vci_param_int, |
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| 126 | vci_param_ext, |
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| 127 | dspin_rsp_width, |
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| 128 | dspin_cmd_width>( |
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| 129 | smemc.str().c_str(), |
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| 130 | mtd, // Mapping Table direct space |
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| 131 | mtx, // Mapping Table external space |
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| 132 | IntTab(cluster_xy), // SRCID external space |
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| 133 | IntTab(cluster_xy, tgtid_memc), // TGTID direct space |
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| 134 | x_width, // Number of x bits in platform |
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| 135 | y_width, // Number of y bits in platform |
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| 136 | memc_ways, memc_sets, 16, // CACHE SIZE |
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| 137 | 3, // MAX NUMBER OF COPIES |
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| 138 | 4096, // HEAP SIZE |
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| 139 | 8, // TRANSACTION TABLE DEPTH |
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| 140 | 8, // UPDATE TABLE DEPTH |
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| 141 | 8, // INVALIDATE TABLE DEPTH |
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| 142 | trace_start_cycle, |
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| 143 | trace_ok ); |
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| 144 | |
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| 145 | ///////////////////////////////////////////////////////////////////////////// |
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| 146 | std::ostringstream sxram; |
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| 147 | sxram << "xram_" << x_id << "_" << y_id; |
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| 148 | xram = new VciSimpleRam<vci_param_ext>( |
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| 149 | sxram.str().c_str(), |
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| 150 | IntTab(cluster_xy), |
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| 151 | mtx, |
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| 152 | loader, |
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| 153 | xram_latency); |
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| 154 | |
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| 155 | ///////////////////////////////////////////////////////////////////////////// |
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| 156 | std::ostringstream sxicu; |
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| 157 | sxicu << "xicu_" << x_id << "_" << y_id; |
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| 158 | xicu = new VciXicu<vci_param_int>( |
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| 159 | sxicu.str().c_str(), |
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| 160 | mtd, // mapping table |
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| 161 | IntTab(cluster_xy, tgtid_xicu), // TGTID_D |
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[628] | 162 | 16, // number of timer IRQs |
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| 163 | 16, // number of hard IRQs |
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| 164 | 16, // number of soft IRQs |
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| 165 | 16 ); // number of output IRQs |
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[621] | 166 | |
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| 167 | ///////////////////////////////////////////////////////////////////////////// |
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[628] | 168 | size_t nb_initiators = nb_procs; |
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| 169 | size_t nb_targets = 2; |
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[621] | 170 | |
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[628] | 171 | if ((x_id == 0) and (y_id == 0)) // cluster(0,0) |
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[621] | 172 | { |
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[1029] | 173 | nb_targets++; // TTY |
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| 174 | |
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| 175 | if (not use_ramdisk) |
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| 176 | { |
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| 177 | nb_initiators++; |
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| 178 | nb_targets++; |
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| 179 | } |
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[621] | 180 | } |
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| 181 | |
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[628] | 182 | std::ostringstream s_xbar_cmd; |
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[692] | 183 | xbar_cmd = new VciLocalCrossbar<vci_param_int>( |
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[628] | 184 | s_xbar_cmd.str().c_str(), |
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[621] | 185 | mtd, // mapping table |
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[692] | 186 | cluster_xy, // cluster id |
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| 187 | nb_initiators, // number of local initiators |
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| 188 | nb_targets, // number of local targets |
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| 189 | 0 ); // default target |
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[621] | 190 | |
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[692] | 191 | wi_gate = new VciDspinInitiatorWrapper<vci_param_int, |
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| 192 | dspin_cmd_width, |
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| 193 | dspin_rsp_width>( |
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| 194 | "wi_gate", |
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| 195 | x_width + y_width + l_width); |
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[621] | 196 | |
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[692] | 197 | wt_gate = new VciDspinTargetWrapper<vci_param_int, |
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| 198 | dspin_cmd_width, |
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| 199 | dspin_rsp_width>( |
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| 200 | "wt_gate", |
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| 201 | x_width + y_width + l_width); |
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| 202 | |
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[621] | 203 | ///////////////////////////////////////////////////////////////////////////// |
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[628] | 204 | std::ostringstream s_xbar_m2p; |
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| 205 | s_xbar_m2p << "xbar_m2p_" << x_id << "_" << y_id; |
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| 206 | xbar_m2p = new DspinLocalCrossbar<dspin_cmd_width>( |
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| 207 | s_xbar_m2p.str().c_str(), |
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[621] | 208 | mtd, // mapping table |
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| 209 | x_id, y_id, // cluster coordinates |
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| 210 | x_width, y_width, l_width, |
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| 211 | 1, // number of local sources |
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[628] | 212 | nb_procs, // number of local dests |
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[621] | 213 | 2, 2, // fifo depths |
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| 214 | true, // CMD |
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| 215 | false, // don't use local routing table |
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| 216 | true ); // broadcast |
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| 217 | |
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| 218 | ///////////////////////////////////////////////////////////////////////////// |
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[628] | 219 | std::ostringstream s_xbar_p2m; |
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| 220 | s_xbar_p2m << "xbar_p2m_" << x_id << "_" << y_id; |
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| 221 | xbar_p2m = new DspinLocalCrossbar<dspin_rsp_width>( |
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| 222 | s_xbar_p2m.str().c_str(), |
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[621] | 223 | mtd, // mapping table |
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| 224 | x_id, y_id, // cluster coordinates |
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| 225 | x_width, y_width, 0, // l_width unused on p2m network |
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| 226 | nb_procs, // number of local sources |
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| 227 | 1, // number of local dests |
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| 228 | 2, 2, // fifo depths |
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| 229 | false, // RSP |
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| 230 | false, // don't use local routing table |
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| 231 | false ); // no broadcast |
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| 232 | |
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| 233 | ///////////////////////////////////////////////////////////////////////////// |
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[628] | 234 | std::ostringstream s_xbar_cla; |
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| 235 | s_xbar_cla << "xbar_cla_" << x_id << "_" << y_id; |
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| 236 | xbar_cla = new DspinLocalCrossbar<dspin_cmd_width>( |
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| 237 | s_xbar_cla.str().c_str(), |
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[621] | 238 | mtd, // mapping table |
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| 239 | x_id, y_id, // cluster coordinates |
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| 240 | x_width, y_width, l_width, |
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| 241 | 1, // number of local sources |
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[628] | 242 | nb_procs, // number of local dests |
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| 243 | 2, 2, // fifo depths |
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[621] | 244 | true, // CMD |
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| 245 | false, // don't use local routing table |
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[628] | 246 | false); // no broadcast |
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[621] | 247 | |
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| 248 | ///////////////////////////////////////////////////////////////////////////// |
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[628] | 249 | std::ostringstream s_router_cmd; |
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| 250 | s_router_cmd << "router_cmd_" << x_id << "_" << y_id; |
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| 251 | router_cmd = new DspinRouter<dspin_cmd_width>( |
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| 252 | s_router_cmd.str().c_str(), |
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[621] | 253 | x_id,y_id, // coordinate in the mesh |
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| 254 | x_width, y_width, // x & y fields width |
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| 255 | 4,4); // input & output fifo depths |
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| 256 | |
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| 257 | ///////////////////////////////////////////////////////////////////////////// |
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[628] | 258 | std::ostringstream s_router_rsp; |
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| 259 | s_router_rsp << "router_rsp_" << x_id << "_" << y_id; |
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| 260 | router_rsp = new DspinRouter<dspin_rsp_width>( |
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| 261 | s_router_rsp.str().c_str(), |
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[621] | 262 | x_id,y_id, // coordinates in mesh |
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| 263 | x_width, y_width, // x & y fields width |
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| 264 | 4,4); // input & output fifo depths |
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| 265 | |
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[628] | 266 | ///////////////////////////////////////////////////////////////////////////// |
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| 267 | std::ostringstream s_router_m2p; |
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| 268 | s_router_m2p << "router_m2p_" << x_id << "_" << y_id; |
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| 269 | router_m2p = new DspinRouter<dspin_cmd_width>( |
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| 270 | s_router_m2p.str().c_str(), |
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| 271 | x_id,y_id, // coordinate in the mesh |
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| 272 | x_width, y_width, // x & y fields width |
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| 273 | 4,4, // input & output fifo depths |
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| 274 | true); // broadcast supported |
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[621] | 275 | |
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[628] | 276 | ///////////////////////////////////////////////////////////////////////////// |
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| 277 | std::ostringstream s_router_p2m; |
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| 278 | s_router_p2m << "router_p2m_" << x_id << "_" << y_id; |
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| 279 | router_p2m = new DspinRouter<dspin_rsp_width>( |
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| 280 | s_router_p2m.str().c_str(), |
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| 281 | x_id,y_id, // coordinates in mesh |
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| 282 | x_width, y_width, // x & y fields width |
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| 283 | 4,4); // input & output fifo depths |
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[621] | 284 | |
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[628] | 285 | ///////////////////////////////////////////////////////////////////////////// |
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| 286 | std::ostringstream s_router_cla; |
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| 287 | s_router_cla << "router_cla_" << x_id << "_" << y_id; |
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| 288 | router_cla = new DspinRouter<dspin_cmd_width>( |
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| 289 | s_router_cla.str().c_str(), |
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| 290 | x_id,y_id, // coordinate in the mesh |
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| 291 | x_width, y_width, // x & y fields width |
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| 292 | 4,4); // input & output fifo depths |
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| 293 | |
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[664] | 294 | // backup BDV and TTY peripherals in cluster(0,0) |
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[692] | 295 | bdev = NULL; |
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| 296 | mtty = NULL; |
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[628] | 297 | if ((x_id == 0) and (y_id == 0)) |
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| 298 | { |
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[1029] | 299 | if (not use_ramdisk) |
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| 300 | { |
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| 301 | ///////////////////////////////////////////// |
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| 302 | bdev = new VciBlockDeviceTsar<vci_param_int>( |
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| 303 | "bdev", |
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| 304 | mtd, |
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| 305 | IntTab(cluster_xy, nb_procs), |
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| 306 | IntTab(cluster_xy, tgtid_bdev), |
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| 307 | disk_pathname, |
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| 308 | 512, |
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| 309 | 64 ); // burst size |
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| 310 | } |
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[621] | 311 | |
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| 312 | ///////////////////////////////////////////// |
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| 313 | mtty = new VciMultiTty<vci_param_int>( |
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| 314 | "mtty", |
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| 315 | IntTab(cluster_xy, tgtid_mtty), |
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| 316 | mtd, |
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[692] | 317 | "tty_backup", NULL ); |
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[628] | 318 | } |
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[621] | 319 | |
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[628] | 320 | std::cout << std::endl; |
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[621] | 321 | |
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| 322 | //////////////////////////////////// |
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| 323 | // Connections are defined here |
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| 324 | //////////////////////////////////// |
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| 325 | |
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[628] | 326 | //////////////////////// ROUTERS |
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| 327 | router_cmd->p_clk (this->p_clk); |
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| 328 | router_cmd->p_resetn (this->p_resetn); |
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| 329 | router_rsp->p_clk (this->p_clk); |
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| 330 | router_rsp->p_resetn (this->p_resetn); |
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| 331 | router_m2p->p_clk (this->p_clk); |
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| 332 | router_m2p->p_resetn (this->p_resetn); |
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| 333 | router_p2m->p_clk (this->p_clk); |
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| 334 | router_p2m->p_resetn (this->p_resetn); |
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| 335 | router_cla->p_clk (this->p_clk); |
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| 336 | router_cla->p_resetn (this->p_resetn); |
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[621] | 337 | |
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[628] | 338 | // loop on N/S/E/W ports |
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| 339 | for (size_t i = 0; i < 4; i++) |
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[621] | 340 | { |
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[628] | 341 | router_cmd->p_out[i] (this->p_cmd_out[i]); |
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| 342 | router_cmd->p_in[i] (this->p_cmd_in[i]); |
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[621] | 343 | |
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[628] | 344 | router_rsp->p_out[i] (this->p_rsp_out[i]); |
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| 345 | router_rsp->p_in[i] (this->p_rsp_in[i]); |
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| 346 | |
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| 347 | router_m2p->p_out[i] (this->p_m2p_out[i]); |
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| 348 | router_m2p->p_in[i] (this->p_m2p_in[i]); |
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| 349 | |
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| 350 | router_p2m->p_out[i] (this->p_p2m_out[i]); |
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| 351 | router_p2m->p_in[i] (this->p_p2m_in[i]); |
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| 352 | |
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| 353 | router_cla->p_out[i] (this->p_cla_out[i]); |
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| 354 | router_cla->p_in[i] (this->p_cla_in[i]); |
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[621] | 355 | } |
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| 356 | |
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[628] | 357 | router_cmd->p_out[4] (signal_dspin_cmd_g2l_d); |
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| 358 | router_cmd->p_in[4] (signal_dspin_cmd_l2g_d); |
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[621] | 359 | |
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[628] | 360 | router_rsp->p_out[4] (signal_dspin_rsp_g2l_d); |
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| 361 | router_rsp->p_in[4] (signal_dspin_rsp_l2g_d); |
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[621] | 362 | |
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[628] | 363 | router_m2p->p_out[4] (signal_dspin_m2p_g2l_c); |
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| 364 | router_m2p->p_in[4] (signal_dspin_m2p_l2g_c); |
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[621] | 365 | |
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[628] | 366 | router_p2m->p_out[4] (signal_dspin_p2m_g2l_c); |
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| 367 | router_p2m->p_in[4] (signal_dspin_p2m_l2g_c); |
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[621] | 368 | |
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[628] | 369 | router_cla->p_out[4] (signal_dspin_clack_g2l_c); |
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| 370 | router_cla->p_in[4] (signal_dspin_clack_l2g_c); |
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| 371 | |
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| 372 | std::cout << " - routers connected" << std::endl; |
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| 373 | |
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[621] | 374 | ///////////////////// CMD DSPIN local crossbar direct |
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[628] | 375 | xbar_cmd->p_clk (this->p_clk); |
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| 376 | xbar_cmd->p_resetn (this->p_resetn); |
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[692] | 377 | xbar_cmd->p_initiator_to_up (signal_vci_l2g); |
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| 378 | xbar_cmd->p_target_to_up (signal_vci_g2l); |
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[621] | 379 | |
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[692] | 380 | xbar_cmd->p_to_target[tgtid_memc] (signal_vci_tgt_memc); |
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| 381 | xbar_cmd->p_to_target[tgtid_xicu] (signal_vci_tgt_xicu); |
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[621] | 382 | |
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| 383 | for (size_t p = 0; p < nb_procs; p++) |
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[692] | 384 | xbar_cmd->p_to_initiator[p] (signal_vci_ini_proc[p]); |
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[621] | 385 | |
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[628] | 386 | if ((x_id == 0) and (y_id == 0)) // cluster(0,0) |
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[621] | 387 | { |
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[692] | 388 | xbar_cmd->p_to_target[tgtid_mtty] (signal_vci_tgt_mtty); |
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[1029] | 389 | |
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| 390 | if (not use_ramdisk) |
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| 391 | { |
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| 392 | xbar_cmd->p_to_target[tgtid_bdev] (signal_vci_tgt_bdev); |
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| 393 | xbar_cmd->p_to_initiator[nb_procs] (signal_vci_ini_bdev); |
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| 394 | } |
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[621] | 395 | } |
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| 396 | |
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[692] | 397 | wi_gate->p_clk (this->p_clk); |
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| 398 | wi_gate->p_resetn (this->p_resetn); |
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| 399 | wi_gate->p_vci (signal_vci_l2g); |
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| 400 | wi_gate->p_dspin_cmd (signal_dspin_cmd_l2g_d); |
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| 401 | wi_gate->p_dspin_rsp (signal_dspin_rsp_g2l_d); |
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[621] | 402 | |
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[692] | 403 | wt_gate->p_clk (this->p_clk); |
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| 404 | wt_gate->p_resetn (this->p_resetn); |
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| 405 | wt_gate->p_vci (signal_vci_g2l); |
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| 406 | wt_gate->p_dspin_cmd (signal_dspin_cmd_g2l_d); |
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| 407 | wt_gate->p_dspin_rsp (signal_dspin_rsp_l2g_d); |
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[621] | 408 | |
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[692] | 409 | std::cout << " - CMD & RSP Direct crossbar connected" << std::endl; |
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[621] | 410 | |
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| 411 | ////////////////////// M2P DSPIN local crossbar coherence |
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[628] | 412 | xbar_m2p->p_clk (this->p_clk); |
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| 413 | xbar_m2p->p_resetn (this->p_resetn); |
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| 414 | xbar_m2p->p_global_out (signal_dspin_m2p_l2g_c); |
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| 415 | xbar_m2p->p_global_in (signal_dspin_m2p_g2l_c); |
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| 416 | xbar_m2p->p_local_in[0] (signal_dspin_m2p_memc); |
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[621] | 417 | for (size_t p = 0; p < nb_procs; p++) |
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[628] | 418 | xbar_m2p->p_local_out[p] (signal_dspin_m2p_proc[p]); |
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[621] | 419 | |
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| 420 | std::cout << " - M2P Coherence crossbar connected" << std::endl; |
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| 421 | |
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[628] | 422 | ////////////////////////// P2M DSPIN local crossbar coherence |
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| 423 | xbar_p2m->p_clk (this->p_clk); |
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| 424 | xbar_p2m->p_resetn (this->p_resetn); |
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| 425 | xbar_p2m->p_global_out (signal_dspin_p2m_l2g_c); |
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| 426 | xbar_p2m->p_global_in (signal_dspin_p2m_g2l_c); |
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| 427 | xbar_p2m->p_local_out[0] (signal_dspin_p2m_memc); |
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[621] | 428 | for (size_t p = 0; p < nb_procs; p++) |
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[628] | 429 | xbar_p2m->p_local_in[p] (signal_dspin_p2m_proc[p]); |
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[621] | 430 | |
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[628] | 431 | std::cout << " - P2M Coherence crossbar connected" << std::endl; |
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[621] | 432 | |
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[628] | 433 | ////////////////////// CLACK DSPIN local crossbar coherence |
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| 434 | xbar_cla->p_clk (this->p_clk); |
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| 435 | xbar_cla->p_resetn (this->p_resetn); |
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| 436 | xbar_cla->p_global_out (signal_dspin_clack_l2g_c); |
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| 437 | xbar_cla->p_global_in (signal_dspin_clack_g2l_c); |
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| 438 | xbar_cla->p_local_in[0] (signal_dspin_clack_memc); |
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[621] | 439 | for (size_t p = 0; p < nb_procs; p++) |
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[628] | 440 | xbar_cla->p_local_out[p] (signal_dspin_clack_proc[p]); |
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[621] | 441 | |
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[628] | 442 | std::cout << " - CLA Coherence crossbar connected" << std::endl; |
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[621] | 443 | |
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| 444 | //////////////////////////////////// Processors |
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| 445 | for (size_t p = 0; p < nb_procs; p++) |
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| 446 | { |
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| 447 | proc[p]->p_clk (this->p_clk); |
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| 448 | proc[p]->p_resetn (this->p_resetn); |
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| 449 | proc[p]->p_vci (signal_vci_ini_proc[p]); |
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| 450 | proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]); |
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| 451 | proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]); |
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| 452 | proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]); |
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[628] | 453 | |
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| 454 | for ( size_t j = 0 ; j < 6 ; j++) |
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[621] | 455 | { |
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[628] | 456 | if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_irq[4*p + j]); |
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| 457 | else proc[p]->p_irq[j] (signal_false); |
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[621] | 458 | } |
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| 459 | } |
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| 460 | |
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| 461 | std::cout << " - Processors connected" << std::endl; |
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| 462 | |
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| 463 | ///////////////////////////////////// XICU |
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| 464 | xicu->p_clk (this->p_clk); |
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| 465 | xicu->p_resetn (this->p_resetn); |
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| 466 | xicu->p_vci (signal_vci_tgt_xicu); |
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[628] | 467 | |
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| 468 | for (size_t i = 0 ; i < 16 ; i++) |
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[621] | 469 | { |
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[628] | 470 | xicu->p_irq[i] (signal_proc_irq[i]); |
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[621] | 471 | } |
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| 472 | |
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[628] | 473 | for (size_t i = 0; i < 16; i++) |
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[621] | 474 | { |
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[628] | 475 | if ((x_id == 0) and (y_id == 0)) // cluster (0,0) |
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[621] | 476 | { |
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[1029] | 477 | if (i == 8) xicu->p_hwi[i] (signal_irq_memc); |
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| 478 | else if (i == 9 and not use_ramdisk) xicu->p_hwi[i] (signal_irq_bdev); |
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| 479 | else if (i == 10) xicu->p_hwi[i] (signal_irq_mtty); |
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| 480 | else xicu->p_hwi[i] (signal_false); |
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[621] | 481 | } |
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[628] | 482 | else // other clusters |
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[621] | 483 | { |
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[732] | 484 | if (i == 8) xicu->p_hwi[i] (signal_irq_memc); |
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[628] | 485 | else xicu->p_hwi[i] (signal_false); |
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[621] | 486 | } |
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| 487 | } |
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| 488 | |
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| 489 | std::cout << " - XICU connected" << std::endl; |
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| 490 | |
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| 491 | //////////////////////////////////////////////// MEMC |
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| 492 | memc->p_clk (this->p_clk); |
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| 493 | memc->p_resetn (this->p_resetn); |
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| 494 | memc->p_irq (signal_irq_memc); |
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| 495 | memc->p_vci_ixr (signal_vci_xram); |
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| 496 | memc->p_vci_tgt (signal_vci_tgt_memc); |
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| 497 | memc->p_dspin_p2m (signal_dspin_p2m_memc); |
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| 498 | memc->p_dspin_m2p (signal_dspin_m2p_memc); |
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| 499 | memc->p_dspin_clack (signal_dspin_clack_memc); |
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| 500 | |
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| 501 | std::cout << " - MEMC connected" << std::endl; |
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| 502 | |
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| 503 | /////////////////////////////////////////////// XRAM |
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| 504 | xram->p_clk (this->p_clk); |
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| 505 | xram->p_resetn (this->p_resetn); |
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| 506 | xram->p_vci (signal_vci_xram); |
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| 507 | |
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| 508 | std::cout << " - XRAM connected" << std::endl; |
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| 509 | |
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[628] | 510 | /////////////////////////////// Extra Components in cluster(0,0) |
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[621] | 511 | |
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[628] | 512 | if ((x_id == 0) and (y_id == 0)) |
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[621] | 513 | { |
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[1029] | 514 | if (not use_ramdisk) |
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| 515 | { |
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| 516 | // BDEV |
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| 517 | bdev->p_clk (this->p_clk); |
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| 518 | bdev->p_resetn (this->p_resetn); |
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| 519 | bdev->p_irq (signal_irq_bdev); |
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| 520 | bdev->p_vci_target (signal_vci_tgt_bdev); |
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| 521 | bdev->p_vci_initiator (signal_vci_ini_bdev); |
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[621] | 522 | |
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[1029] | 523 | std::cout << " - BDEV connected" << std::endl; |
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| 524 | } |
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[621] | 525 | |
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[628] | 526 | // MTTY (single channel) |
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[621] | 527 | mtty->p_clk (this->p_clk); |
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| 528 | mtty->p_resetn (this->p_resetn); |
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| 529 | mtty->p_vci (signal_vci_tgt_mtty); |
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[628] | 530 | mtty->p_irq[0] (signal_irq_mtty); |
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[621] | 531 | |
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| 532 | std::cout << " - MTTY connected" << std::endl; |
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[628] | 533 | } |
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[621] | 534 | } // end constructor |
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| 535 | |
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| 536 | |
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| 537 | |
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| 538 | template<size_t dspin_cmd_width, |
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| 539 | size_t dspin_rsp_width, |
---|
| 540 | typename vci_param_int, |
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| 541 | typename vci_param_ext> TsarLetiCluster<dspin_cmd_width, |
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| 542 | dspin_rsp_width, |
---|
| 543 | vci_param_int, |
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| 544 | vci_param_ext>::~TsarLetiCluster() { |
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| 545 | |
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[628] | 546 | dealloc_elems<DspinInput<dspin_cmd_width> > (p_cmd_in, 4); |
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| 547 | dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cmd_out, 4); |
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[621] | 548 | |
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[628] | 549 | dealloc_elems<DspinInput<dspin_rsp_width> > (p_rsp_in, 4); |
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| 550 | dealloc_elems<DspinOutput<dspin_rsp_width> >(p_rsp_out, 4); |
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| 551 | |
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| 552 | dealloc_elems<DspinInput<dspin_cmd_width> > (p_m2p_in, 4); |
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| 553 | dealloc_elems<DspinOutput<dspin_cmd_width> >(p_m2p_out, 4); |
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| 554 | |
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| 555 | dealloc_elems<DspinInput<dspin_rsp_width> > (p_p2m_in, 4); |
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| 556 | dealloc_elems<DspinOutput<dspin_rsp_width> >(p_p2m_out, 4); |
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| 557 | |
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| 558 | dealloc_elems<DspinInput<dspin_cmd_width> > (p_cla_in, 4); |
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| 559 | dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cla_out, 4); |
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| 560 | |
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[692] | 561 | for (size_t p = 0; p < m_nprocs ; p++) |
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[621] | 562 | { |
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[692] | 563 | if ( proc[p] ) delete proc[p]; |
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[621] | 564 | } |
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| 565 | |
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| 566 | delete memc; |
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| 567 | delete xram; |
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| 568 | delete xicu; |
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[628] | 569 | delete xbar_cmd; |
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| 570 | delete xbar_m2p; |
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| 571 | delete xbar_p2m; |
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| 572 | delete xbar_cla; |
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[621] | 573 | delete router_cmd; |
---|
| 574 | delete router_rsp; |
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[628] | 575 | delete router_m2p; |
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| 576 | delete router_p2m; |
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| 577 | delete router_cla; |
---|
[692] | 578 | delete wi_gate; |
---|
| 579 | delete wt_gate; |
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[628] | 580 | |
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| 581 | if ( bdev ) |
---|
[621] | 582 | { |
---|
| 583 | delete bdev; |
---|
[628] | 584 | } |
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| 585 | |
---|
| 586 | if ( mtty ) |
---|
| 587 | { |
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[621] | 588 | delete mtty; |
---|
| 589 | } |
---|
| 590 | } |
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| 591 | |
---|
| 592 | |
---|
| 593 | }} |
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| 594 | |
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| 595 | // Local Variables: |
---|
| 596 | // tab-width: 4 |
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| 597 | // c-basic-offset: 4 |
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| 598 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 599 | // indent-tabs-mode: nil |
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| 600 | // End: |
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| 601 | |
---|
| 602 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 603 | |
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| 604 | |
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| 605 | |
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