[621] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_leti_cluster.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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[628] | 5 | // Date : february 2014 |
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[621] | 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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| 8 | |
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| 9 | #include "../include/tsar_leti_cluster.h" |
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| 10 | |
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| 11 | namespace soclib { |
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| 12 | namespace caba { |
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| 13 | |
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| 14 | //////////////////////////////////////////////////////////////////////////////////// |
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| 15 | template<size_t dspin_cmd_width, |
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| 16 | size_t dspin_rsp_width, |
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| 17 | typename vci_param_int, |
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| 18 | typename vci_param_ext> TsarLetiCluster<dspin_cmd_width, |
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| 19 | dspin_rsp_width, |
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| 20 | vci_param_int, |
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| 21 | vci_param_ext>::TsarLetiCluster( |
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| 22 | //////////////////////////////////////////////////////////////////////////////////// |
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| 23 | sc_module_name insname, |
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| 24 | size_t nb_procs, |
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| 25 | size_t x_id, |
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| 26 | size_t y_id, |
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| 27 | size_t cluster_xy, |
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| 28 | const soclib::common::MappingTable &mtd, |
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| 29 | const soclib::common::MappingTable &mtx, |
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| 30 | uint32_t reset_address, |
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| 31 | size_t x_width, |
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| 32 | size_t y_width, |
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| 33 | size_t l_width, |
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| 34 | size_t tgtid_memc, |
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| 35 | size_t tgtid_xicu, |
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| 36 | size_t tgtid_mtty, |
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| 37 | size_t tgtid_bdev, |
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[628] | 38 | const char* disk_pathname, |
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[621] | 39 | size_t memc_ways, |
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| 40 | size_t memc_sets, |
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| 41 | size_t l1_i_ways, |
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| 42 | size_t l1_i_sets, |
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| 43 | size_t l1_d_ways, |
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| 44 | size_t l1_d_sets, |
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| 45 | size_t xram_latency, |
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| 46 | const Loader &loader, |
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| 47 | uint32_t frozen_cycles, |
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| 48 | uint32_t trace_start_cycle, |
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| 49 | bool trace_proc_ok, |
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| 50 | uint32_t trace_proc_id, |
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| 51 | bool trace_memc_ok, |
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| 52 | uint32_t trace_memc_id ) |
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| 53 | : soclib::caba::BaseModule(insname), |
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[692] | 54 | m_nprocs(nb_procs), |
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[621] | 55 | p_clk("clk"), |
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| 56 | p_resetn("resetn") |
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| 57 | |
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| 58 | { |
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[628] | 59 | ///////////////////////////////////////////////////////////////////////////// |
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| 60 | // Vectors of ports definition and allocation |
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| 61 | ///////////////////////////////////////////////////////////////////////////// |
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[621] | 62 | |
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[628] | 63 | p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cmd_in", 4); |
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| 64 | p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cmd_out", 4); |
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[621] | 65 | |
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[628] | 66 | p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_rsp_in", 4); |
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| 67 | p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_rsp_out", 4); |
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[621] | 68 | |
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[628] | 69 | p_m2p_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_m2p_in", 4); |
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| 70 | p_m2p_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_m2p_out", 4); |
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| 71 | |
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| 72 | p_p2m_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_p2m_in", 4); |
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| 73 | p_p2m_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_p2m_out", 4); |
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| 74 | |
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| 75 | p_cla_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cla_in", 4); |
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| 76 | p_cla_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cla_out", 4); |
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| 77 | |
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[621] | 78 | ///////////////////////////////////////////////////////////////////////////// |
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[628] | 79 | // Components definition and allocation |
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[621] | 80 | ///////////////////////////////////////////////////////////////////////////// |
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| 81 | |
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| 82 | // The processor is a MIPS32 wrapped in the GDB server |
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| 83 | // the reset address is defined by the reset_address argument |
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| 84 | typedef GdbServer<Mips32ElIss> mips_iss; |
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| 85 | mips_iss::setResetAddress( reset_address ); |
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| 86 | |
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| 87 | for (size_t p = 0; p < nb_procs; p++) |
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| 88 | { |
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| 89 | uint32_t global_proc_id = cluster_xy * nb_procs + p; |
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| 90 | uint32_t global_cc_id = (cluster_xy << l_width) + p; |
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| 91 | bool trace_ok = trace_proc_ok and (trace_proc_id == global_proc_id); |
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| 92 | |
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| 93 | std::ostringstream sproc; |
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| 94 | sproc << "proc_" << x_id << "_" << y_id << "_" << p; |
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| 95 | proc[p] = new VciCcVCacheWrapper<vci_param_int, |
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| 96 | dspin_cmd_width, |
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| 97 | dspin_rsp_width, |
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| 98 | mips_iss >( |
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| 99 | sproc.str().c_str(), |
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| 100 | global_proc_id, // GLOBAL PROC_ID |
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| 101 | mtd, // Mapping Table |
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| 102 | IntTab(cluster_xy,p), // SRCID |
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| 103 | global_cc_id, // GLOBAL_CC_ID |
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| 104 | 8, // ITLB ways |
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| 105 | 8, // ITLB sets |
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| 106 | 8, // DTLB ways |
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| 107 | 8, // DTLB sets |
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| 108 | l1_i_ways,l1_i_sets, 16, // ICACHE size |
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| 109 | l1_d_ways,l1_d_sets, 16, // DCACHE size |
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| 110 | 4, // WBUF nlines |
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| 111 | 4, // WBUF nwords |
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| 112 | x_width, |
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| 113 | y_width, |
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| 114 | frozen_cycles, // max frozen cycles |
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| 115 | trace_start_cycle, |
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| 116 | trace_ok ); |
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| 117 | } |
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| 118 | |
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| 119 | ///////////////////////////////////////////////////////////////////////////// |
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| 120 | bool trace_ok = trace_memc_ok and (trace_memc_id == cluster_xy); |
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| 121 | std::ostringstream smemc; |
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| 122 | smemc << "memc_" << x_id << "_" << y_id; |
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| 123 | memc = new VciMemCache<vci_param_int, |
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| 124 | vci_param_ext, |
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| 125 | dspin_rsp_width, |
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| 126 | dspin_cmd_width>( |
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| 127 | smemc.str().c_str(), |
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| 128 | mtd, // Mapping Table direct space |
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| 129 | mtx, // Mapping Table external space |
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| 130 | IntTab(cluster_xy), // SRCID external space |
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| 131 | IntTab(cluster_xy, tgtid_memc), // TGTID direct space |
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| 132 | x_width, // Number of x bits in platform |
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| 133 | y_width, // Number of y bits in platform |
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| 134 | memc_ways, memc_sets, 16, // CACHE SIZE |
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| 135 | 3, // MAX NUMBER OF COPIES |
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| 136 | 4096, // HEAP SIZE |
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| 137 | 8, // TRANSACTION TABLE DEPTH |
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| 138 | 8, // UPDATE TABLE DEPTH |
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| 139 | 8, // INVALIDATE TABLE DEPTH |
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| 140 | trace_start_cycle, |
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| 141 | trace_ok ); |
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| 142 | |
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| 143 | ///////////////////////////////////////////////////////////////////////////// |
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| 144 | std::ostringstream sxram; |
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| 145 | sxram << "xram_" << x_id << "_" << y_id; |
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| 146 | xram = new VciSimpleRam<vci_param_ext>( |
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| 147 | sxram.str().c_str(), |
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| 148 | IntTab(cluster_xy), |
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| 149 | mtx, |
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| 150 | loader, |
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| 151 | xram_latency); |
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| 152 | |
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| 153 | ///////////////////////////////////////////////////////////////////////////// |
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| 154 | std::ostringstream sxicu; |
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| 155 | sxicu << "xicu_" << x_id << "_" << y_id; |
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| 156 | xicu = new VciXicu<vci_param_int>( |
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| 157 | sxicu.str().c_str(), |
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| 158 | mtd, // mapping table |
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| 159 | IntTab(cluster_xy, tgtid_xicu), // TGTID_D |
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[628] | 160 | 16, // number of timer IRQs |
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| 161 | 16, // number of hard IRQs |
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| 162 | 16, // number of soft IRQs |
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| 163 | 16 ); // number of output IRQs |
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[621] | 164 | |
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| 165 | ///////////////////////////////////////////////////////////////////////////// |
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[628] | 166 | size_t nb_initiators = nb_procs; |
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| 167 | size_t nb_targets = 2; |
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[621] | 168 | |
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[628] | 169 | if ((x_id == 0) and (y_id == 0)) // cluster(0,0) |
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[621] | 170 | { |
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[628] | 171 | nb_initiators = nb_procs + 1; |
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| 172 | nb_targets = 4; |
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[621] | 173 | } |
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| 174 | |
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[628] | 175 | std::ostringstream s_xbar_cmd; |
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[692] | 176 | xbar_cmd = new VciLocalCrossbar<vci_param_int>( |
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[628] | 177 | s_xbar_cmd.str().c_str(), |
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[621] | 178 | mtd, // mapping table |
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[692] | 179 | cluster_xy, // cluster id |
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| 180 | nb_initiators, // number of local initiators |
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| 181 | nb_targets, // number of local targets |
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| 182 | 0 ); // default target |
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[621] | 183 | |
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[692] | 184 | wi_gate = new VciDspinInitiatorWrapper<vci_param_int, |
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| 185 | dspin_cmd_width, |
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| 186 | dspin_rsp_width>( |
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| 187 | "wi_gate", |
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| 188 | x_width + y_width + l_width); |
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[621] | 189 | |
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[692] | 190 | wt_gate = new VciDspinTargetWrapper<vci_param_int, |
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| 191 | dspin_cmd_width, |
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| 192 | dspin_rsp_width>( |
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| 193 | "wt_gate", |
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| 194 | x_width + y_width + l_width); |
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| 195 | |
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[621] | 196 | ///////////////////////////////////////////////////////////////////////////// |
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[628] | 197 | std::ostringstream s_xbar_m2p; |
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| 198 | s_xbar_m2p << "xbar_m2p_" << x_id << "_" << y_id; |
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| 199 | xbar_m2p = new DspinLocalCrossbar<dspin_cmd_width>( |
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| 200 | s_xbar_m2p.str().c_str(), |
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[621] | 201 | mtd, // mapping table |
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| 202 | x_id, y_id, // cluster coordinates |
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| 203 | x_width, y_width, l_width, |
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| 204 | 1, // number of local sources |
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[628] | 205 | nb_procs, // number of local dests |
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[621] | 206 | 2, 2, // fifo depths |
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| 207 | true, // CMD |
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| 208 | false, // don't use local routing table |
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| 209 | true ); // broadcast |
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| 210 | |
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| 211 | ///////////////////////////////////////////////////////////////////////////// |
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[628] | 212 | std::ostringstream s_xbar_p2m; |
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| 213 | s_xbar_p2m << "xbar_p2m_" << x_id << "_" << y_id; |
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| 214 | xbar_p2m = new DspinLocalCrossbar<dspin_rsp_width>( |
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| 215 | s_xbar_p2m.str().c_str(), |
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[621] | 216 | mtd, // mapping table |
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| 217 | x_id, y_id, // cluster coordinates |
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| 218 | x_width, y_width, 0, // l_width unused on p2m network |
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| 219 | nb_procs, // number of local sources |
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| 220 | 1, // number of local dests |
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| 221 | 2, 2, // fifo depths |
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| 222 | false, // RSP |
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| 223 | false, // don't use local routing table |
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| 224 | false ); // no broadcast |
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| 225 | |
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| 226 | ///////////////////////////////////////////////////////////////////////////// |
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[628] | 227 | std::ostringstream s_xbar_cla; |
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| 228 | s_xbar_cla << "xbar_cla_" << x_id << "_" << y_id; |
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| 229 | xbar_cla = new DspinLocalCrossbar<dspin_cmd_width>( |
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| 230 | s_xbar_cla.str().c_str(), |
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[621] | 231 | mtd, // mapping table |
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| 232 | x_id, y_id, // cluster coordinates |
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| 233 | x_width, y_width, l_width, |
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| 234 | 1, // number of local sources |
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[628] | 235 | nb_procs, // number of local dests |
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| 236 | 2, 2, // fifo depths |
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[621] | 237 | true, // CMD |
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| 238 | false, // don't use local routing table |
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[628] | 239 | false); // no broadcast |
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[621] | 240 | |
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| 241 | ///////////////////////////////////////////////////////////////////////////// |
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[628] | 242 | std::ostringstream s_router_cmd; |
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| 243 | s_router_cmd << "router_cmd_" << x_id << "_" << y_id; |
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| 244 | router_cmd = new DspinRouter<dspin_cmd_width>( |
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| 245 | s_router_cmd.str().c_str(), |
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[621] | 246 | x_id,y_id, // coordinate in the mesh |
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| 247 | x_width, y_width, // x & y fields width |
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| 248 | 4,4); // input & output fifo depths |
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| 249 | |
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| 250 | ///////////////////////////////////////////////////////////////////////////// |
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[628] | 251 | std::ostringstream s_router_rsp; |
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| 252 | s_router_rsp << "router_rsp_" << x_id << "_" << y_id; |
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| 253 | router_rsp = new DspinRouter<dspin_rsp_width>( |
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| 254 | s_router_rsp.str().c_str(), |
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[621] | 255 | x_id,y_id, // coordinates in mesh |
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| 256 | x_width, y_width, // x & y fields width |
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| 257 | 4,4); // input & output fifo depths |
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| 258 | |
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[628] | 259 | ///////////////////////////////////////////////////////////////////////////// |
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| 260 | std::ostringstream s_router_m2p; |
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| 261 | s_router_m2p << "router_m2p_" << x_id << "_" << y_id; |
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| 262 | router_m2p = new DspinRouter<dspin_cmd_width>( |
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| 263 | s_router_m2p.str().c_str(), |
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| 264 | x_id,y_id, // coordinate in the mesh |
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| 265 | x_width, y_width, // x & y fields width |
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| 266 | 4,4, // input & output fifo depths |
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| 267 | true); // broadcast supported |
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[621] | 268 | |
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[628] | 269 | ///////////////////////////////////////////////////////////////////////////// |
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| 270 | std::ostringstream s_router_p2m; |
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| 271 | s_router_p2m << "router_p2m_" << x_id << "_" << y_id; |
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| 272 | router_p2m = new DspinRouter<dspin_rsp_width>( |
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| 273 | s_router_p2m.str().c_str(), |
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| 274 | x_id,y_id, // coordinates in mesh |
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| 275 | x_width, y_width, // x & y fields width |
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| 276 | 4,4); // input & output fifo depths |
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[621] | 277 | |
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[628] | 278 | ///////////////////////////////////////////////////////////////////////////// |
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| 279 | std::ostringstream s_router_cla; |
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| 280 | s_router_cla << "router_cla_" << x_id << "_" << y_id; |
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| 281 | router_cla = new DspinRouter<dspin_cmd_width>( |
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| 282 | s_router_cla.str().c_str(), |
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| 283 | x_id,y_id, // coordinate in the mesh |
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| 284 | x_width, y_width, // x & y fields width |
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| 285 | 4,4); // input & output fifo depths |
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| 286 | |
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[664] | 287 | // backup BDV and TTY peripherals in cluster(0,0) |
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[692] | 288 | bdev = NULL; |
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| 289 | mtty = NULL; |
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[628] | 290 | if ((x_id == 0) and (y_id == 0)) |
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| 291 | { |
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[621] | 292 | ///////////////////////////////////////////// |
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| 293 | bdev = new VciBlockDeviceTsar<vci_param_int>( |
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| 294 | "bdev", |
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| 295 | mtd, |
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[628] | 296 | IntTab(cluster_xy, nb_procs), |
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[621] | 297 | IntTab(cluster_xy, tgtid_bdev), |
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[628] | 298 | disk_pathname, |
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| 299 | 512, |
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| 300 | 64 ); // burst size |
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[621] | 301 | |
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| 302 | ///////////////////////////////////////////// |
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| 303 | mtty = new VciMultiTty<vci_param_int>( |
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| 304 | "mtty", |
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| 305 | IntTab(cluster_xy, tgtid_mtty), |
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| 306 | mtd, |
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[692] | 307 | "tty_backup", NULL ); |
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[628] | 308 | } |
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[621] | 309 | |
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[628] | 310 | std::cout << std::endl; |
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[621] | 311 | |
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| 312 | //////////////////////////////////// |
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| 313 | // Connections are defined here |
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| 314 | //////////////////////////////////// |
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| 315 | |
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[628] | 316 | //////////////////////// ROUTERS |
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| 317 | router_cmd->p_clk (this->p_clk); |
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| 318 | router_cmd->p_resetn (this->p_resetn); |
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| 319 | router_rsp->p_clk (this->p_clk); |
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| 320 | router_rsp->p_resetn (this->p_resetn); |
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| 321 | router_m2p->p_clk (this->p_clk); |
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| 322 | router_m2p->p_resetn (this->p_resetn); |
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| 323 | router_p2m->p_clk (this->p_clk); |
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| 324 | router_p2m->p_resetn (this->p_resetn); |
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| 325 | router_cla->p_clk (this->p_clk); |
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| 326 | router_cla->p_resetn (this->p_resetn); |
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[621] | 327 | |
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[628] | 328 | // loop on N/S/E/W ports |
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| 329 | for (size_t i = 0; i < 4; i++) |
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[621] | 330 | { |
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[628] | 331 | router_cmd->p_out[i] (this->p_cmd_out[i]); |
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| 332 | router_cmd->p_in[i] (this->p_cmd_in[i]); |
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[621] | 333 | |
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[628] | 334 | router_rsp->p_out[i] (this->p_rsp_out[i]); |
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| 335 | router_rsp->p_in[i] (this->p_rsp_in[i]); |
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| 336 | |
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| 337 | router_m2p->p_out[i] (this->p_m2p_out[i]); |
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| 338 | router_m2p->p_in[i] (this->p_m2p_in[i]); |
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| 339 | |
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| 340 | router_p2m->p_out[i] (this->p_p2m_out[i]); |
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| 341 | router_p2m->p_in[i] (this->p_p2m_in[i]); |
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| 342 | |
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| 343 | router_cla->p_out[i] (this->p_cla_out[i]); |
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| 344 | router_cla->p_in[i] (this->p_cla_in[i]); |
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[621] | 345 | } |
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| 346 | |
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[628] | 347 | router_cmd->p_out[4] (signal_dspin_cmd_g2l_d); |
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| 348 | router_cmd->p_in[4] (signal_dspin_cmd_l2g_d); |
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[621] | 349 | |
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[628] | 350 | router_rsp->p_out[4] (signal_dspin_rsp_g2l_d); |
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| 351 | router_rsp->p_in[4] (signal_dspin_rsp_l2g_d); |
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[621] | 352 | |
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[628] | 353 | router_m2p->p_out[4] (signal_dspin_m2p_g2l_c); |
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| 354 | router_m2p->p_in[4] (signal_dspin_m2p_l2g_c); |
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[621] | 355 | |
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[628] | 356 | router_p2m->p_out[4] (signal_dspin_p2m_g2l_c); |
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| 357 | router_p2m->p_in[4] (signal_dspin_p2m_l2g_c); |
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[621] | 358 | |
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[628] | 359 | router_cla->p_out[4] (signal_dspin_clack_g2l_c); |
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| 360 | router_cla->p_in[4] (signal_dspin_clack_l2g_c); |
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| 361 | |
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| 362 | std::cout << " - routers connected" << std::endl; |
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| 363 | |
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[621] | 364 | ///////////////////// CMD DSPIN local crossbar direct |
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[628] | 365 | xbar_cmd->p_clk (this->p_clk); |
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| 366 | xbar_cmd->p_resetn (this->p_resetn); |
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[692] | 367 | xbar_cmd->p_initiator_to_up (signal_vci_l2g); |
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| 368 | xbar_cmd->p_target_to_up (signal_vci_g2l); |
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[621] | 369 | |
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[692] | 370 | xbar_cmd->p_to_target[tgtid_memc] (signal_vci_tgt_memc); |
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| 371 | xbar_cmd->p_to_target[tgtid_xicu] (signal_vci_tgt_xicu); |
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[621] | 372 | |
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| 373 | for (size_t p = 0; p < nb_procs; p++) |
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[692] | 374 | xbar_cmd->p_to_initiator[p] (signal_vci_ini_proc[p]); |
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[621] | 375 | |
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[628] | 376 | if ((x_id == 0) and (y_id == 0)) // cluster(0,0) |
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[621] | 377 | { |
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[692] | 378 | xbar_cmd->p_to_target[tgtid_mtty] (signal_vci_tgt_mtty); |
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| 379 | xbar_cmd->p_to_target[tgtid_bdev] (signal_vci_tgt_bdev); |
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| 380 | xbar_cmd->p_to_initiator[nb_procs] (signal_vci_ini_bdev); |
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[621] | 381 | } |
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| 382 | |
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[692] | 383 | wi_gate->p_clk (this->p_clk); |
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| 384 | wi_gate->p_resetn (this->p_resetn); |
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| 385 | wi_gate->p_vci (signal_vci_l2g); |
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| 386 | wi_gate->p_dspin_cmd (signal_dspin_cmd_l2g_d); |
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| 387 | wi_gate->p_dspin_rsp (signal_dspin_rsp_g2l_d); |
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[621] | 388 | |
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[692] | 389 | wt_gate->p_clk (this->p_clk); |
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| 390 | wt_gate->p_resetn (this->p_resetn); |
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| 391 | wt_gate->p_vci (signal_vci_g2l); |
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| 392 | wt_gate->p_dspin_cmd (signal_dspin_cmd_g2l_d); |
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| 393 | wt_gate->p_dspin_rsp (signal_dspin_rsp_l2g_d); |
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[621] | 394 | |
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[692] | 395 | std::cout << " - CMD & RSP Direct crossbar connected" << std::endl; |
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[621] | 396 | |
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| 397 | ////////////////////// M2P DSPIN local crossbar coherence |
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[628] | 398 | xbar_m2p->p_clk (this->p_clk); |
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| 399 | xbar_m2p->p_resetn (this->p_resetn); |
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| 400 | xbar_m2p->p_global_out (signal_dspin_m2p_l2g_c); |
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| 401 | xbar_m2p->p_global_in (signal_dspin_m2p_g2l_c); |
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| 402 | xbar_m2p->p_local_in[0] (signal_dspin_m2p_memc); |
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[621] | 403 | for (size_t p = 0; p < nb_procs; p++) |
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[628] | 404 | xbar_m2p->p_local_out[p] (signal_dspin_m2p_proc[p]); |
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[621] | 405 | |
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| 406 | std::cout << " - M2P Coherence crossbar connected" << std::endl; |
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| 407 | |
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[628] | 408 | ////////////////////////// P2M DSPIN local crossbar coherence |
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| 409 | xbar_p2m->p_clk (this->p_clk); |
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| 410 | xbar_p2m->p_resetn (this->p_resetn); |
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| 411 | xbar_p2m->p_global_out (signal_dspin_p2m_l2g_c); |
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| 412 | xbar_p2m->p_global_in (signal_dspin_p2m_g2l_c); |
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| 413 | xbar_p2m->p_local_out[0] (signal_dspin_p2m_memc); |
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[621] | 414 | for (size_t p = 0; p < nb_procs; p++) |
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[628] | 415 | xbar_p2m->p_local_in[p] (signal_dspin_p2m_proc[p]); |
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[621] | 416 | |
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[628] | 417 | std::cout << " - P2M Coherence crossbar connected" << std::endl; |
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[621] | 418 | |
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[628] | 419 | ////////////////////// CLACK DSPIN local crossbar coherence |
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| 420 | xbar_cla->p_clk (this->p_clk); |
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| 421 | xbar_cla->p_resetn (this->p_resetn); |
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| 422 | xbar_cla->p_global_out (signal_dspin_clack_l2g_c); |
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| 423 | xbar_cla->p_global_in (signal_dspin_clack_g2l_c); |
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| 424 | xbar_cla->p_local_in[0] (signal_dspin_clack_memc); |
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[621] | 425 | for (size_t p = 0; p < nb_procs; p++) |
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[628] | 426 | xbar_cla->p_local_out[p] (signal_dspin_clack_proc[p]); |
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[621] | 427 | |
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[628] | 428 | std::cout << " - CLA Coherence crossbar connected" << std::endl; |
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[621] | 429 | |
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| 430 | //////////////////////////////////// Processors |
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| 431 | for (size_t p = 0; p < nb_procs; p++) |
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| 432 | { |
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| 433 | proc[p]->p_clk (this->p_clk); |
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| 434 | proc[p]->p_resetn (this->p_resetn); |
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| 435 | proc[p]->p_vci (signal_vci_ini_proc[p]); |
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| 436 | proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]); |
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| 437 | proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]); |
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| 438 | proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]); |
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[628] | 439 | |
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| 440 | for ( size_t j = 0 ; j < 6 ; j++) |
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[621] | 441 | { |
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[628] | 442 | if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_irq[4*p + j]); |
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| 443 | else proc[p]->p_irq[j] (signal_false); |
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[621] | 444 | } |
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| 445 | } |
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| 446 | |
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| 447 | std::cout << " - Processors connected" << std::endl; |
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| 448 | |
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| 449 | ///////////////////////////////////// XICU |
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| 450 | xicu->p_clk (this->p_clk); |
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| 451 | xicu->p_resetn (this->p_resetn); |
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| 452 | xicu->p_vci (signal_vci_tgt_xicu); |
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[628] | 453 | |
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| 454 | for (size_t i = 0 ; i < 16 ; i++) |
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[621] | 455 | { |
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[628] | 456 | xicu->p_irq[i] (signal_proc_irq[i]); |
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[621] | 457 | } |
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| 458 | |
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[628] | 459 | for (size_t i = 0; i < 16; i++) |
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[621] | 460 | { |
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[628] | 461 | if ((x_id == 0) and (y_id == 0)) // cluster (0,0) |
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[621] | 462 | { |
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[628] | 463 | if (i == 8) xicu->p_hwi[i] (signal_irq_memc); |
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| 464 | else if (i == 9) xicu->p_hwi[i] (signal_irq_bdev); |
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| 465 | else if (i == 10) xicu->p_hwi[i] (signal_irq_mtty); |
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| 466 | else xicu->p_hwi[i] (signal_false); |
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[621] | 467 | } |
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[628] | 468 | else // other clusters |
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[621] | 469 | { |
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[732] | 470 | if (i == 8) xicu->p_hwi[i] (signal_irq_memc); |
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[628] | 471 | else xicu->p_hwi[i] (signal_false); |
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[621] | 472 | } |
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| 473 | } |
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| 474 | |
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| 475 | std::cout << " - XICU connected" << std::endl; |
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| 476 | |
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| 477 | //////////////////////////////////////////////// MEMC |
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| 478 | memc->p_clk (this->p_clk); |
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| 479 | memc->p_resetn (this->p_resetn); |
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| 480 | memc->p_irq (signal_irq_memc); |
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| 481 | memc->p_vci_ixr (signal_vci_xram); |
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| 482 | memc->p_vci_tgt (signal_vci_tgt_memc); |
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| 483 | memc->p_dspin_p2m (signal_dspin_p2m_memc); |
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| 484 | memc->p_dspin_m2p (signal_dspin_m2p_memc); |
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| 485 | memc->p_dspin_clack (signal_dspin_clack_memc); |
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| 486 | |
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| 487 | std::cout << " - MEMC connected" << std::endl; |
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| 488 | |
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| 489 | /////////////////////////////////////////////// XRAM |
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| 490 | xram->p_clk (this->p_clk); |
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| 491 | xram->p_resetn (this->p_resetn); |
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| 492 | xram->p_vci (signal_vci_xram); |
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| 493 | |
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| 494 | std::cout << " - XRAM connected" << std::endl; |
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| 495 | |
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[628] | 496 | /////////////////////////////// Extra Components in cluster(0,0) |
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[621] | 497 | |
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[628] | 498 | if ((x_id == 0) and (y_id == 0)) |
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[621] | 499 | { |
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| 500 | // BDEV |
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| 501 | bdev->p_clk (this->p_clk); |
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| 502 | bdev->p_resetn (this->p_resetn); |
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| 503 | bdev->p_irq (signal_irq_bdev); |
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| 504 | bdev->p_vci_target (signal_vci_tgt_bdev); |
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| 505 | bdev->p_vci_initiator (signal_vci_ini_bdev); |
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| 506 | |
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| 507 | std::cout << " - BDEV connected" << std::endl; |
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| 508 | |
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[628] | 509 | // MTTY (single channel) |
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[621] | 510 | mtty->p_clk (this->p_clk); |
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| 511 | mtty->p_resetn (this->p_resetn); |
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| 512 | mtty->p_vci (signal_vci_tgt_mtty); |
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[628] | 513 | mtty->p_irq[0] (signal_irq_mtty); |
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[621] | 514 | |
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| 515 | std::cout << " - MTTY connected" << std::endl; |
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[628] | 516 | } |
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[621] | 517 | } // end constructor |
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| 518 | |
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| 519 | |
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| 520 | |
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| 521 | template<size_t dspin_cmd_width, |
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| 522 | size_t dspin_rsp_width, |
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| 523 | typename vci_param_int, |
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| 524 | typename vci_param_ext> TsarLetiCluster<dspin_cmd_width, |
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| 525 | dspin_rsp_width, |
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| 526 | vci_param_int, |
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| 527 | vci_param_ext>::~TsarLetiCluster() { |
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| 528 | |
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[628] | 529 | dealloc_elems<DspinInput<dspin_cmd_width> > (p_cmd_in, 4); |
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| 530 | dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cmd_out, 4); |
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[621] | 531 | |
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[628] | 532 | dealloc_elems<DspinInput<dspin_rsp_width> > (p_rsp_in, 4); |
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| 533 | dealloc_elems<DspinOutput<dspin_rsp_width> >(p_rsp_out, 4); |
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| 534 | |
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| 535 | dealloc_elems<DspinInput<dspin_cmd_width> > (p_m2p_in, 4); |
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| 536 | dealloc_elems<DspinOutput<dspin_cmd_width> >(p_m2p_out, 4); |
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| 537 | |
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| 538 | dealloc_elems<DspinInput<dspin_rsp_width> > (p_p2m_in, 4); |
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| 539 | dealloc_elems<DspinOutput<dspin_rsp_width> >(p_p2m_out, 4); |
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| 540 | |
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| 541 | dealloc_elems<DspinInput<dspin_cmd_width> > (p_cla_in, 4); |
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| 542 | dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cla_out, 4); |
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| 543 | |
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[692] | 544 | for (size_t p = 0; p < m_nprocs ; p++) |
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[621] | 545 | { |
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[692] | 546 | if ( proc[p] ) delete proc[p]; |
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[621] | 547 | } |
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| 548 | |
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| 549 | delete memc; |
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| 550 | delete xram; |
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| 551 | delete xicu; |
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[628] | 552 | delete xbar_cmd; |
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| 553 | delete xbar_m2p; |
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| 554 | delete xbar_p2m; |
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| 555 | delete xbar_cla; |
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[621] | 556 | delete router_cmd; |
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| 557 | delete router_rsp; |
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[628] | 558 | delete router_m2p; |
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| 559 | delete router_p2m; |
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| 560 | delete router_cla; |
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[692] | 561 | delete wi_gate; |
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| 562 | delete wt_gate; |
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[628] | 563 | |
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| 564 | if ( bdev ) |
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[621] | 565 | { |
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| 566 | delete bdev; |
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[628] | 567 | } |
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| 568 | |
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| 569 | if ( mtty ) |
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| 570 | { |
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[621] | 571 | delete mtty; |
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| 572 | } |
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| 573 | } |
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| 574 | |
---|
| 575 | |
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| 576 | }} |
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| 577 | |
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| 578 | // Local Variables: |
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| 579 | // tab-width: 4 |
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| 580 | // c-basic-offset: 4 |
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| 581 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 582 | // indent-tabs-mode: nil |
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| 583 | // End: |
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| 584 | |
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| 585 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 586 | |
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| 587 | |
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| 588 | |
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