Context Navigation

source: trunk/platforms/tsar_generic_mwmr/arch.py @ 979

Last change on this file since 979 was 975, checked in by cfuguet, 10 years ago

Update arch.py scripts to support the new mapping.py version

In this new version, the addIrq() function takes as a supplementary argument the instance of the interrupt generating peripheral.

Property svn:executable set to *

File size: 19.0 KB

Rev	Line
[956]	1	#!/usr/bin/env python
	2
	3	from math import log, ceil
	4	from mapping import *
	5
	6	##################################################################################
	7	# file : arch.py (for the tsar_generic_mwmr architecture)
	8	# date : may 2014
	9	# author : Alain Greiner
	10	##################################################################################
	11	# This file contains a mapping generator for the "tsar_generic_mwmr" platform.
	12	# This includes both the hardware architecture (clusters, processors, peripherals,
	13	# physical space segmentation) and the mapping of all boot and kernel objects
	14	# (global vsegs).
	15	#
	16	# This platform includes 6 external peripherals, accessible through an IOB
	17	# components located in cluster [0,0] or in cluster [x_size-1, y_size-1].
	18	# Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA, PIC.
	19	#
	20	# All clusters contain (nb_procs) processors, one L2 cache, one XCU, and
	21	# one MWMR-DMA controller.
	22	#
	23	# The "constructor" parameters are:
	24	# - x_size : number of clusters in a row
	25	# - y_size : number of clusters in a column
	26	# - nb_procs : number of processors per cluster
	27	# - nb_ttys : number of TTY channels
	28	# - fbf_width : frame_buffer width = frame_buffer heigth
	29	#
	30	# The other hardware parameters are:
	31	# - nb_nics : number of NIC channels
	32	# - nb_cmas : number of CMA channels
	33	# - x_io : cluster_io x coordinate
	34	# - y_io : cluster_io y coordinate
	35	# - x_width : number of bits for x coordinate
	36	# - y_width : number of bits for y coordinate
	37	# - paddr_width : number of bits for physical address
	38	# - irq_per_proc : number of input IRQs per processor
	39	# - use_ramdisk : use a ramdisk when True
	40	# - vseg_increment : address increment for replicated peripherals
	41	#
	42	# Regarding the boot and kernel vsegs mapping :
	43	# - We use one big physical page (2 Mbytes) for the preloader and the four
	44	# boot vsegs, all allocated in cluster[0,0].
	45	# - We use one big page per cluster for the replicated kernel code vsegs.
	46	# - We use one big page in cluster[0][0] for the kernel data vseg.
	47	# - We use one big page per cluster for the distributed kernel heap vsegs.
	48	# - We use one big page per cluster for the distributed ptab vsegs.
	49	# - We use small physical pages (4 Kbytes) per cluster for the schedulers.
	50	# - We use one big page for each external peripheral in IO cluster,
	51	# - We use one small page per cluster for each internal peripheral.
	52	##################################################################################
	53
	54	########################
	55	def arch( x_size = 2,
	56	y_size = 2,
	57	nb_procs = 2,
	58	nb_ttys = 1,
[975]	59	fbf_width = 128,
	60	ioc_type = 'BDV' ):
[956]	61
	62	### define architecture constants
	63
	64	nb_nics = 1
	65	nb_cmas = 2
	66	x_io = 0
	67	y_io = 0
	68	x_width = 4
	69	y_width = 4
	70	p_width = 4
	71	paddr_width = 40
	72	irq_per_proc = 4
	73	use_ramdisk = False
	74	peri_increment = 0x10000 # distributed peripherals vbase address increment
	75
	76	### parameters checking
	77
	78	assert( nb_procs <= (1 << p_width) )
	79
	80	assert( (x_size == 1) or (x_size == 2) or (x_size == 4)
	81	or (x_size == 8) or (x_size == 16) )
	82
	83	assert( (y_size == 1) or (y_size == 2) or (y_size == 4)
	84	or (y_size == 8) or (y_size == 16) )
	85
	86	assert( (nb_ttys >= 1) and (nb_ttys <= 8) )
	87
	88	assert( ((x_io == 0) and (y_io == 0)) or
	89	((x_io == x_size-1) and (y_io == y_size-1)) )
	90
	91	### define type and name
	92
	93	platform_type = 'tsar_mwmr'
	94	platform_name = '%s_%d_%d_%d' % ( platform_type, x_size, y_size , nb_procs )
	95
	96	### define physical segments replicated in all clusters
	97
	98	ram_base = 0x0000000000
	99	ram_size = 0x1000000 # 16 Mbytes
	100
	101	xcu_base = 0x00B0000000
	102	xcu_size = 0x1000 # 4 Kbytes
	103
	104	mwr_base = 0x00B1000000
	105	mwr_size = 0x1000 # 4 Kbytes
	106
	107	mmc_base = 0x00B2000000
	108	mmc_size = 0x1000 # 4 Kbytes
	109
	110	### define physical segments for external peripherals
	111	## These segments are only defined in cluster_io
	112
	113	bdv_base = 0x00B3000000
	114	bdv_size = 0x1000 # 4kbytes
	115
	116	tty_base = 0x00B4000000
	117	tty_size = 0x4000 # 16 Kbytes
	118
	119	nic_base = 0x00B5000000
	120	nic_size = 0x80000 # 512 kbytes
	121
	122	cma_base = 0x00B6000000
	123	cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics
	124
	125	fbf_base = 0x00B7000000
	126	fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes
	127
	128	pic_base = 0x00B8000000
	129	pic_size = 0x1000 # 4 Kbytes
	130
	131	iob_base = 0x00BE000000
	132	iob_size = 0x1000 # 4 bytes
	133
	134	rom_base = 0x00BFC00000
	135	rom_size = 0x4000 # 16 Kbytes
	136
	137	### define bootloader vsegs base addresses and sizes
	138	### We want to pack these 4 vsegs in the same big page
	139	### => boot cost is one BIG page in cluster[0][0]
	140
	141	boot_mapping_vbase = 0x00000000 # ident
	142	boot_mapping_size = 0x00080000 # 512 Kbytes
	143
	144	boot_code_vbase = 0x00080000 # ident
	145	boot_code_size = 0x00040000 # 256 Kbytes
	146
	147	boot_data_vbase = 0x000C0000 # ident
	148	boot_data_size = 0x000C0000 # 768 Kbytes
	149
	150	boot_stack_vbase = 0x00180000 # ident
	151	boot_stack_size = 0x00080000 # 512 Kbytes
	152
	153	### define kernel vsegs base addresses and sizes
	154	### code, init, ptab, heap & sched vsegs are replicated in all clusters.
	155	### data & uncdata vsegs are only mapped in cluster[0][0].
	156
	157	kernel_code_vbase = 0x80000000
	158	kernel_code_size = 0x00100000 # 1 Mbytes per cluster
	159
	160	kernel_init_vbase = 0x80100000
	161	kernel_init_size = 0x00100000 # 1 Mbytes per cluster
	162
	163	kernel_data_vbase = 0x90000000
	164	kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0,0]
	165
	166	kernel_ptab_vbase = 0xE0000000
	167	kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster
	168
	169	kernel_heap_vbase = 0xD0000000
	170	kernel_heap_size = 0x00200000 # 2 Mbytes per cluster
	171
	172	kernel_sched_vbase = 0xA0000000
	173	kernel_sched_size = 0x00002000*nb_procs # 8 Kbytes per proc per cluster
	174
	175	#########################
	176	### create mapping
	177	#########################
	178
	179	mapping = Mapping( name = platform_name,
	180	x_size = x_size,
	181	y_size = y_size,
	182	nprocs = nb_procs,
	183	x_width = x_width,
	184	y_width = y_width,
	185	p_width = p_width,
	186	paddr_width = paddr_width,
	187	coherence = True,
	188	irq_per_proc = irq_per_proc,
	189	use_ramdisk = use_ramdisk,
	190	x_io = x_io,
	191	y_io = y_io,
	192	peri_increment = peri_increment,
	193	ram_base = ram_base,
	194	ram_size = ram_size )
	195
	196
	197	#############################
	198	### Hardware Components
	199	#############################
	200
	201	for x in xrange( x_size ):
	202	for y in xrange( y_size ):
	203	cluster_xy = (x << y_width) + y;
	204	offset = cluster_xy << (paddr_width - x_width - y_width)
	205
	206	### components replicated in all clusters
	207	ram = mapping.addRam( 'RAM', base = ram_base + offset,
	208	size = ram_size )
	209
	210	mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset,
	211	size = mmc_size, ptype = 'MMC' )
	212
	213	mwr = mapping.addPeriph( 'MWR', base = mwr_base + offset,
	214	size = mwr_size, ptype = 'MWR', subtype = 'GCD',
	215	arg0 = 2, arg1 = 1, arg2 = 1, arg3 = 0 )
	216
	217	xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset,
	218	size = xcu_size, ptype = 'XCU',
	219	channels = nb_procs * irq_per_proc,
	220	arg0 = 32, arg1 = 32, arg2 = 32, arg3 = 16 )
	221
[975]	222	mapping.addIrq( xcu, index = 0, src = mmc,
	223	isrtype = 'ISR_MMC' )
	224	mapping.addIrq( xcu, index = 1, src = mwr,
	225	isrtype = 'ISR_MWR' , channel = 2 )
[956]	226
	227	for p in xrange ( nb_procs ):
	228	mapping.addProc( x, y, p )
	229
	230	### external peripherals in cluster_io
	231	if ( (x==x_io) and (y==y_io) ):
	232
	233	iob = mapping.addPeriph( 'IOB', base = iob_base + offset, size = iob_size,
	234	ptype = 'IOB' )
	235
	236	bdv = mapping.addPeriph( 'BDV', base = bdv_base + offset, size = bdv_size,
	237	ptype = 'IOC', subtype = 'BDV' )
	238
	239	tty = mapping.addPeriph( 'TTY', base = tty_base + offset, size = tty_size,
	240	ptype = 'TTY', channels = nb_ttys )
	241
	242	nic = mapping.addPeriph( 'NIC', base = nic_base + offset, size = nic_size,
	243	ptype = 'NIC', channels = nb_nics )
	244
	245	cma = mapping.addPeriph( 'CMA', base = cma_base + offset, size = cma_size,
	246	ptype = 'CMA', channels = nb_cmas )
	247
	248	fbf = mapping.addPeriph( 'FBF', base = fbf_base + offset, size = fbf_size,
	249	ptype = 'FBF', arg0 = fbf_width, arg1 = fbf_width )
	250
	251	rom = mapping.addPeriph( 'ROM', base = rom_base + offset, size = rom_size,
	252	ptype = 'ROM' )
	253
	254	pic = mapping.addPeriph( 'PIC', base = pic_base + offset, size = pic_size,
	255	ptype = 'PIC', channels = 32 )
	256
[975]	257	mapping.addIrq( pic, index = 0, src = nic,
	258	isrtype = 'ISR_NIC_RX', channel = 0 )
	259	mapping.addIrq( pic, index = 1, src = nic,
	260	isrtype = 'ISR_NIC_RX', channel = 1 )
[956]	261
[975]	262	mapping.addIrq( pic, index = 2, src = nic,
	263	isrtype = 'ISR_NIC_TX', channel = 0 )
	264	mapping.addIrq( pic, index = 3, src = nic,
	265	isrtype = 'ISR_NIC_TX', channel = 1 )
[956]	266
[975]	267	mapping.addIrq( pic, index = 4, src = cma,
	268	isrtype = 'ISR_CMA', channel = 0 )
	269	mapping.addIrq( pic, index = 5, src = cma,
	270	isrtype = 'ISR_CMA', channel = 1 )
	271	mapping.addIrq( pic, index = 6, src = cma,
	272	isrtype = 'ISR_CMA', channel = 2 )
	273	mapping.addIrq( pic, index = 7, src = cma,
	274	isrtype = 'ISR_CMA', channel = 3 )
[956]	275
[975]	276	mapping.addIrq( pic, index = 8, src = bdv,
	277	isrtype = 'ISR_BDV', channel = 0 )
[956]	278
[975]	279	mapping.addIrq( pic, index = 16, src = tty,
	280	isrtype = 'ISR_TTY_RX', channel = 0 )
	281	mapping.addIrq( pic, index = 17, src = tty,
	282	isrtype = 'ISR_TTY_RX', channel = 1 )
	283	mapping.addIrq( pic, index = 18, src = tty,
	284	isrtype = 'ISR_TTY_RX', channel = 2 )
	285	mapping.addIrq( pic, index = 19, src = tty,
	286	isrtype = 'ISR_TTY_RX', channel = 3 )
	287	mapping.addIrq( pic, index = 20, src = tty,
	288	isrtype = 'ISR_TTY_RX', channel = 4 )
	289	mapping.addIrq( pic, index = 21, src = tty,
	290	isrtype = 'ISR_TTY_RX', channel = 5 )
	291	mapping.addIrq( pic, index = 22, src = tty,
	292	isrtype = 'ISR_TTY_RX', channel = 6 )
	293	mapping.addIrq( pic, index = 23, src = tty,
	294	isrtype = 'ISR_TTY_RX', channel = 7 )
[956]	295
	296
	297	####################################
	298	### Boot & Kernel vsegs mapping
	299	####################################
	300
	301	### global vsegs for boot_loader
	302	### we want to pack those 4 vsegs in the same big page
	303	### => same flags CXW_ / identity mapping / non local / big page
	304
	305	mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size,
	306	'CXW_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM',
	307	identity = True , local = False, big = True )
	308
	309	mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size,
	310	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
	311	identity = True , local = False, big = True )
	312
	313	mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size,
	314	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
	315	identity = True , local = False, big = True )
	316
	317	mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size,
	318	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
	319	identity = True , local = False, big = True )
	320
	321	### global vseg kernel_data : big / non local
	322	### Only mapped in cluster[0][0]
	323	mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size,
	324	'CXW_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM',
	325	binpath = 'build/kernel/kernel.elf',
	326	local = False, big = True )
	327
	328	### global vsegs kernel_code, kernel_init : big / local
	329	### replicated in all clusters with the same name & same vbase
	330	for x in xrange( x_size ):
	331	for y in xrange( y_size ):
	332	mapping.addGlobal( 'seg_kernel_code', kernel_code_vbase, kernel_code_size,
	333	'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM',
	334	binpath = 'build/kernel/kernel.elf',
	335	local = True, big = True )
	336
	337	mapping.addGlobal( 'seg_kernel_init', kernel_init_vbase, kernel_init_size,
	338	'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM',
	339	binpath = 'build/kernel/kernel.elf',
	340	local = True, big = True )
	341
	342	### Global vsegs kernel_ptab_x_y : big / non local
	343	### one vseg per cluster: name indexed by (x,y)
	344	for x in xrange( x_size ):
	345	for y in xrange( y_size ):
	346	offset = ((x << y_width) + y) * kernel_ptab_size
	347	base = kernel_ptab_vbase + offset
	348	mapping.addGlobal( 'seg_kernel_ptab_%d_%d' %(x,y), base, kernel_ptab_size,
	349	'CXW_', vtype = 'PTAB', x = x, y = y, pseg = 'RAM',
	350	local = False , big = True )
	351
	352	### global vsegs kernel_sched_x_y : small / non local
	353	### one vseg per cluster with name indexed by (x,y)
	354	for x in xrange( x_size ):
	355	for y in xrange( y_size ):
	356	offset = ((x << y_width) + y) * kernel_sched_size
	357	mapping.addGlobal( 'seg_kernel_sched_%d_%d' %(x,y),
	358	kernel_sched_vbase + offset , kernel_sched_size,
	359	'C_W_', vtype = 'SCHED', x = x , y = y , pseg = 'RAM',
	360	local = False, big = False )
	361
	362	### global vsegs kernel_heap_x_y : big / non local
	363	### one vseg per cluster with name indexed by (x,y)
	364	for x in xrange( x_size ):
	365	for y in xrange( y_size ):
	366	offset = ((x << y_width) + y) * kernel_heap_size
	367	mapping.addGlobal( 'seg_kernel_heap_%d_%d' %(x,y),
	368	kernel_heap_vbase + offset , kernel_heap_size,
	369	'C_W_', vtype = 'HEAP', x = x , y = y , pseg = 'RAM',
	370	local = False, big = True )
	371
	372	### global vsegs for external peripherals : non local / big page
	373	mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_',
	374	vtype = 'PERI', x = 0, y = 0, pseg = 'IOB',
	375	local = False, big = True )
	376
	377	mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_',
	378	vtype = 'PERI', x = 0, y = 0, pseg = 'BDV',
	379	local = False, big = True )
	380
	381	mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_',
	382	vtype = 'PERI', x = 0, y = 0, pseg = 'TTY',
	383	local = False, big = True )
	384
	385	mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_',
	386	vtype = 'PERI', x = 0, y = 0, pseg = 'NIC',
	387	local = False, big = True )
	388
	389	mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_',
	390	vtype = 'PERI', x = 0, y = 0, pseg = 'CMA',
	391	local = False, big = True )
	392
	393	mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_',
	394	vtype = 'PERI', x = 0, y = 0, pseg = 'FBF',
	395	local = False, big = True )
	396
	397	mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_',
	398	vtype = 'PERI', x = 0, y = 0, pseg = 'PIC',
	399	local = False, big = True )
	400
	401	mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_',
	402	vtype = 'PERI', x = 0, y = 0, pseg = 'ROM',
	403	local = False, big = True )
	404
	405	### global vsegs for internal peripherals : non local / small pages
	406	### allocated in all clusters with name indexed by (x,y)
	407	### as vbase address is incremented by (cluster_xy * vseg_increment)
	408	for x in xrange( x_size ):
	409	for y in xrange( y_size ):
	410	offset = ((x << y_width) + y) * peri_increment
	411
	412	mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size,
	413	'__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU',
	414	local = False, big = False )
	415
	416	mapping.addGlobal( 'seg_mwr_%d_%d' %(x,y), mwr_base + offset, mwr_size,
	417	'__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MWR',
	418	local = False, big = False )
	419
	420	mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size,
	421	'__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC',
	422	local = False, big = False )
	423
	424	return mapping
	425
	426	################################# platform test ####################################
	427
	428	if __name__ == '__main__':
	429
	430	mapping = arch( x_size = 2,
	431	y_size = 2,
	432	nb_procs = 2 )
	433
	434	# print mapping.netbsd_dts()
	435
	436	print mapping.xml()
	437
	438	# print mapping.giet_vsegs()
	439
	440
	441	# Local Variables:
	442	# tab-width: 4;
	443	# c-basic-offset: 4;
	444	# c-file-offsets:((innamespace . 0)(inline-open . 0));
	445	# indent-tabs-mode: nil;
	446	# End:
	447	#
	448	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
	449

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
Plural-Forms: nplurals=2; plural=(n != 1)
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 8bit
Generated-By: Babel 2.8.0