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source: trunk/platforms/tsar_generic_mwmr/tsar_mwmr_cluster/caba/source/src/tsar_mwmr_cluster.cpp @ 956

Last change on this file since 956 was 956, checked in by alain, 9 years ago
Introducing the tsar_generic_mwmr platform, derived from tsar_generic_iob. In each cluster, the vci_multi_dma component is replaced by a vci_mwmr_dma component connected to a coproc_gcd coprocessor.
File size: 34.0 KB

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1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_mwmr_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_mwmr_cluster.h"
16
17	#define tmpl(x) \
18	template<typename vci_param_int , typename vci_param_ext,\
19	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
20	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
21	x TsarMwmrCluster<\
22	vci_param_int , vci_param_ext,\
23	dspin_int_cmd_width, dspin_int_rsp_width,\
24	dspin_ram_cmd_width, dspin_ram_rsp_width>
25
26	namespace soclib { namespace caba {
27
28	//////////////////////////////////////////////////////////////////////////
29	// Constructor
30	//////////////////////////////////////////////////////////////////////////
31	tmpl(/**/)::TsarMwmrCluster(
32	//////////////////////////////////////////////////////////////////////////
33	sc_module_name insname,
34	size_t nb_procs,
35	size_t x_id,
36	size_t y_id,
37	size_t xmax,
38	size_t ymax,
39
40	const soclib::common::MappingTable &mt_int,
41	const soclib::common::MappingTable &mt_ram,
42	const soclib::common::MappingTable &mt_iox,
43
44	size_t x_width,
45	size_t y_width,
46	size_t l_width,
47	size_t p_width,
48
49	size_t int_memc_tgt_id, // local index
50	size_t int_xicu_tgt_id, // local index
51	size_t int_mwmr_tgt_id, // local index
52	size_t int_iobx_tgt_id, // local index
53
54	size_t int_proc_ini_id, // local index
55	size_t int_mwmr_ini_id, // local index
56	size_t int_iobx_ini_id, // local index
57
58	size_t ram_xram_tgt_id, // local index
59	size_t ram_memc_ini_id, // local index
60	size_t ram_iobx_ini_id, // local index
61
62	bool is_io, // (IOB)?
63	size_t iox_iobx_tgt_id, // local_index
64	size_t iox_iobx_ini_id, // local index
65
66	size_t memc_ways,
67	size_t memc_sets,
68	size_t l1_i_ways,
69	size_t l1_i_sets,
70	size_t l1_d_ways,
71	size_t l1_d_sets,
72	size_t xram_latency,
73	size_t xcu_nb_inputs,
74
75	const Loader &loader,
76
77	uint32_t frozen_cycles,
78	uint32_t debug_start_cycle,
79	bool memc_debug_ok,
80	bool proc_debug_ok,
81	bool iob_debug_ok )
82	: soclib::caba::BaseModule(insname),
83	p_clk("clk"),
84	p_resetn("resetn")
85	{
86	assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates");
87
88	size_t cluster_id = (x_id<<4) + y_id;
89
90	// Vectors of DSPIN ports for inter-cluster communications
91	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
92	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
93	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
94	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
95
96	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
97	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
98	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
99	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
100
101	// VCI ports from IOB to IOX network (only in IO clusters)
102	if ( is_io )
103	{
104	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
105	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
106	}
107
108	/////////////////////////////////////////////////////////////////////////////
109	// Hardware components
110	/////////////////////////////////////////////////////////////////////////////
111
112	//////////// PROCS
113	for (size_t p = 0; p < nb_procs; p++)
114	{
115	std::ostringstream s_proc;
116	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
117	proc[p] = new VciCcVCacheWrapper<vci_param_int,
118	dspin_int_cmd_width,
119	dspin_int_rsp_width,
120	GdbServer<Mips32ElIss> >(
121	s_proc.str().c_str(),
122	(cluster_id << p_width) + p, // GLOBAL PROC_ID
123	mt_int, // Mapping Table INT network
124	IntTab(cluster_id,p), // SRCID
125	(cluster_id << l_width) + p, // CC_GLOBAL_ID
126	8, // ITLB ways
127	8, // ITLB sets
128	8, // DTLB ways
129	8, // DTLB sets
130	l1_i_ways, l1_i_sets, 16, // ICACHE size
131	l1_d_ways, l1_d_sets, 16, // DCACHE size
132	4, // WBUF nlines
133	4, // WBUF nwords
134	x_width,
135	y_width,
136	frozen_cycles, // max frozen cycles
137	debug_start_cycle,
138	proc_debug_ok);
139	}
140
141	/////////// MEMC
142	std::ostringstream s_memc;
143	s_memc << "memc_" << x_id << "_" << y_id;
144	memc = new VciMemCache<vci_param_int,
145	vci_param_ext,
146	dspin_int_rsp_width,
147	dspin_int_cmd_width>(
148	s_memc.str().c_str(),
149	mt_int, // Mapping Table INT network
150	mt_ram, // Mapping Table RAM network
151	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
152	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
153	x_width, // number of bits for x coordinate
154	y_width, // number of bits for y coordinate
155	memc_ways, memc_sets, 16, // CACHE SIZE
156	3, // MAX NUMBER OF COPIES
157	4096, // HEAP SIZE
158	8, // TRANSACTION TABLE DEPTH
159	8, // UPDATE TABLE DEPTH
160	8, // INVALIDATE TABLE DEPTH
161	debug_start_cycle,
162	memc_debug_ok );
163
164	std::ostringstream s_wi_memc;
165	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
166	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
167	dspin_ram_cmd_width,
168	dspin_ram_rsp_width>(
169	s_wi_memc.str().c_str(),
170	x_width + y_width + l_width);
171
172	/////////// XICU
173	std::ostringstream s_xicu;
174	s_xicu << "xicu_" << x_id << "_" << y_id;
175	xicu = new VciXicu<vci_param_int>(
176	s_xicu.str().c_str(),
177	mt_int, // mapping table INT network
178	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
179	xcu_nb_inputs, // number of timer IRQs
180	xcu_nb_inputs, // number of hard IRQs
181	xcu_nb_inputs, // number of soft IRQs
182	16); // number of output IRQs
183
184	//////////// MWMR controller
185	std::ostringstream s_mwmr;
186	s_mwmr << "mwmr_" << x_id << "_" << y_id;
187	mwmr = new VciMwmrDma<vci_param_int>(
188	s_mwmr.str().c_str(),
189	mt_int,
190	IntTab(cluster_id, int_mwmr_ini_id), // SRCID
191	IntTab(cluster_id, int_mwmr_tgt_id), // TGTID
192	2, // nb to_coproc ports
193	1, // nb from_coproc ports
194	1, // nb config registers
195	0, // nb status registers
196	64 ); // burst size (bytes)
197
198	/////////// GCD coprocessor
199	std::ostringstream s_gcd;
200	s_gcd << "gcd_" << x_id << "_" << y_id;
201	gcd = new CoprocGcd(
202	s_gcd.str().c_str(),
203	64 ); // burst size (bytes)
204
205
206	/////////// Direct LOCAL_XBAR(S)
207	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
208	size_t nb_direct_targets = is_io ? 4 : 3;
209
210	std::ostringstream s_int_xbar_d;
211	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
212	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
213	s_int_xbar_d.str().c_str(),
214	mt_int, // mapping table
215	cluster_id, // cluster id
216	nb_direct_initiators, // number of local initiators
217	nb_direct_targets, // number of local targets
218	0 ); // default target
219
220	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
221	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
222	<< x_id << "_" << y_id;
223	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
224	dspin_int_cmd_width,
225	dspin_int_rsp_width>(
226	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
227	x_width + y_width + l_width);
228
229	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
230	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
231	<< x_id << "_" << y_id;
232	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
233	dspin_int_cmd_width,
234	dspin_int_rsp_width>(
235	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
236	x_width + y_width + l_width);
237
238	//////////// Coherence LOCAL_XBAR(S)
239	std::ostringstream s_int_xbar_m2p_c;
240	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
241	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
242	s_int_xbar_m2p_c.str().c_str(),
243	mt_int, // mapping table
244	x_id, y_id, // cluster coordinates
245	x_width, y_width, l_width, // several dests
246	1, // number of local sources
247	nb_procs, // number of local dests
248	2, 2, // fifo depths
249	true, // pseudo CMD
250	false, // no routing table
251	true ); // broacast
252
253	std::ostringstream s_int_xbar_p2m_c;
254	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
255	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
256	s_int_xbar_p2m_c.str().c_str(),
257	mt_int, // mapping table
258	x_id, y_id, // cluster coordinates
259	x_width, y_width, 0, // only one dest
260	nb_procs, // number of local sources
261	1, // number of local dests
262	2, 2, // fifo depths
263	false, // pseudo RSP
264	false, // no routing table
265	false ); // no broacast
266
267	std::ostringstream s_int_xbar_clack_c;
268	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
269	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
270	s_int_xbar_clack_c.str().c_str(),
271	mt_int, // mapping table
272	x_id, y_id, // cluster coordinates
273	x_width, y_width, l_width,
274	1, // number of local sources
275	nb_procs, // number of local targets
276	1, 1, // fifo depths
277	true, // CMD
278	false, // no routing table
279	false); // broadcast
280
281	////////////// INT ROUTER(S)
282	std::ostringstream s_int_router_cmd;
283	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id;
284	int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>(
285	s_int_router_cmd.str().c_str(),
286	x_id,y_id, // coordinate in the mesh
287	x_width, y_width, // x & y fields width
288	3, // nb virtual channels
289	4,4); // input & output fifo depths
290
291	std::ostringstream s_int_router_rsp;
292	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id;
293	int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>(
294	s_int_router_rsp.str().c_str(),
295	x_id,y_id, // router coordinates in mesh
296	x_width, y_width, // x & y fields width
297	2, // nb virtual channels
298	4,4); // input & output fifo depths
299
300	////////////// XRAM
301	std::ostringstream s_xram;
302	s_xram << "xram_" << x_id << "_" << y_id;
303	xram = new VciSimpleRam<vci_param_ext>(
304	s_xram.str().c_str(),
305	IntTab(cluster_id, ram_xram_tgt_id),
306	mt_ram,
307	loader,
308	xram_latency);
309
310	std::ostringstream s_wt_xram;
311	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
312	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
313	dspin_ram_cmd_width,
314	dspin_ram_rsp_width>(
315	s_wt_xram.str().c_str(),
316	x_width + y_width + l_width);
317
318	///////////// RAM ROUTER(S)
319	std::ostringstream s_ram_router_cmd;
320	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
321	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
322	s_ram_router_cmd.str().c_str(),
323	x_id, y_id, // router coordinates in mesh
324	x_width, // x field width in first flit
325	y_width, // y field width in first flit
326	4, 4); // input & output fifo depths
327
328	std::ostringstream s_ram_router_rsp;
329	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
330	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
331	s_ram_router_rsp.str().c_str(),
332	x_id, y_id, // coordinates in mesh
333	x_width, // x field width in first flit
334	y_width, // y field width in first flit
335	4, 4); // input & output fifo depths
336
337
338	////////////////////// I/O CLUSTER ONLY ///////////////////////
339	if ( is_io )
340	{
341	/////////// IO_BRIDGE
342	std::ostringstream s_iob;
343	s_iob << "iob_" << x_id << "_" << y_id;
344	iob = new VciIoBridge<vci_param_int,
345	vci_param_ext>(
346	s_iob.str().c_str(),
347	mt_ram, // EXT network maptab
348	mt_int, // INT network maptab
349	mt_iox, // IOX network maptab
350	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
351	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
352	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
353	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
354	16, // cache line words
355	8, // IOTLB ways
356	8, // IOTLB sets
357	debug_start_cycle,
358	iob_debug_ok );
359
360	std::ostringstream s_iob_ram_wi;
361	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
362	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
363	dspin_ram_cmd_width,
364	dspin_ram_rsp_width>(
365	s_iob_ram_wi.str().c_str(),
366	vci_param_int::S);
367
368	std::ostringstream s_ram_xbar_cmd;
369	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
370	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
371	s_ram_xbar_cmd.str().c_str(), // name
372	mt_ram, // mapping table
373	x_id, y_id, // x, y
374	x_width, y_width, l_width, // x_width, y_width, l_width
375	2, 0, // local inputs, local outputs
376	2, 2, // in fifo, out fifo depths
377	true, // is cmd ?
378	false, // use routing table ?
379	false); // support broadcast ?
380
381	std::ostringstream s_ram_xbar_rsp;
382	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
383	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
384	s_ram_xbar_rsp.str().c_str(), // name
385	mt_ram, // mapping table
386	x_id, y_id, // x, y
387	x_width, y_width, l_width, // x_width, y_width, l_width
388	0, 2, // local inputs, local outputs
389	2, 2, // in fifo, out fifo depths
390	false, // is cmd ?
391	true, // use routing table ?
392	false); // support broadcast ?
393	} // end if IO
394
395	////////////////////////////////////
396	// Connections are defined here
397	////////////////////////////////////
398
399	// on coherence network : local srcid[proc] in [0...nb_procs-1]
400	// : local srcid[memc] = nb_procs
401
402	//////////////////////// internal CMD & RSP routers
403	int_router_cmd->p_clk (this->p_clk);
404	int_router_cmd->p_resetn (this->p_resetn);
405	int_router_rsp->p_clk (this->p_clk);
406	int_router_rsp->p_resetn (this->p_resetn);
407
408	for (int i = 0; i < 4; i++)
409	{
410	for(int k = 0; k < 3; k++)
411	{
412	int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]);
413	int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]);
414	}
415
416	for(int k = 0; k < 2; k++)
417	{
418	int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]);
419	int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]);
420	}
421	}
422
423	// local ports
424	int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d);
425	int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c);
426	int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c);
427	int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d);
428	int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c);
429	int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c);
430
431	int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d);
432	int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c);
433	int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d);
434	int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c);
435
436	std::cout << " - Connected : CMD & RSP routers" << std::endl;
437
438	///////////////////// CMD DSPIN local crossbar direct
439	int_xbar_d->p_clk (this->p_clk);
440	int_xbar_d->p_resetn (this->p_resetn);
441	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
442	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
443
444	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
445	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
446	int_xbar_d->p_to_target[int_mwmr_tgt_id] (signal_int_vci_tgt_mwmr);
447	int_xbar_d->p_to_initiator[int_mwmr_ini_id] (signal_int_vci_ini_mwmr);
448	for (size_t p = 0; p < nb_procs; p++)
449	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
450
451	if ( is_io )
452	{
453	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
454	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
455	}
456
457	int_wi_gate_d->p_clk (this->p_clk);
458	int_wi_gate_d->p_resetn (this->p_resetn);
459	int_wi_gate_d->p_vci (signal_int_vci_l2g);
460	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
461	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
462
463	int_wt_gate_d->p_clk (this->p_clk);
464	int_wt_gate_d->p_resetn (this->p_resetn);
465	int_wt_gate_d->p_vci (signal_int_vci_g2l);
466	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
467	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
468
469	////////////////////// M2P DSPIN local crossbar coherence
470	int_xbar_m2p_c->p_clk (this->p_clk);
471	int_xbar_m2p_c->p_resetn (this->p_resetn);
472	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
473	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
474	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
475	for (size_t p = 0; p < nb_procs; p++)
476	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
477
478	////////////////////////// P2M DSPIN local crossbar coherence
479	int_xbar_p2m_c->p_clk (this->p_clk);
480	int_xbar_p2m_c->p_resetn (this->p_resetn);
481	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
482	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
483	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
484	for (size_t p = 0; p < nb_procs; p++)
485	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
486
487	////////////////////// CLACK DSPIN local crossbar coherence
488	int_xbar_clack_c->p_clk (this->p_clk);
489	int_xbar_clack_c->p_resetn (this->p_resetn);
490	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
491	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
492	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
493	for (size_t p = 0; p < nb_procs; p++)
494	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
495
496	std::cout << " - Connected : local crossbars" << std::endl;
497
498	/////////////////////////////////// GCD coprocessor
499	gcd->p_clk (this->p_clk);
500	gcd->p_resetn (this->p_resetn);
501	gcd->p_opa (signal_to_coproc[0]);
502	gcd->p_opb (signal_to_coproc[1]);
503	gcd->p_res (signal_from_coproc[0]);
504	gcd->p_config (signal_config_coproc[0]);
505
506	std::cout << " - Connected : GCD" << std::endl;
507
508	/////////////////////////////////// MWMR controler
509	mwmr->p_clk (this->p_clk);
510	mwmr->p_resetn (this->p_resetn);
511	mwmr->p_vci_target (signal_int_vci_tgt_mwmr);
512	mwmr->p_vci_initiator (signal_int_vci_ini_mwmr);
513	mwmr->p_to_coproc[0] (signal_to_coproc[0]);
514	mwmr->p_to_coproc[1] (signal_to_coproc[1]);
515	mwmr->p_from_coproc[0] (signal_from_coproc[0]);
516	mwmr->p_config[0] (signal_config_coproc[0]);
517	mwmr->p_irq (signal_irq_mwmr);
518
519	std::cout << " - Connected : MWMR" << std::endl;
520
521	//////////////////////////////////// Processors
522	for (size_t p = 0; p < nb_procs; p++)
523	{
524	proc[p]->p_clk (this->p_clk);
525	proc[p]->p_resetn (this->p_resetn);
526	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
527	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
528	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
529	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
530
531	for ( size_t j = 0 ; j < 6 ; j++)
532	{
533	if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]);
534	else proc[p]->p_irq[j] (signal_false);
535	}
536	}
537
538	std::cout << " - Connected : processors" << std::endl;
539
540	///////////////////////////////////// XICU
541	xicu->p_clk (this->p_clk);
542	xicu->p_resetn (this->p_resetn);
543	xicu->p_vci (signal_int_vci_tgt_xicu);
544	for ( size_t i=0 ; i < 16 ; i++)
545	{
546	xicu->p_irq[i] (signal_proc_it[i]);
547	}
548	for ( size_t i=0 ; i < xcu_nb_inputs ; i++)
549	{
550	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
551	else if ( i == 1 ) xicu->p_hwi[i] (signal_irq_mwmr);
552	else xicu->p_hwi[i] (signal_false);
553	}
554
555	std::cout << " - Connected : XCU" << std::endl;
556
557	///////////////////////////////////// MEMC
558	memc->p_clk (this->p_clk);
559	memc->p_resetn (this->p_resetn);
560	memc->p_vci_ixr (signal_ram_vci_ini_memc);
561	memc->p_vci_tgt (signal_int_vci_tgt_memc);
562	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
563	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
564	memc->p_dspin_clack (signal_int_dspin_clack_memc);
565	memc->p_irq (signal_irq_memc);
566
567	// wrapper to RAM network
568	memc_ram_wi->p_clk (this->p_clk);
569	memc_ram_wi->p_resetn (this->p_resetn);
570	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
571	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
572	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
573
574	std::cout << " - Connected : MEMC" << std::endl;
575
576	//////////////////////////////////// XRAM
577	xram->p_clk (this->p_clk);
578	xram->p_resetn (this->p_resetn);
579	xram->p_vci (signal_ram_vci_tgt_xram);
580
581	// wrapper to RAM network
582	xram_ram_wt->p_clk (this->p_clk);
583	xram_ram_wt->p_resetn (this->p_resetn);
584	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
585	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
586	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
587
588	//////////////////////////// RAM network CMD & RSP routers
589	ram_router_cmd->p_clk (this->p_clk);
590	ram_router_cmd->p_resetn (this->p_resetn);
591	ram_router_rsp->p_clk (this->p_clk);
592	ram_router_rsp->p_resetn (this->p_resetn);
593	for( size_t n=0 ; n<4 ; n++)
594	{
595	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
596	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
597	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
598	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
599	}
600
601	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
602	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
603
604	if ( is_io )
605	{
606	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
607	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
608	}
609	else
610	{
611	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
612	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
613	}
614
615	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
616	if ( is_io )
617	{
618	// IO bridge
619	iob->p_clk (this->p_clk);
620	iob->p_resetn (this->p_resetn);
621	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
622	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
623	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
624	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
625	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
626
627	// initiator wrapper to RAM network
628	iob_ram_wi->p_clk (this->p_clk);
629	iob_ram_wi->p_resetn (this->p_resetn);
630	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
631	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
632	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
633
634	// crossbar between MEMC and IOB to RAM network
635	ram_xbar_cmd->p_clk (this->p_clk);
636	ram_xbar_cmd->p_resetn (this->p_resetn);
637	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
638	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
639	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
640	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
641
642	ram_xbar_rsp->p_clk (this->p_clk);
643	ram_xbar_rsp->p_resetn (this->p_resetn);
644	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
645	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
646	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
647	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
648	}
649
650	SC_METHOD(init);
651
652	} // end constructor
653
654	tmpl(void)::init()
655	{
656	signal_ram_dspin_cmd_false.write = false;
657	signal_ram_dspin_rsp_false.read = true;
658	} // end init
659
660	}}
661
662
663	// Local Variables:
664	// tab-width: 3
665	// c-basic-offset: 3
666	// c-file-offsets:((innamespace . 0)(inline-open . 0))
667	// indent-tabs-mode: nil
668	// End:
669
670	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
671

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Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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