[1012] | 1 | |
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| 2 | |
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| 3 | |
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| 4 | def hard_config(x, y, x_width, y_width, p, hard_config, protocol): |
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| 5 | |
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| 6 | ram_tgtid = 0 |
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| 7 | xcu_tgtid = 1 |
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| 8 | dma_tgtid = 2 |
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| 9 | tty_tgtid = 3 |
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| 10 | ioc_tgtid = 4 |
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| 11 | nic_tgtid = 5 |
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| 12 | rom_tgtid = 6 |
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| 13 | cma_tgtid = 7 |
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| 14 | sim_tgtid = 8 |
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| 15 | fbf_tgtid = 9 |
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| 16 | |
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| 17 | nb_dma_channels = 1 |
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| 18 | nb_cma_channels = 0 |
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| 19 | nb_tty_channels = 4 |
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| 20 | nb_ioc_channels = 1 |
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| 21 | |
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| 22 | fbf_x_size = 1024 |
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| 23 | fbf_y_size = 1024 |
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| 24 | |
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| 25 | seg_rom_base = 0xbfc00000 |
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| 26 | seg_rom_size = 0x00100000 |
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| 27 | |
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| 28 | cluster_inc = 0x80000000 / (x * y) * 2 |
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| 29 | cluster_io_id = seg_rom_base >> (32 - x_width - y_width) |
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| 30 | cluster_io_inc = cluster_io_id * cluster_inc |
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| 31 | ram_max_size = 0x40000000 / (x * y) # 1 Go Max |
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| 32 | |
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| 33 | seg_ram_base = 0x00000000 |
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| 34 | seg_ram_size = min(0x10000000, ram_max_size) |
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| 35 | |
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| 36 | seg_xcu_base = (cluster_inc >> 1) + (xcu_tgtid << 19) |
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| 37 | seg_xcu_size = 0x00001000 # 4Ko |
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| 38 | |
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| 39 | seg_dma_base = (cluster_inc >> 1) + (dma_tgtid << 19) |
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| 40 | seg_dma_size = 0x00001000 * nb_dma_channels |
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| 41 | |
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| 42 | def periph_address(tgtid): |
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| 43 | return (cluster_inc >> 1) + cluster_io_inc + (tgtid << 19) |
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| 44 | |
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| 45 | seg_ioc_base = periph_address(ioc_tgtid); |
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| 46 | seg_ioc_size = 0x00001000 |
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| 47 | |
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| 48 | seg_tty_base = periph_address(tty_tgtid) |
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| 49 | seg_tty_size = 0x00001000 |
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| 50 | |
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| 51 | seg_fbf_base = periph_address(fbf_tgtid) |
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| 52 | seg_fbf_size = fbf_x_size * fbf_y_size * 2 |
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| 53 | |
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| 54 | seg_nic_base = periph_address(nic_tgtid) |
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| 55 | seg_nic_size = 0x00080000 |
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| 56 | |
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| 57 | seg_cma_base = periph_address(cma_tgtid) |
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| 58 | seg_cma_size = 0x00004000 * nb_cma_channels |
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| 59 | |
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| 60 | seg_sim_base = periph_address(sim_tgtid) |
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| 61 | seg_sim_size = 0x00001000 |
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| 62 | |
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| 63 | header = ''' |
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| 64 | #ifndef _HARD_CONFIG_H_ |
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| 65 | #define _HARD_CONFIG_H_ |
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| 66 | |
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| 67 | /* Generated from run_simus.py */ |
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| 68 | |
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| 69 | /* General platform parameters */ |
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| 70 | |
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| 71 | #define X_SIZE %(x_size)d |
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| 72 | #define Y_SIZE %(y_size)d |
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| 73 | #define X_WIDTH %(x_width)d |
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| 74 | #define Y_WIDTH %(y_width)d |
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| 75 | #define P_WIDTH 4 |
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| 76 | #define X_IO 0 |
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| 77 | #define Y_IO 0 |
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| 78 | #define NB_PROCS_MAX %(proc_per_clus)d |
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| 79 | #define IRQ_PER_PROCESSOR 4 |
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| 80 | #define RESET_ADDRESS 0x%(seg_rom_base)x |
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| 81 | |
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| 82 | |
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| 83 | /* Peripherals */ |
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| 84 | |
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| 85 | #define RAM_TGTID %(ram_tgtid)d |
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| 86 | #define XCU_TGTID %(xcu_tgtid)d |
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| 87 | #define DMA_TGTID %(dma_tgtid)d |
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| 88 | #define TTY_TGTID %(tty_tgtid)d |
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| 89 | #define IOC_TGTID %(ioc_tgtid)d |
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| 90 | #define NIC_TGTID %(nic_tgtid)d |
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| 91 | #define ROM_TGTID %(rom_tgtid)d |
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| 92 | #define CMA_TGTID %(cma_tgtid)d |
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| 93 | #define SIM_TGTID %(sim_tgtid)d |
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| 94 | #define FBF_TGTID %(fbf_tgtid)d |
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| 95 | |
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| 96 | #define NB_TTY_CHANNELS %(nb_tty_channels)d |
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| 97 | #define NB_IOC_CHANNELS %(nb_ioc_channels)d |
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| 98 | #define NB_NIC_CHANNELS 0 |
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| 99 | #define NB_CMA_CHANNELS %(nb_cma_channels)d |
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| 100 | #define NB_TIM_CHANNELS 0 |
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| 101 | #define NB_DMA_CHANNELS %(nb_dma_channels)d |
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| 102 | |
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| 103 | #define USE_XCU 1 |
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| 104 | #define USE_IOB 0 |
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| 105 | #define USE_PIC 0 |
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| 106 | #define USE_FBF 1 |
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| 107 | |
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| 108 | #define USE_IOC_BDV 1 |
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| 109 | #define USE_IOC_SDC 0 |
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| 110 | #define USE_IOC_HBA 0 |
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| 111 | #define USE_IOC_RDK 0 |
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| 112 | |
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| 113 | #define FBF_X_SIZE %(fbf_x_size)d |
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| 114 | #define FBF_Y_SIZE %(fbf_y_size)d |
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| 115 | |
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| 116 | |
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| 117 | /* base addresses and sizes for physical segments */ |
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| 118 | |
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| 119 | #define SEG_RAM_BASE 0x%(seg_ram_base)x |
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| 120 | #define SEG_RAM_SIZE 0x%(seg_ram_size)x |
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| 121 | |
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| 122 | #define SEG_CMA_BASE 0x0 // Component requires a multiple of 4K |
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| 123 | #define SEG_CMA_SIZE 0x0 |
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| 124 | |
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| 125 | #define SEG_DMA_BASE 0x%(seg_dma_base)x |
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| 126 | #define SEG_DMA_SIZE 0x%(seg_dma_size)x |
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| 127 | |
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| 128 | #define SEG_FBF_BASE 0x%(seg_fbf_base)x |
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| 129 | #define SEG_FBF_SIZE 0x%(seg_fbf_size)x |
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| 130 | |
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| 131 | #define SEG_ICU_BASE 0xffffffff |
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| 132 | #define SEG_ICU_SIZE 0x0 |
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| 133 | |
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| 134 | #define SEG_IOB_BASE 0xffffffff |
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| 135 | #define SEG_IOB_SIZE 0x0 |
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| 136 | |
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| 137 | #define SEG_IOC_BASE 0x%(seg_ioc_base)x |
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| 138 | #define SEG_IOC_SIZE 0x%(seg_ioc_size)x |
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| 139 | |
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| 140 | #define SEG_MMC_BASE 0xffffffff |
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| 141 | #define SEG_MMC_SIZE 0x0 |
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| 142 | |
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| 143 | #define SEG_MWR_BASE 0xffffffff |
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| 144 | #define SEG_MWR_SIZE 0x0 |
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| 145 | |
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| 146 | #define SEG_ROM_BASE 0x%(seg_rom_base)x |
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| 147 | #define SEG_ROM_SIZE 0x%(seg_rom_size)x |
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| 148 | |
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| 149 | #define SEG_SIM_BASE 0x%(seg_sim_base)x |
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| 150 | #define SEG_SIM_SIZE 0x%(seg_sim_size)x |
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| 151 | |
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| 152 | #define SEG_NIC_BASE 0x%(seg_nic_base)x |
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| 153 | #define SEG_NIC_SIZE 0x%(seg_nic_size)x |
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| 154 | |
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| 155 | #define SEG_PIC_BASE 0xffffffff |
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| 156 | #define SEG_PIC_SIZE 0x0 |
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| 157 | |
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| 158 | #define SEG_TIM_BASE 0xffffffff |
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| 159 | #define SEG_TIM_SIZE 0x0 |
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| 160 | |
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| 161 | #define SEG_TTY_BASE 0x%(seg_tty_base)x |
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| 162 | #define SEG_TTY_SIZE 0x%(seg_tty_size)x |
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| 163 | |
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| 164 | #define SEG_XCU_BASE 0x%(seg_xcu_base)x |
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| 165 | #define SEG_XCU_SIZE 0x%(seg_xcu_size)x |
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| 166 | |
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| 167 | #define SEG_RDK_BASE 0xffffffff |
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| 168 | #define SEG_RDK_SIZE 0x0 |
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| 169 | |
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| 170 | ''' % dict(x_size = x, y_size = y, x_width = x_width, y_width = y_width, |
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| 171 | proc_per_clus = p, |
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| 172 | nb_tty_channels = nb_tty_channels, |
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| 173 | nb_ioc_channels = nb_ioc_channels, |
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| 174 | nb_cma_channels = nb_cma_channels, |
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| 175 | nb_dma_channels = nb_dma_channels, |
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| 176 | fbf_x_size = fbf_x_size, fbf_y_size = fbf_y_size, |
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| 177 | ram_tgtid = ram_tgtid, |
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| 178 | xcu_tgtid = xcu_tgtid, |
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| 179 | dma_tgtid = dma_tgtid, |
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| 180 | tty_tgtid = tty_tgtid, |
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| 181 | ioc_tgtid = ioc_tgtid, |
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| 182 | nic_tgtid = nic_tgtid, |
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| 183 | rom_tgtid = rom_tgtid, |
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| 184 | cma_tgtid = cma_tgtid, |
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| 185 | sim_tgtid = sim_tgtid, |
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| 186 | fbf_tgtid = fbf_tgtid, |
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| 187 | seg_ram_base = seg_ram_base, |
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| 188 | seg_ram_size = seg_ram_size, |
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| 189 | seg_dma_base = seg_dma_base, |
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| 190 | seg_dma_size = seg_dma_size, |
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| 191 | seg_fbf_base = seg_fbf_base, |
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| 192 | seg_fbf_size = seg_fbf_size, |
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| 193 | seg_ioc_base = seg_ioc_base, |
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| 194 | seg_ioc_size = seg_ioc_size, |
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| 195 | seg_rom_base = seg_rom_base, |
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| 196 | seg_rom_size = seg_rom_size, |
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| 197 | seg_sim_base = seg_sim_base, |
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| 198 | seg_sim_size = seg_sim_size, |
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| 199 | seg_nic_base = seg_nic_base, |
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| 200 | seg_nic_size = seg_nic_size, |
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| 201 | seg_tty_base = seg_tty_base, |
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| 202 | seg_tty_size = seg_tty_size, |
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| 203 | seg_xcu_base = seg_xcu_base, |
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| 204 | seg_xcu_size = seg_xcu_size) |
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| 205 | |
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| 206 | if protocol == 'wtidl': |
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| 207 | header += '#define WT_IDL\n' |
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| 208 | |
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| 209 | header += '#endif //_HD_CONFIG_H\n' |
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| 210 | |
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| 211 | file = open(hard_config, 'w') |
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| 212 | file.write(header) |
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| 213 | file.close() |
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| 214 | |
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| 215 | |
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| 216 | if __name__ == "__main__": |
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| 217 | if len(sys.argv) != 6: |
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| 218 | print "Usage: %s <x> <y> <p> <hard_config-filename> <protocol>" % argv[0] |
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| 219 | print "with:" |
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| 220 | print "<x>: number of clusters in X" |
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| 221 | print "<y>: number of clusters in Y" |
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| 222 | print "<p>: number of processors per clusters" |
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| 223 | sys.exit(0) |
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| 224 | |
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| 225 | x = argv[1] |
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| 226 | y = argv[2] |
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| 227 | p = argv[3] |
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| 228 | hard_config_filename = argv[4] |
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| 229 | protocol = argv[5] |
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| 230 | |
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| 231 | hard_config(x, y, p, hard_config_filename, protocol) |
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| 232 | |
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| 233 | |
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