| 1 |
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| 2 | RAM_TGTID = 0
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| 3 | XCU_TGTID = 1
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| 4 | DMA_TGTID = 2
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| 5 | TTY_TGTID = 3
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| 6 | IOC_TGTID = 4
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| 7 | NIC_TGTID = 5
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| 8 | ROM_TGTID = 6
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| 9 | CMA_TGTID = 7
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| 10 | SIM_TGTID = 8
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| 11 | FBF_TGTID = 9
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| 12 |
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| 13 | DMA_SIZE = 0X00001000
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| 14 | XCU_SIZE = 0X00001000
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| 15 | TTY_SIZE = 0X00001000
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| 16 | IOC_SIZE = 0X00001000
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| 17 | NIC_SIZE = 0x00080000
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| 18 | ROM_SIZE = 0x00100000
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| 19 | CMA_SIZE = 0x00004000
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| 20 | SIM_SIZE = 0X00001000
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| 21 | FBF_SIZE = 0X00200000
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| 22 |
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| 23 | RAM_BASE = 0x0
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| 24 | RAM_MAX_TOTAL_SIZE = 0x10000000
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| 25 | RAM_MAX_CLUST_SIZE = 0x10000000
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| 26 |
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| 27 |
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| 28 | NB_DMA_CHANNELS = 1
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| 29 | NB_CMA_CHANNELS = 0
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| 30 | NB_TTY_CHANNELS = 4
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| 31 | NB_IOC_CHANNELS = 1
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| 32 | TTY_CHANNEL_SIZE = 0X00000010
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| 33 |
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| 34 | FBF_X_SIZE = 1024
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| 35 | FBF_Y_SIZE = 1024
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| 36 |
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| 37 |
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| 38 | P_WIDTH = 4
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| 39 |
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| 40 | ADDR_WIDTH = 32
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| 41 | BOOT_ADDR = 0xbfc00000
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| 42 |
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| 43 | OUTPUT_IRQ_PER_PROC = 4
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| 44 |
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| 45 |
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| 46 | def get_x_io(x_width, y_width):
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| 47 | return BOOT_ADDR >> (ADDR_WIDTH - x_width)
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| 48 |
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| 49 | def get_y_io(x_width, y_width):
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| 50 | return (BOOT_ADDR >> (ADDR_WIDTH - x_width - y_width)) & ((1 << y_width) - 1)
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| 51 |
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| 52 |
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| 53 | def replicated_periph_base_addr(x_width, y_width, tgtid):
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| 54 | demi_cluster_inc = (1 << (ADDR_WIDTH - 1)) >> (x_width + y_width)
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| 55 | return demi_cluster_inc + (tgtid << 19)
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| 56 |
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| 57 | def replicated_periph_addr(x, y, x_width, y_width, base_addr):
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| 58 | cid = x * (1 << y_width) + y
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| 59 | demi_cluster_inc = (1 << (ADDR_WIDTH - 1)) >> (x_width + y_width)
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| 60 | return demi_cluster_inc * 2 * cid + base_addr
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| 61 |
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| 62 |
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| 63 |
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| 64 | def periph_addr(x_width, y_width, tgtid):
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| 65 | demi_cluster_inc = (1 << (ADDR_WIDTH - 1)) >> (x_width + y_width)
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| 66 |
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| 67 | x_io = get_x_io(x_width, y_width)
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| 68 | y_io = get_y_io(x_width, y_width)
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| 69 | cluster_io_id = x_io * (1 << y_width) + y_io
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| 70 | cluster_io_offset = cluster_io_id * demi_cluster_inc * 2
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| 71 | return demi_cluster_inc + cluster_io_offset + (tgtid << 19)
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| 72 |
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| 73 |
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| 74 | def ram_size(x_width, y_width):
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| 75 | return min(RAM_MAX_TOTAL_SIZE >> (x_width + y_width), RAM_MAX_CLUST_SIZE)
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| 76 |
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| 77 |
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| 78 | def ram_addr(x, y, x_width, y_width):
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| 79 | cid = x * (1 << y_width) + y
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| 80 | demi_cluster_inc = (1 << (ADDR_WIDTH - 1)) >> (x_width + y_width)
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| 81 | return demi_cluster_inc * 2 * cid + RAM_BASE
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| 82 |
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