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source: trunk/platforms/tsar_generic_xbar/top.cpp @ 437

Last change on this file since 437 was 428, checked in by cfuguet, 12 years ago

Modification in tsar_generic_xbar:

Adapting the platform metadata files to new vci_mem_cache parameters

File size: 35.3 KB

Line
1	/////////////////////////////////////////////////////////////////////////
2	// File: top.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : may 2013
6	// This program is released under the GNU public license
7	/////////////////////////////////////////////////////////////////////////
8	// This file define a generic TSAR architecture.
9	// The physical address space is 40 bits.
10	//
11	// The number of clusters cannot be larger than 256.
12	// The number of processors per cluster cannot be larger than 8.
13	//
14	// - It uses four dspin_local_crossbar per cluster as local interconnect
15	// - It uses two virtual_dspin routers per cluster as global interconnect
16	// - It uses the vci_cc_vcache_wrapper
17	// - It uses the vci_mem_cache
18	// - It contains one vci_xicu per cluster.
19	// - It contains one vci_multi_dma per cluster.
20	// - It contains one vci_simple_ram per cluster to model the L3 cache.
21	//
22	// The communication between the MemCache and the Xram is 64 bits.
23	//
24	// All clusters are identical, but the cluster 0 (called io_cluster),
25	// contains 5 extra components:
26	// - the boot rom (BROM)
27	// - the disk controller (BDEV)
28	// - the multi-channel network controller (MNIC)
29	// - the multi-channel tty controller (MTTY)
30	// - the frame buffer controller (FBUF)
31	//
32	// It is build with one single component implementing a cluster,
33	// defined in files tsar_xbar_cluster.* (with * = cpp, h, sd)
34	//
35	// The IRQs are connected to XICUs as follow:
36	// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters.
37	// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters.
38	// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster.
39	// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster.
40	//
41	// Some hardware parameters are used when compiling the OS, and are used
42	// by this top.cpp file. They must be defined in the hard_config.h file :
43	// - CLUSTER_X : number of clusters in a row (power of 2)
44	// - CLUSTER_Y : number of clusters in a column (power of 2)
45	// - CLUSTER_SIZE : size of the segment allocated to a cluster
46	// - NB_PROCS_MAX : number of processors per cluster (power of 2)
47	// - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9)
48	// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16)
49	// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9)
50	//
51	// Some other hardware parameters are not used when compiling the OS,
52	// and can be directly defined in this top.cpp file:
53	// - XRAM_LATENCY : external ram latency
54	// - MEMC_WAYS : L2 cache number of ways
55	// - MEMC_SETS : L2 cache number of sets
56	// - L1_IWAYS
57	// - L1_ISETS
58	// - L1_DWAYS
59	// - L1_DSETS
60	// - FBUF_X_SIZE : width of frame buffer (pixels)
61	// - FBUF_Y_SIZE : heigth of frame buffer (lines)
62	// - BDEV_SECTOR_SIZE : block size for block drvice
63	// - BDEV_IMAGE_NAME : file pathname for block device
64	// - NIC_RX_NAME : file pathname for NIC received packets
65	// - NIC_TX_NAME : file pathname for NIC transmited packets
66	// - NIC_TIMEOUT : max number of cycles before closing a container
67	/////////////////////////////////////////////////////////////////////////
68	// General policy for 40 bits physical address decoding:
69	// All physical segments base addresses are multiple of 1 Mbytes
70	// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
71	// The (x_width + y_width) MSB bits (left aligned) define
72	// the cluster index, and the LADR bits define the local index:
73	// \| X_ID \| Y_ID \|---\| LADR \| OFFSET \|
74	// \|x_width\|y_width\|---\| 8 \| 24 \|
75	/////////////////////////////////////////////////////////////////////////
76	// General policy for 14 bits SRCID decoding:
77	// Each component is identified by (x_id, y_id, l_id) tuple.
78	// \| X_ID \| Y_ID \|---\| L_ID \|
79	// \|x_width\|y_width\|---\| 6 \|
80	/////////////////////////////////////////////////////////////////////////
81
82	#include <systemc>
83	#include <sys/time.h>
84	#include <iostream>
85	#include <sstream>
86	#include <cstdlib>
87	#include <cstdarg>
88	#include <stdint.h>
89
90	#include "gdbserver.h"
91	#include "mapping_table.h"
92	#include "tsar_xbar_cluster.h"
93	#include "alloc_elems.h"
94
95	///////////////////////////////////////////////////
96	// OS
97	///////////////////////////////////////////////////
98	#define USE_ALMOS 0
99
100	#define almos_bootloader_pathname "bootloader.bin"
101	#define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D"
102	#define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D"
103
104	///////////////////////////////////////////////////
105	// Parallelisation
106	///////////////////////////////////////////////////
107	#define USE_OPENMP 0
108
109	#if USE_OPENMP
110	#include <omp.h>
111	#endif
112
113	// cluster index (computed from x,y coordinates)
114	#define cluster(x,y) (y + CLUSTER_Y*x)
115
116	///////////////////////////////////////////////////////////
117	// DSPIN parameters
118	///////////////////////////////////////////////////////////
119
120	#define dspin_cmd_width 39
121	#define dspin_rsp_width 32
122
123	///////////////////////////////////////////////////////////
124	// VCI parameters
125	///////////////////////////////////////////////////////////
126
127	#define int_vci_cell_width 4
128	#define int_vci_plen_width 8
129	#define int_vci_address_width 40
130	#define int_vci_rerror_width 1
131	#define int_vci_clen_width 1
132	#define int_vci_rflag_width 1
133	#define int_vci_srcid_width 14
134	#define int_vci_pktid_width 4
135	#define int_vci_trdid_width 4
136	#define int_vci_wrplen_width 1
137
138	#define ext_vci_cell_width 8
139	#define ext_vci_plen_width 8
140	#define ext_vci_address_width 40
141	#define ext_vci_rerror_width 1
142	#define ext_vci_clen_width 1
143	#define ext_vci_rflag_width 1
144	#define ext_vci_srcid_width 14
145	#define ext_vci_pktid_width 4
146	#define ext_vci_trdid_width 4
147	#define ext_vci_wrplen_width 1
148
149	////////////////////////////////////////////////////////////
150	// Main Hardware Parameters values
151	//////////////////////i/////////////////////////////////////
152
153	#include "giet_vm/hard_config.h"
154
155	////////////////////////////////////////////////////////////
156	// Secondary Hardware Parameters
157	//////////////////////i/////////////////////////////////////
158
159	#define XRAM_LATENCY 0
160
161	#define MEMC_WAYS 16
162	#define MEMC_SETS 256
163
164	#define L1_IWAYS 4
165	#define L1_ISETS 64
166
167	#define L1_DWAYS 4
168	#define L1_DSETS 64
169
170	#define FBUF_X_SIZE 128
171	#define FBUF_Y_SIZE 128
172
173	#define BDEV_SECTOR_SIZE 512
174	#define BDEV_IMAGE_NAME "giet_vm/display/images.raw"
175
176	#define NIC_RX_NAME "giet_vm/nic/rx_packets.txt"
177	#define NIC_TX_NAME "giet_vm/nic/tx_packets.txt"
178	#define NIC_TIMEOUT 10000
179
180	////////////////////////////////////////////////////////////
181	// Software to be loaded in ROM & RAM
182	//////////////////////i/////////////////////////////////////
183
184	#define SOFT_NAME "giet_vm/soft.elf"
185
186	////////////////////////////////////////////////////////////
187	// DEBUG Parameters default values
188	//////////////////////i/////////////////////////////////////
189
190	#define MAX_FROZEN_CYCLES 10000
191
192	#define TRACE_MEMC_ID 1000000
193	#define TRACE_PROC_ID 1000000
194
195	/////////////////////////////////////////////////////////
196	// Physical segments definition
197	/////////////////////////////////////////////////////////
198	// There is 3 segments replicated in all clusters
199	// and 5 specific segments in the "IO" cluster
200	// (containing address 0xBF000000)
201	/////////////////////////////////////////////////////////
202
203	// specific segments in "IO" cluster : absolute physical address
204
205	#define BROM_BASE 0x00BFC00000
206	#define BROM_SIZE 0x0000100000 // 1 Mbytes
207
208	#define FBUF_BASE 0x00B2000000
209	#define FBUF_SIZE FBUF_X_SIZE * FBUF_Y_SIZE
210
211	#define BDEV_BASE 0x00B3000000
212	#define BDEV_SIZE 0x0000001000 // 4 Kbytes
213
214	#define MTTY_BASE 0x00B4000000
215	#define MTTY_SIZE 0x0000001000 // 4 Kbytes
216
217	#define MNIC_BASE 0x00B5000000
218	#define MNIC_SIZE 0x0000080000 // 512 Kbytes (for 8 channels)
219
220	// replicated segments : address is incremented by a cluster offset
221	// offset = cluster(x,y) << (address_width-x_width-y_width);
222
223	#define MEMC_BASE 0x0000000000
224	#define MEMC_SIZE 0x0010000000 // 256 Mbytes per cluster
225
226	#define XICU_BASE 0x00B0000000
227	#define XICU_SIZE 0x0000001000 // 4 Kbytes
228
229	#define MDMA_BASE 0x00B1000000
230	#define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel
231
232	////////////////////////////////////////////////////////////////////
233	// TGTID definition in direct space
234	// For all components: global TGTID = global SRCID = cluster_index
235	////////////////////////////////////////////////////////////////////
236
237	#define MEMC_TGTID 0
238	#define XICU_TGTID 1
239	#define MDMA_TGTID 2
240	#define MTTY_TGTID 3
241	#define FBUF_TGTID 4
242	#define BDEV_TGTID 5
243	#define BROM_TGTID 6
244	#define MNIC_TGTID 7
245
246	/////////////////////////////////
247	int _main(int argc, char *argv[])
248	{
249	using namespace sc_core;
250	using namespace soclib::caba;
251	using namespace soclib::common;
252
253	char soft_name[256] = SOFT_NAME; // pathname to binary code
254	size_t ncycles = 1000000000; // simulated cycles
255	char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image
256	char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file
257	char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file
258	ssize_t threads_nr = 1; // simulator's threads number
259	bool debug_ok = false; // trace activated
260	size_t debug_period = 1; // trace period
261	size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced
262	size_t debug_proc_id = TRACE_PROC_ID; // index of proc to be traced
263	uint32_t debug_from = 0; // trace start cycle
264	uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor
265	size_t cluster_io_id = 0; // index of cluster containing IOs
266
267	////////////// command line arguments //////////////////////
268	if (argc > 1)
269	{
270	for (int n = 1; n < argc; n = n + 2)
271	{
272	if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc))
273	{
274	ncycles = atoi(argv[n+1]);
275	}
276	else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
277	{
278	strcpy(soft_name, argv[n+1]);
279	}
280	else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
281	{
282	strcpy(disk_name, argv[n+1]);
283	}
284	else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
285	{
286	debug_ok = true;
287	debug_from = atoi(argv[n+1]);
288	}
289	else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) )
290	{
291	debug_memc_id = atoi(argv[n+1]);
292	assert( (debug_memc_id < (CLUSTER_X*CLUSTER_Y) ) &&
293	"debug_memc_id larger than XMAX * YMAX" );
294	}
295	else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) )
296	{
297	debug_proc_id = atoi(argv[n+1]);
298	assert( (debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) &&
299	"debug_proc_id larger than XMAX * YMAX * NB_PROCS" );
300	}
301	else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc))
302	{
303	threads_nr = atoi(argv[n+1]);
304	threads_nr = (threads_nr < 1) ? 1 : threads_nr;
305	}
306	else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc))
307	{
308	frozen_cycles = atoi(argv[n+1]);
309	}
310	else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc))
311	{
312	debug_period = atoi(argv[n+1]);
313	}
314	else
315	{
316	std::cout << " Arguments are (key,value) couples." << std::endl;
317	std::cout << " The order is not important." << std::endl;
318	std::cout << " Accepted arguments are :" << std::endl << std::endl;
319	std::cout << " -SOFT pathname_for_embedded_soft" << std::endl;
320	std::cout << " -DISK pathname_for_disk_image" << std::endl;
321	std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
322	std::cout << " -DEBUG debug_start_cycle" << std::endl;
323	std::cout << " -THREADS simulator's threads number" << std::endl;
324	std::cout << " -FROZEN max_number_of_lines" << std::endl;
325	std::cout << " -PERIOD number_of_cycles between trace" << std::endl;
326	std::cout << " -MEMCID index_memc_to_be_traced" << std::endl;
327	std::cout << " -PROCID index_proc_to_be_traced" << std::endl;
328	exit(0);
329	}
330	}
331	}
332
333	// checking hardware parameters
334	assert( ( (CLUSTER_X == 1) or (CLUSTER_X == 2) or (CLUSTER_X == 4) or
335	(CLUSTER_X == 8) or (CLUSTER_X == 16) ) and
336	"The CLUSTER_X parameter must be 1, 2, 4, 8 or 16" );
337
338	assert( ( (CLUSTER_Y == 1) or (CLUSTER_Y == 2) or (CLUSTER_Y == 4) or
339	(CLUSTER_Y == 8) or (CLUSTER_Y == 16) ) and
340	"The CLUSTER_Y parameter must be 1, 2, 4, 8 or 16" );
341
342	assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or
343	(NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and
344	"The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" );
345
346	assert( (NB_DMA_CHANNELS < 9) and
347	"The NB_DMA_CHANNELS parameter must be smaller than 9" );
348
349	assert( (NB_TTY_CHANNELS < 15) and
350	"The NB_TTY_CHANNELS parameter must be smaller than 15" );
351
352	assert( (NB_NIC_CHANNELS < 9) and
353	"The NB_NIC_CHANNELS parameter must be smaller than 9" );
354
355	assert( (int_vci_address_width == ext_vci_address_width) and
356	"address widths must be equal on internal & external networks" );
357
358	assert( (int_vci_address_width == 40) and
359	"VCI address width must be 40 bits" );
360
361	std::cout << std::endl;
362	std::cout << " - CLUSTER_X = " << CLUSTER_X << std::endl;
363	std::cout << " - CLUSTER_Y = " << CLUSTER_Y << std::endl;
364	std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl;
365	std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl;
366	std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl;
367	std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl;
368	std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;
369	std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;
370	std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;
371	std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;
372
373	std::cout << std::endl;
374
375	// Internal and External VCI parameters definition
376	typedef soclib::caba::VciParams<int_vci_cell_width,
377	int_vci_plen_width,
378	int_vci_address_width,
379	int_vci_rerror_width,
380	int_vci_clen_width,
381	int_vci_rflag_width,
382	int_vci_srcid_width,
383	int_vci_pktid_width,
384	int_vci_trdid_width,
385	int_vci_wrplen_width> vci_param_int;
386
387	typedef soclib::caba::VciParams<ext_vci_cell_width,
388	ext_vci_plen_width,
389	ext_vci_address_width,
390	ext_vci_rerror_width,
391	ext_vci_clen_width,
392	ext_vci_rflag_width,
393	ext_vci_srcid_width,
394	ext_vci_pktid_width,
395	ext_vci_trdid_width,
396	ext_vci_wrplen_width> vci_param_ext;
397
398	#if USE_OPENMP
399	omp_set_dynamic(false);
400	omp_set_num_threads(threads_nr);
401	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
402	#endif
403
404	// Define parameters depending on mesh size
405	size_t x_width;
406	size_t y_width;
407
408	if (CLUSTER_X == 1) x_width = 0;
409	else if (CLUSTER_X == 2) x_width = 1;
410	else if (CLUSTER_X <= 4) x_width = 2;
411	else if (CLUSTER_X <= 8) x_width = 3;
412	else x_width = 4;
413
414	if (CLUSTER_Y == 1) y_width = 0;
415	else if (CLUSTER_Y == 2) y_width = 1;
416	else if (CLUSTER_Y <= 4) y_width = 2;
417	else if (CLUSTER_Y <= 8) y_width = 3;
418	else y_width = 4;
419
420	/////////////////////
421	// Mapping Tables
422	/////////////////////
423
424	// internal network
425	MappingTable maptabd(int_vci_address_width,
426	IntTab(x_width + y_width, 16 - x_width - y_width),
427	IntTab(x_width + y_width, int_vci_srcid_width - x_width - y_width),
428	0x00FF000000);
429
430	for (size_t x = 0; x < CLUSTER_X; x++)
431	{
432	for (size_t y = 0; y < CLUSTER_Y; y++)
433	{
434	sc_uint<int_vci_address_width> offset;
435	offset = (sc_uint<int_vci_address_width>)cluster(x,y)
436	<< (int_vci_address_width-x_width-y_width);
437
438	std::ostringstream sh;
439	sh << "seg_memc_" << x << "_" << y;
440	maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE,
441	IntTab(cluster(x,y),MEMC_TGTID), true));
442
443	std::ostringstream si;
444	si << "seg_xicu_" << x << "_" << y;
445	maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE,
446	IntTab(cluster(x,y),XICU_TGTID), false));
447
448	std::ostringstream sd;
449	sd << "seg_mdma_" << x << "_" << y;
450	maptabd.add(Segment(sd.str(), MDMA_BASE+offset, MDMA_SIZE,
451	IntTab(cluster(x,y),MDMA_TGTID), false));
452
453	if ( cluster(x,y) == cluster_io_id )
454	{
455	maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE,
456	IntTab(cluster(x,y),MTTY_TGTID), false));
457	maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE,
458	IntTab(cluster(x,y),FBUF_TGTID), false));
459	maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE,
460	IntTab(cluster(x,y),BDEV_TGTID), false));
461	maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE,
462	IntTab(cluster(x,y),MNIC_TGTID), false));
463	maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE,
464	IntTab(cluster(x,y),BROM_TGTID), true));
465	}
466	}
467	}
468	std::cout << maptabd << std::endl;
469
470	// external network
471	MappingTable maptabx(ext_vci_address_width,
472	IntTab(x_width+y_width),
473	IntTab(x_width+y_width),
474	0xFFFF000000ULL);
475
476	for (size_t x = 0; x < CLUSTER_X; x++)
477	{
478	for (size_t y = 0; y < CLUSTER_Y ; y++)
479	{
480
481	sc_uint<ext_vci_address_width> offset;
482	offset = (sc_uint<ext_vci_address_width>)cluster(x,y)
483	<< (ext_vci_address_width-x_width-y_width);
484
485	std::ostringstream sh;
486	sh << "x_seg_memc_" << x << "_" << y;
487
488	maptabx.add(Segment(sh.str(), MEMC_BASE+offset,
489	MEMC_SIZE, IntTab(cluster(x,y)), false));
490	}
491	}
492	std::cout << maptabx << std::endl;
493
494	////////////////////
495	// Signals
496	///////////////////
497
498	sc_clock signal_clk("clk");
499	sc_signal<bool> signal_resetn("resetn");
500
501	enum {
502	NORTH = VirtualDspinRouter<dspin_cmd_width>::NORTH,
503	SOUTH = VirtualDspinRouter<dspin_cmd_width>::SOUTH,
504	EAST = VirtualDspinRouter<dspin_cmd_width>::EAST,
505	WEST = VirtualDspinRouter<dspin_cmd_width>::WEST,
506	LOCAL = VirtualDspinRouter<dspin_cmd_width>::LOCAL
507	};
508
509	// Horizontal inter-clusters DSPIN signals
510	DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_inc =
511	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2);
512	DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_dec =
513	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2);
514	DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_inc =
515	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2);
516	DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_dec =
517	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2);
518
519	// Vertical inter-clusters DSPIN signals
520	DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_inc =
521	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2);
522	DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_dec =
523	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2);
524	DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_inc =
525	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2);
526	DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_dec =
527	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2);
528
529	// Mesh boundaries DSPIN signals
530	DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_in =
531	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4);
532	DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_out =
533	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4);
534	DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_in =
535	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4);
536	DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_out =
537	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4);
538
539
540	////////////////////////////
541	// Loader
542	////////////////////////////
543
544	#if USE_ALMOS
545	soclib::common::Loader loader(almos_bootloader_pathname,
546	almos_archinfo_pathname,
547	almos_kernel_pathname);
548	#else
549	soclib::common::Loader loader(soft_name);
550	#endif
551
552	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
553	proc_iss::set_loader(loader);
554
555	////////////////////////////
556	// Clusters construction
557	////////////////////////////
558
559	TsarXbarCluster<dspin_cmd_width,
560	dspin_rsp_width,
561	vci_param_int,
562	vci_param_ext>* clusters[CLUSTER_X][CLUSTER_Y];
563
564	#if USE_OPENMP
565	#pragma omp parallel
566	{
567	#pragma omp for
568	#endif
569	for(size_t i = 0; i < (CLUSTER_X * CLUSTER_Y); i++)
570	{
571	size_t x = i / CLUSTER_Y;
572	size_t y = i % CLUSTER_Y;
573
574	#if USE_OPENMP
575	#pragma omp critical
576	{
577	#endif
578
579	std::ostringstream sc;
580	sc << "cluster_" << x << "_" << y;
581	clusters[x][y] = new TsarXbarCluster<dspin_cmd_width,
582	dspin_rsp_width,
583	vci_param_int,
584	vci_param_ext>
585	(
586	sc.str().c_str(),
587	NB_PROCS_MAX,
588	NB_TTY_CHANNELS,
589	NB_DMA_CHANNELS,
590	x,
591	y,
592	cluster(x,y),
593	maptabd,
594	maptabx,
595	x_width,
596	y_width,
597	int_vci_srcid_width - x_width - y_width, // l_id width,
598	MEMC_TGTID,
599	XICU_TGTID,
600	MDMA_TGTID,
601	FBUF_TGTID,
602	MTTY_TGTID,
603	BROM_TGTID,
604	MNIC_TGTID,
605	BDEV_TGTID,
606	MEMC_WAYS,
607	MEMC_SETS,
608	L1_IWAYS,
609	L1_ISETS,
610	L1_DWAYS,
611	L1_DSETS,
612	XRAM_LATENCY,
613	(cluster(x,y) == cluster_io_id),
614	FBUF_X_SIZE,
615	FBUF_Y_SIZE,
616	disk_name,
617	BDEV_SECTOR_SIZE,
618	NB_NIC_CHANNELS,
619	nic_rx_name,
620	nic_tx_name,
621	NIC_TIMEOUT,
622	loader,
623	frozen_cycles,
624	debug_from ,
625	debug_ok and (cluster(x,y) == debug_memc_id),
626	debug_ok and (cluster(x,y) == debug_proc_id)
627	);
628
629	std::cout << std::endl;
630	std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl;
631	std::cout << std::endl;
632
633	#if USE_OPENMP
634	} // end critical
635	#endif
636	} // end for
637	#if USE_OPENMP
638	}
639	#endif
640
641	///////////////////////////////////////////////////////////////
642	// Net-list
643	///////////////////////////////////////////////////////////////
644
645	// Clock & RESET
646	for (size_t x = 0; x < (CLUSTER_X); x++){
647	for (size_t y = 0; y < CLUSTER_Y; y++){
648	clusters[x][y]->p_clk (signal_clk);
649	clusters[x][y]->p_resetn (signal_resetn);
650	}
651	}
652
653	// Inter Clusters horizontal connections
654	if (CLUSTER_X > 1){
655	for (size_t x = 0; x < (CLUSTER_X-1); x++){
656	for (size_t y = 0; y < CLUSTER_Y; y++){
657	for (size_t k = 0; k < 2; k++){
658	clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]);
659	clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]);
660	clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]);
661	clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]);
662	clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]);
663	clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]);
664	clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]);
665	clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]);
666	}
667	}
668	}
669	}
670	std::cout << std::endl << "Horizontal connections established" << std::endl;
671
672	// Inter Clusters vertical connections
673	if (CLUSTER_Y > 1) {
674	for (size_t y = 0; y < (CLUSTER_Y-1); y++){
675	for (size_t x = 0; x < CLUSTER_X; x++){
676	for (size_t k = 0; k < 2; k++){
677	clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]);
678	clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]);
679	clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]);
680	clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]);
681	clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]);
682	clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]);
683	clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]);
684	clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]);
685	}
686	}
687	}
688	}
689	std::cout << "Vertical connections established" << std::endl;
690
691	// East & West boundary cluster connections
692	for (size_t y = 0; y < CLUSTER_Y; y++)
693	{
694	for (size_t k = 0; k < 2; k++)
695	{
696	clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]);
697	clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]);
698	clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]);
699	clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]);
700
701	clusters[CLUSTER_X-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[CLUSTER_X-1][y][k][EAST]);
702	clusters[CLUSTER_X-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[CLUSTER_X-1][y][k][EAST]);
703	clusters[CLUSTER_X-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[CLUSTER_X-1][y][k][EAST]);
704	clusters[CLUSTER_X-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[CLUSTER_X-1][y][k][EAST]);
705	}
706	}
707
708	// North & South boundary clusters connections
709	for (size_t x = 0; x < CLUSTER_X; x++)
710	{
711	for (size_t k = 0; k < 2; k++)
712	{
713	clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]);
714	clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]);
715	clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]);
716	clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]);
717
718	clusters[x][CLUSTER_Y-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][CLUSTER_Y-1][k][NORTH]);
719	clusters[x][CLUSTER_Y-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][CLUSTER_Y-1][k][NORTH]);
720	clusters[x][CLUSTER_Y-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][CLUSTER_Y-1][k][NORTH]);
721	clusters[x][CLUSTER_Y-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][CLUSTER_Y-1][k][NORTH]);
722	}
723	}
724	std::cout << "North, South, West, East connections established" << std::endl;
725	std::cout << std::endl;
726
727
728	////////////////////////////////////////////////////////
729	// Simulation
730	///////////////////////////////////////////////////////
731
732	sc_start(sc_core::sc_time(0, SC_NS));
733	signal_resetn = false;
734
735	// network boundaries signals
736	for (size_t x = 0; x < CLUSTER_X ; x++){
737	for (size_t y = 0; y < CLUSTER_Y ; y++){
738	for (size_t k = 0; k < 2; k++){
739	for (size_t a = 0; a < 4; a++){
740	signal_dspin_false_cmd_in [x][y][k][a].write = false;
741	signal_dspin_false_cmd_in [x][y][k][a].read = true;
742	signal_dspin_false_cmd_out[x][y][k][a].write = false;
743	signal_dspin_false_cmd_out[x][y][k][a].read = true;
744
745	signal_dspin_false_rsp_in [x][y][k][a].write = false;
746	signal_dspin_false_rsp_in [x][y][k][a].read = true;
747	signal_dspin_false_rsp_out[x][y][k][a].write = false;
748	signal_dspin_false_rsp_out[x][y][k][a].read = true;
749	}
750	}
751	}
752	}
753
754	sc_start(sc_core::sc_time(1, SC_NS));
755	signal_resetn = true;
756
757	for (size_t n = 1; n < ncycles; n++)
758	{
759	// Monitor a specific address for L1 & L2 caches
760	//clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL);
761	//clusters[1][0]->memc->copies_monitor(0x800002C000ULL);
762
763	if (debug_ok and (n > debug_from) and (n % debug_period == 0))
764	{
765	std::cout << "****************** cycle " << std::dec << n ;
766	std::cout << " ************************************************" << std::endl;
767
768	// trace proc[debug_proc_id]
769	if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) )
770	{
771	size_t l = debug_proc_id % NB_PROCS_MAX ;
772	size_t y = (debug_proc_id / NB_PROCS_MAX) % CLUSTER_Y ;
773	size_t x = debug_proc_id / (CLUSTER_Y * NB_PROCS_MAX) ;
774
775	std::ostringstream vci_signame;
776	vci_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
777	std::ostringstream p2m_signame;
778	p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ;
779	std::ostringstream m2p_signame;
780	m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ;
781	std::ostringstream cmd_signame;
782	cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ;
783	std::ostringstream rsp_signame;
784	rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ;
785
786	clusters[x][y]->proc[l]->print_trace();
787	clusters[x][y]->wi_proc[l]->print_trace();
788	clusters[x][y]->signal_vci_ini_proc[l].print_trace(vci_signame.str());
789	clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str());
790	clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str());
791	clusters[x][y]->signal_dspin_cmd_proc_i[l].print_trace(cmd_signame.str());
792	clusters[x][y]->signal_dspin_rsp_proc_i[l].print_trace(rsp_signame.str());
793
794	clusters[x][y]->xbar_rsp_d->print_trace();
795	clusters[x][y]->xbar_cmd_d->print_trace();
796	clusters[x][y]->signal_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD");
797	clusters[x][y]->signal_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD");
798	clusters[x][y]->signal_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP");
799	clusters[x][y]->signal_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP");
800	}
801
802	// trace memc[debug_memc_id]
803	if ( debug_memc_id < (CLUSTER_X * CLUSTER_Y) )
804	{
805	size_t x = debug_memc_id / CLUSTER_Y;
806	size_t y = debug_memc_id % CLUSTER_Y;
807
808	std::ostringstream smemc;
809	smemc << "[SIG]MEMC_" << x << "_" << y;
810	std::ostringstream sxram;
811	sxram << "[SIG]XRAM_" << x << "_" << y;
812	std::ostringstream sm2p;
813	sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ;
814	std::ostringstream sp2m;
815	sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ;
816	std::ostringstream cmd_signame;
817	cmd_signame << "[SIG]MEMC_" << x << "_" << y << " CMD" ;
818	std::ostringstream rsp_signame;
819	rsp_signame << "[SIG]MEMC_" << x << "_" << y << " RSP" ;
820
821	clusters[x][y]->memc->print_trace();
822	clusters[x][y]->wt_memc->print_trace();
823	clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
824	clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
825	clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str());
826	clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str());
827	clusters[x][y]->signal_dspin_cmd_memc_t.print_trace(cmd_signame.str());
828	clusters[x][y]->signal_dspin_rsp_memc_t.print_trace(rsp_signame.str());
829	}
830
831	// trace replicated peripherals
832	// clusters[1][1]->mdma->print_trace();
833	// clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1");
834	// clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1");
835
836
837	// trace external peripherals
838	size_t io_x = cluster_io_id / CLUSTER_Y;
839	size_t io_y = cluster_io_id % CLUSTER_Y;
840
841	clusters[io_x][io_y]->brom->print_trace();
842	clusters[io_x][io_y]->wt_brom->print_trace();
843	clusters[io_x][io_y]->signal_vci_tgt_brom.print_trace("[SIG]BROM");
844	clusters[io_x][io_y]->signal_dspin_cmd_brom_t.print_trace("[SIG]BROM CMD");
845	clusters[io_x][io_y]->signal_dspin_rsp_brom_t.print_trace("[SIG]BROM RSP");
846
847	// clusters[io_x][io_y]->bdev->print_trace();
848	// clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT");
849	// clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI");
850	}
851
852	sc_start(sc_core::sc_time(1, SC_NS));
853	}
854	return EXIT_SUCCESS;
855	}
856
857	int sc_main (int argc, char *argv[])
858	{
859	try {
860	return _main(argc, argv);
861	} catch (std::exception &e) {
862	std::cout << e.what() << std::endl;
863	} catch (...) {
864	std::cout << "Unknown exception occured" << std::endl;
865	throw;
866	}
867	return 1;
868	}
869
870
871	// Local Variables:
872	// tab-width: 3
873	// c-basic-offset: 3
874	// c-file-offsets:((innamespace . 0)(inline-open . 0))
875	// indent-tabs-mode: nil
876	// End:
877
878	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3

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