1 | ///////////////////////////////////////////////////////////////////////// |
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2 | // File: top.cpp |
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3 | // Author: Alain Greiner |
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4 | // Copyright: UPMC/LIP6 |
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5 | // Date : may 2013 |
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6 | // This program is released under the GNU public license |
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7 | ///////////////////////////////////////////////////////////////////////// |
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8 | // This file define a generic TSAR architecture. |
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9 | // The physical address space is 40 bits. |
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10 | // |
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11 | // The number of clusters cannot be larger than 256. |
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12 | // The number of processors per cluster cannot be larger than 8. |
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13 | // |
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14 | // - It uses four dspin_local_crossbar per cluster as local interconnect |
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15 | // - It uses two virtual_dspin routers per cluster as global interconnect |
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16 | // - It uses the vci_cc_vcache_wrapper |
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17 | // - It uses the vci_mem_cache |
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18 | // - It contains one vci_xicu per cluster. |
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19 | // - It contains one vci_multi_dma per cluster. |
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20 | // - It contains one vci_simple_ram per cluster to model the L3 cache. |
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21 | // |
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22 | // The communication between the MemCache and the Xram is 64 bits. |
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23 | // |
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24 | // All clusters are identical, but the cluster 0 (called io_cluster), |
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25 | // contains 6 extra components: |
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26 | // - the boot rom (BROM) |
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27 | // - the disk controller (BDEV) |
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28 | // - the multi-channel network controller (MNIC) |
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29 | // - the multi-channel chained buffer dma controller (CDMA) |
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30 | // - the multi-channel tty controller (MTTY) |
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31 | // - the frame buffer controller (FBUF) |
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32 | // |
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33 | // It is build with one single component implementing a cluster, |
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34 | // defined in files tsar_xbar_cluster.* (with * = cpp, h, sd) |
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35 | // |
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36 | // The IRQs are connected to XICUs as follow: |
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37 | // - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters. |
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38 | // - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters. |
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39 | // - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster. |
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40 | // - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. |
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41 | // |
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42 | // Some hardware parameters are used when compiling the OS, and are used |
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43 | // by this top.cpp file. They must be defined in the hard_config.h file : |
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44 | // - CLUSTER_X : number of clusters in a row (power of 2) |
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45 | // - CLUSTER_Y : number of clusters in a column (power of 2) |
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46 | // - CLUSTER_SIZE : size of the segment allocated to a cluster |
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47 | // - NB_PROCS_MAX : number of processors per cluster (power of 2) |
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48 | // - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) |
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49 | // - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16) |
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50 | // - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9) |
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51 | // |
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52 | // Some other hardware parameters are not used when compiling the OS, |
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53 | // and can be directly defined in this top.cpp file: |
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54 | // - XRAM_LATENCY : external ram latency |
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55 | // - MEMC_WAYS : L2 cache number of ways |
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56 | // - MEMC_SETS : L2 cache number of sets |
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57 | // - L1_IWAYS |
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58 | // - L1_ISETS |
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59 | // - L1_DWAYS |
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60 | // - L1_DSETS |
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61 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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62 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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63 | // - BDEV_SECTOR_SIZE : block size for block drvice |
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64 | // - BDEV_IMAGE_NAME : file pathname for block device |
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65 | // - NIC_RX_NAME : file pathname for NIC received packets |
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66 | // - NIC_TX_NAME : file pathname for NIC transmited packets |
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67 | // - NIC_TIMEOUT : max number of cycles before closing a container |
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68 | ///////////////////////////////////////////////////////////////////////// |
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69 | // General policy for 40 bits physical address decoding: |
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70 | // All physical segments base addresses are multiple of 1 Mbytes |
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71 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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72 | // The (x_width + y_width) MSB bits (left aligned) define |
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73 | // the cluster index, and the LADR bits define the local index: |
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74 | // | X_ID | Y_ID |---| LADR | OFFSET | |
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75 | // |x_width|y_width|---| 8 | 24 | |
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76 | ///////////////////////////////////////////////////////////////////////// |
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77 | // General policy for 14 bits SRCID decoding: |
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78 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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79 | // | X_ID | Y_ID |---| L_ID | |
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80 | // |x_width|y_width|---| 6 | |
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81 | ///////////////////////////////////////////////////////////////////////// |
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82 | |
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83 | #include <systemc> |
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84 | #include <sys/time.h> |
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85 | #include <iostream> |
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86 | #include <sstream> |
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87 | #include <cstdlib> |
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88 | #include <cstdarg> |
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89 | #include <stdint.h> |
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90 | |
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91 | #include "gdbserver.h" |
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92 | #include "mapping_table.h" |
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93 | #include "alloc_elems.h" |
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94 | #include "tsar_xbar_cluster.h" |
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95 | |
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96 | #define USE_ALMOS 1 |
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97 | //#define USE_GIET |
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98 | |
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99 | #ifdef USE_ALMOS |
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100 | #ifdef USE_GIET |
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101 | #error "Can't use Two different OS" |
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102 | #endif |
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103 | #endif |
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104 | |
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105 | #ifndef USE_ALMOS |
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106 | #ifndef USE_GIET |
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107 | #error "You need to specify one OS" |
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108 | #endif |
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109 | #endif |
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110 | |
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111 | #ifdef USE_ALMOS |
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112 | #define PREFIX_OS "almos/" |
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113 | #include "almos/hard_config.h" |
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114 | #endif |
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115 | #ifdef USE_GIET |
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116 | #define PREFIX_OS "giet_vm/" |
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117 | #endif |
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118 | |
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119 | /////////////////////////////////////////////////// |
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120 | // Parallelisation |
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121 | /////////////////////////////////////////////////// |
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122 | |
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123 | |
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124 | #if USE_OPENMP |
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125 | #include <omp.h> |
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126 | #endif |
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127 | |
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128 | // cluster index (computed from x,y coordinates) |
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129 | #ifdef USE_ALMOS |
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130 | #define cluster(x,y) (y + x * Y_SIZE) |
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131 | #else |
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132 | #define cluster(x,y) (y + (x << Y_WIDTH)) |
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133 | #endif |
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134 | |
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135 | |
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136 | #define min(x, y) (x < y ? x : y) |
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137 | |
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138 | /////////////////////////////////////////////////////////// |
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139 | // DSPIN parameters |
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140 | /////////////////////////////////////////////////////////// |
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141 | |
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142 | #define dspin_cmd_width 39 |
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143 | #define dspin_rsp_width 32 |
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144 | |
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145 | /////////////////////////////////////////////////////////// |
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146 | // VCI parameters |
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147 | /////////////////////////////////////////////////////////// |
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148 | |
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149 | #define vci_cell_width_int 4 |
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150 | #define vci_cell_width_ext 8 |
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151 | |
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152 | #ifdef USE_ALMOS |
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153 | #define vci_address_width 32 |
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154 | #endif |
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155 | #ifdef USE_GIET |
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156 | #define vci_address_width 40 |
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157 | #endif |
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158 | #define vci_plen_width 8 |
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159 | #define vci_rerror_width 1 |
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160 | #define vci_clen_width 1 |
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161 | #define vci_rflag_width 1 |
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162 | #define vci_srcid_width 14 |
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163 | #define vci_pktid_width 4 |
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164 | #define vci_trdid_width 4 |
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165 | #define vci_wrplen_width 1 |
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166 | |
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167 | //////////////////////////////////////////////////////////// |
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168 | // Secondary Hardware Parameters |
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169 | //////////////////////i///////////////////////////////////// |
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170 | |
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171 | |
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172 | #define XRAM_LATENCY 0 |
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173 | |
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174 | #define MEMC_WAYS 16 |
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175 | #define MEMC_SETS 256 |
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176 | |
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177 | #define L1_IWAYS 4 |
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178 | #define L1_ISETS 64 |
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179 | |
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180 | #define L1_DWAYS 4 |
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181 | #define L1_DSETS 64 |
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182 | |
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183 | #ifdef USE_ALMOS |
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184 | #define FBUF_X_SIZE 1024 |
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185 | #define FBUF_Y_SIZE 1024 |
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186 | #endif |
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187 | #ifdef USE_GIET |
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188 | #define FBUF_X_SIZE 128 |
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189 | #define FBUF_Y_SIZE 128 |
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190 | #endif |
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191 | |
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192 | #ifdef USE_GIET |
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193 | #define BDEV_SECTOR_SIZE 512 |
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194 | #define BDEV_IMAGE_NAME PREFIX_OS"display/images.raw" |
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195 | #endif |
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196 | #ifdef USE_ALMOS |
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197 | #define BDEV_SECTOR_SIZE 4096 |
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198 | #define BDEV_IMAGE_NAME PREFIX_OS"hdd-img.bin" |
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199 | #endif |
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200 | |
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201 | #define NIC_RX_NAME PREFIX_OS"nic/rx_packets.txt" |
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202 | #define NIC_TX_NAME PREFIX_OS"nic/tx_packets.txt" |
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203 | #define NIC_TIMEOUT 10000 |
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204 | |
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205 | #define NORTH 0 |
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206 | #define SOUTH 1 |
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207 | #define EAST 2 |
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208 | #define WEST 3 |
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209 | |
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210 | //////////////////////////////////////////////////////////// |
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211 | // Software to be loaded in ROM & RAM |
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212 | //////////////////////i///////////////////////////////////// |
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213 | |
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214 | #ifdef USE_ALMOS |
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215 | #define soft_name PREFIX_OS"bootloader-tsar-mipsel.bin",\ |
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216 | PREFIX_OS"kernel-soclib.bin@0xbfc10000:D",\ |
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217 | PREFIX_OS"arch-info.bib@0xBFC08000:D" |
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218 | #endif |
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219 | #ifdef USE_GIET |
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220 | #define soft_pathname PREFIX_OS"soft.elf" |
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221 | #endif |
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222 | |
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223 | //////////////////////////////////////////////////////////// |
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224 | // DEBUG Parameters default values |
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225 | //////////////////////i///////////////////////////////////// |
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226 | |
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227 | #define MAX_FROZEN_CYCLES 100000000 |
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228 | |
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229 | |
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230 | //////////////////////////////////////////////////////////////////// |
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231 | // TGTID definition in direct space |
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232 | // For all components: global TGTID = global SRCID = cluster_index |
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233 | //////////////////////////////////////////////////////////////////// |
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234 | |
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235 | #define MEMC_TGTID 0 |
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236 | #define XICU_TGTID 1 |
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237 | #define MDMA_TGTID 2 |
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238 | #define MTTY_TGTID 3 |
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239 | #define BDEV_TGTID 4 |
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240 | #define MNIC_TGTID 5 |
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241 | #define BROM_TGTID 6 |
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242 | #define CDMA_TGTID 7 |
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243 | #define SIMH_TGTID 8 |
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244 | #define FBUF_TGTID 9 |
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245 | |
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246 | |
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247 | ///////////////////////////////////////////////////////// |
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248 | // Physical segments definition |
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249 | ///////////////////////////////////////////////////////// |
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250 | // There is 3 segments replicated in all clusters |
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251 | // and 5 specific segments in the "IO" cluster |
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252 | // (containing address 0xBF000000) |
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253 | ///////////////////////////////////////////////////////// |
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254 | |
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255 | #ifdef USE_GIET |
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256 | // specific segments in "IO" cluster : absolute physical address |
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257 | #define BROM_BASE 0x00BFC00000 |
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258 | #define BROM_SIZE 0x0000100000 // 1 Mbytes |
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259 | |
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260 | #define FBUF_BASE 0x00B2000000 |
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261 | #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) |
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262 | |
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263 | #define BDEV_BASE 0x00B3000000 |
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264 | #define BDEV_SIZE 0x0000001000 // 4 Kbytes |
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265 | |
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266 | #define MTTY_BASE 0x00B4000000 |
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267 | #define MTTY_SIZE 0x0000001000 // 4 Kbytes |
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268 | |
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269 | #define MNIC_BASE 0x00B5000000 |
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270 | #define MNIC_SIZE 0x0000080000 // 512 Kbytes (for 8 channels) |
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271 | |
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272 | #define CDMA_BASE 0x00B6000000 |
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273 | #define CDMA_SIZE 0x0000004000 * NB_CMA_CHANNELS |
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274 | |
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275 | // replicated segments : address is incremented by a cluster offset |
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276 | // offset = cluster(x,y) << (address_width-x_width-y_width); |
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277 | |
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278 | #define MEMC_BASE 0x0000000000 |
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279 | #define MEMC_SIZE 0x0010000000 // 256 Mbytes per cluster |
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280 | |
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281 | #define XICU_BASE 0x00B0000000 |
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282 | #define XICU_SIZE 0x0000001000 // 4 Kbytes |
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283 | |
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284 | #define MDMA_BASE 0x00B1000000 |
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285 | #define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel |
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286 | |
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287 | #define SIMH_BASE 0x00B7000000 |
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288 | #define SIMH_SIZE 0x0000001000 |
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289 | #endif |
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290 | |
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291 | #ifdef USE_ALMOS |
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292 | // 2^19 is the offset for the local id (8 bits for global ID : |
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293 | // 1 bit for Memcache or Peripheral, 4 for local peripheral id) |
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294 | // (Almos supports 32 bits physical addresses) |
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295 | |
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296 | #define CLUSTER_INC (0x80000000ULL / (X_SIZE * Y_SIZE) * 2) |
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297 | |
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298 | #define CLUSTER_IO_INC (cluster_io_id * CLUSTER_INC) |
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299 | #define MEMC_MAX_SIZE (0x40000000 / (X_SIZE * Y_SIZE)) // 0x40000000 : valeur totale souhaitée (ici : 1Go) |
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300 | |
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301 | #define BROM_BASE 0x00BFC00000 |
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302 | #define BROM_SIZE 0x0000100000 // 1 Mbytes |
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303 | |
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304 | #define MEMC_BASE 0x0000000000 |
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305 | #define MEMC_SIZE min(0x04000000, MEMC_MAX_SIZE) |
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306 | |
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307 | #define XICU_BASE (CLUSTER_INC >> 1) + (XICU_TGTID << 19) |
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308 | #define XICU_SIZE 0x0000001000 // 4 Kbytes |
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309 | |
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310 | #define MDMA_BASE (CLUSTER_INC >> 1) + (MDMA_TGTID << 19) |
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311 | #define MDMA_SIZE (0x0000001000 * NB_DMA_CHANNELS) // 4 Kbytes per channel |
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312 | |
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313 | #define BDEV_BASE (CLUSTER_INC >> 1) + (BDEV_TGTID << 19) + (CLUSTER_IO_INC) |
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314 | #define BDEV_SIZE 0x0000001000 // 4 Kbytes |
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315 | |
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316 | #define MTTY_BASE (CLUSTER_INC >> 1) + (MTTY_TGTID << 19) + (CLUSTER_IO_INC) |
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317 | #define MTTY_SIZE 0x0000001000 // 4 Kbytes |
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318 | |
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319 | #define FBUF_BASE (CLUSTER_INC >> 1) + (FBUF_TGTID << 19) + (CLUSTER_IO_INC) |
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320 | #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) // Should be 0x80000 |
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321 | |
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322 | #define MNIC_BASE (CLUSTER_INC >> 1) + (MNIC_TGTID << 19) + (CLUSTER_IO_INC) |
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323 | #define MNIC_SIZE 0x0000080000 |
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324 | |
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325 | #define CDMA_BASE (CLUSTER_INC >> 1) + (CDMA_TGTID << 19) + (CLUSTER_IO_INC) |
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326 | #define CDMA_SIZE (0x0000004000 * NB_CMA_CHANNELS) |
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327 | |
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328 | #define SIMH_BASE (CLUSTER_INC >> 1) + (SIMH_TGTID << 19) + (CLUSTER_IO_INC) |
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329 | #define SIMH_SIZE 0x0000001000 |
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330 | #endif |
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331 | |
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332 | bool stop_called = false; |
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333 | |
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334 | ///////////////////////////////// |
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335 | int _main(int argc, char *argv[]) |
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336 | { |
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337 | using namespace sc_core; |
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338 | using namespace soclib::caba; |
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339 | using namespace soclib::common; |
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340 | |
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341 | #ifdef USE_GIET |
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342 | char soft_name[256] = soft_pathname; // pathname to binary code |
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343 | #endif |
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344 | const int64_t max_cycles = 5000000; // Maximum number of cycles simulated in one sc_start call |
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345 | int64_t ncycles = 0x7FFFFFFFFFFFFFFF; // simulated cycles |
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346 | char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image |
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347 | char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file |
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348 | char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file |
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349 | ssize_t threads_nr = 1; // simulator's threads number |
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350 | bool debug_ok = false; // trace activated |
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351 | size_t debug_period = 1; // trace period |
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352 | size_t debug_memc_id = 0; // index of memc to be traced |
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353 | size_t debug_proc_id = 0; // index of proc to be traced |
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354 | int64_t debug_from = 0; // trace start cycle |
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355 | int64_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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356 | size_t cluster_io_id; // index of cluster containing IOs |
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357 | int64_t reset_counters = -1; |
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358 | int64_t dump_counters = -1; |
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359 | bool do_reset_counters = false; |
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360 | bool do_dump_counters = false; |
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361 | struct timeval t1, t2; |
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362 | uint64_t ms1, ms2; |
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363 | |
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364 | ////////////// command line arguments ////////////////////// |
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365 | if (argc > 1) |
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366 | { |
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367 | for (int n = 1; n < argc; n = n + 2) |
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368 | { |
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369 | if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc)) |
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370 | { |
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371 | ncycles = (int64_t) strtol(argv[n + 1], NULL, 0); |
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372 | } |
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373 | else if ((strcmp(argv[n], "-SOFT") == 0) && (n + 1 < argc)) |
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374 | { |
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375 | #ifdef USE_ALMOS |
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376 | assert( 0 && "Can't define almos soft name" ); |
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377 | #endif |
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378 | #ifdef USE_GIET |
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379 | strcpy(soft_name, argv[n + 1]); |
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380 | #endif |
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381 | } |
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382 | else if ((strcmp(argv[n],"-DISK") == 0) && (n + 1 < argc)) |
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383 | { |
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384 | strcpy(disk_name, argv[n + 1]); |
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385 | } |
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386 | else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc)) |
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387 | { |
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388 | debug_ok = true; |
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389 | debug_from = (int64_t) strtol(argv[n + 1], NULL, 0); |
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390 | } |
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391 | else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc)) |
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392 | { |
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393 | debug_memc_id = (size_t) strtol(argv[n + 1], NULL, 0); |
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394 | #ifdef USE_ALMOS |
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395 | assert((debug_memc_id < (X_SIZE * Y_SIZE)) && |
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396 | "debug_memc_id larger than X_SIZE * Y_SIZE" ); |
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397 | #else |
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398 | size_t x = debug_memc_id >> Y_WIDTH; |
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399 | size_t y = debug_memc_id & ((1<<Y_WIDTH)-1); |
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400 | |
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401 | assert( (x <= X_SIZE) and (y <= Y_SIZE) && |
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402 | "MEMCID parameter refers a not valid memory cache"); |
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403 | #endif |
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404 | } |
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405 | else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc)) |
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406 | { |
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407 | debug_proc_id = (size_t) strtol(argv[n + 1], NULL, 0); |
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408 | #ifdef USE_ALMOS |
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409 | assert((debug_proc_id < (X_SIZE * Y_SIZE * NB_PROCS_MAX)) && |
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410 | "debug_proc_id larger than X_SIZE * Y_SIZE * NB_PROCS"); |
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411 | #else |
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412 | size_t cluster_xy = debug_proc_id / NB_PROCS_MAX ; |
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413 | size_t x = cluster_xy >> Y_WIDTH; |
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414 | size_t y = cluster_xy & ((1<<Y_WIDTH)-1); |
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415 | |
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416 | assert( (x <= X_SIZE) and (y <= Y_SIZE) && |
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417 | "PROCID parameter refers a not valid processor"); |
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418 | #endif |
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419 | } |
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420 | else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc)) |
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421 | { |
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422 | threads_nr = (ssize_t) strtol(argv[n + 1], NULL, 0); |
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423 | threads_nr = (threads_nr < 1) ? 1 : threads_nr; |
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424 | } |
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425 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc)) |
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426 | { |
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427 | frozen_cycles = (int64_t) strtol(argv[n + 1], NULL, 0); |
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428 | } |
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429 | else if ((strcmp(argv[n], "-PERIOD") == 0) && (n + 1 < argc)) |
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430 | { |
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431 | debug_period = (size_t) strtol(argv[n + 1], NULL, 0); |
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432 | } |
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433 | else if ((strcmp(argv[n], "--reset-counters") == 0) && (n + 1 < argc)) |
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434 | { |
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435 | reset_counters = (int64_t) strtol(argv[n + 1], NULL, 0); |
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436 | do_reset_counters = true; |
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437 | } |
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438 | else if ((strcmp(argv[n], "--dump-counters") == 0) && (n + 1 < argc)) |
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439 | { |
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440 | dump_counters = (int64_t) strtol(argv[n + 1], NULL, 0); |
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441 | do_dump_counters = true; |
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442 | } |
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443 | else |
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444 | { |
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445 | std::cout << " Arguments are (key,value) couples." << std::endl; |
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446 | std::cout << " The order is not important." << std::endl; |
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447 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
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448 | std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; |
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449 | std::cout << " -DISK pathname_for_disk_image" << std::endl; |
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450 | std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; |
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451 | std::cout << " -DEBUG debug_start_cycle" << std::endl; |
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452 | std::cout << " -THREADS simulator's threads number" << std::endl; |
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453 | std::cout << " -FROZEN max_number_of_lines" << std::endl; |
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454 | std::cout << " -PERIOD number_of_cycles between trace" << std::endl; |
---|
455 | std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; |
---|
456 | std::cout << " -PROCID index_proc_to_be_traced" << std::endl; |
---|
457 | exit(0); |
---|
458 | } |
---|
459 | } |
---|
460 | } |
---|
461 | |
---|
462 | // checking hardware parameters |
---|
463 | assert( ( (X_SIZE == 1) or (X_SIZE == 2) or (X_SIZE == 4) or |
---|
464 | (X_SIZE == 8) or (X_SIZE == 16) ) and |
---|
465 | "The X_SIZE parameter must be 1, 2, 4, 8 or 16" ); |
---|
466 | |
---|
467 | assert( ( (Y_SIZE == 1) or (Y_SIZE == 2) or (Y_SIZE == 4) or |
---|
468 | (Y_SIZE == 8) or (Y_SIZE == 16) ) and |
---|
469 | "The Y_SIZE parameter must be 1, 2, 4, 8 or 16" ); |
---|
470 | |
---|
471 | assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or |
---|
472 | (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and |
---|
473 | "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" ); |
---|
474 | |
---|
475 | assert( (NB_DMA_CHANNELS < 9) and |
---|
476 | "The NB_DMA_CHANNELS parameter must be smaller than 9" ); |
---|
477 | |
---|
478 | assert( (NB_TTY_CHANNELS < 15) and |
---|
479 | "The NB_TTY_CHANNELS parameter must be smaller than 15" ); |
---|
480 | |
---|
481 | assert( (NB_NIC_CHANNELS < 9) and |
---|
482 | "The NB_NIC_CHANNELS parameter must be smaller than 9" ); |
---|
483 | |
---|
484 | #ifdef USE_GIET |
---|
485 | assert( (vci_address_width == 40) and |
---|
486 | "VCI address width with the GIET must be 40 bits" ); |
---|
487 | #endif |
---|
488 | |
---|
489 | #ifdef USE_ALMOS |
---|
490 | assert( (vci_address_width == 32) and |
---|
491 | "VCI address width with ALMOS must be 32 bits" ); |
---|
492 | #endif |
---|
493 | |
---|
494 | |
---|
495 | std::cout << std::endl; |
---|
496 | std::cout << " - X_SIZE = " << X_SIZE << std::endl; |
---|
497 | std::cout << " - Y_SIZE = " << Y_SIZE << std::endl; |
---|
498 | std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; |
---|
499 | std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl; |
---|
500 | std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl; |
---|
501 | std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl; |
---|
502 | std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; |
---|
503 | std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; |
---|
504 | std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; |
---|
505 | std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; |
---|
506 | |
---|
507 | std::cout << std::endl; |
---|
508 | // Internal and External VCI parameters definition |
---|
509 | typedef soclib::caba::VciParams<vci_cell_width_int, |
---|
510 | vci_plen_width, |
---|
511 | vci_address_width, |
---|
512 | vci_rerror_width, |
---|
513 | vci_clen_width, |
---|
514 | vci_rflag_width, |
---|
515 | vci_srcid_width, |
---|
516 | vci_pktid_width, |
---|
517 | vci_trdid_width, |
---|
518 | vci_wrplen_width> vci_param_int; |
---|
519 | |
---|
520 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
---|
521 | vci_plen_width, |
---|
522 | vci_address_width, |
---|
523 | vci_rerror_width, |
---|
524 | vci_clen_width, |
---|
525 | vci_rflag_width, |
---|
526 | vci_srcid_width, |
---|
527 | vci_pktid_width, |
---|
528 | vci_trdid_width, |
---|
529 | vci_wrplen_width> vci_param_ext; |
---|
530 | |
---|
531 | #if USE_OPENMP |
---|
532 | omp_set_dynamic(false); |
---|
533 | omp_set_num_threads(threads_nr); |
---|
534 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
---|
535 | #endif |
---|
536 | |
---|
537 | // Define parameters depending on mesh size |
---|
538 | size_t x_width; |
---|
539 | size_t y_width; |
---|
540 | |
---|
541 | #ifdef USE_ALMOS |
---|
542 | if (X_SIZE == 1) x_width = 0; |
---|
543 | else if (X_SIZE == 2) x_width = 1; |
---|
544 | else if (X_SIZE <= 4) x_width = 2; |
---|
545 | else if (X_SIZE <= 8) x_width = 3; |
---|
546 | else x_width = 4; |
---|
547 | |
---|
548 | if (Y_SIZE == 1) y_width = 0; |
---|
549 | else if (Y_SIZE == 2) y_width = 1; |
---|
550 | else if (Y_SIZE <= 4) y_width = 2; |
---|
551 | else if (Y_SIZE <= 8) y_width = 3; |
---|
552 | else y_width = 4; |
---|
553 | |
---|
554 | #else |
---|
555 | size_t x_width = X_WIDTH; |
---|
556 | size_t y_width = Y_WIDTH; |
---|
557 | |
---|
558 | assert( (X_WIDTH <= 4) and (Y_WIDTH <= 4) and |
---|
559 | "Up to 256 clusters"); |
---|
560 | |
---|
561 | assert( (X_SIZE <= (1 << X_WIDTH)) and (Y_SIZE <= (1 << Y_WIDTH)) and |
---|
562 | "The X_WIDTH and Y_WIDTH parameter are insufficient"); |
---|
563 | |
---|
564 | #endif |
---|
565 | |
---|
566 | // index of cluster containing IOs |
---|
567 | cluster_io_id = 0x00bfc00000ULL >> (vci_address_width - x_width - y_width); |
---|
568 | |
---|
569 | |
---|
570 | ///////////////////// |
---|
571 | // Mapping Tables |
---|
572 | ///////////////////// |
---|
573 | |
---|
574 | // internal network |
---|
575 | MappingTable maptabd(vci_address_width, |
---|
576 | IntTab(x_width + y_width, 16 - x_width - y_width), |
---|
577 | IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), |
---|
578 | 0x00FF800000); |
---|
579 | |
---|
580 | for (size_t x = 0; x < X_SIZE; x++) |
---|
581 | { |
---|
582 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
583 | { |
---|
584 | sc_uint<vci_address_width> offset; |
---|
585 | offset = (sc_uint<vci_address_width>)cluster(x,y) |
---|
586 | << (vci_address_width-x_width-y_width); |
---|
587 | |
---|
588 | std::ostringstream si; |
---|
589 | si << "seg_xicu_" << x << "_" << y; |
---|
590 | maptabd.add(Segment(si.str(), XICU_BASE + offset, XICU_SIZE, |
---|
591 | IntTab(cluster(x,y),XICU_TGTID), false)); |
---|
592 | |
---|
593 | std::ostringstream sd; |
---|
594 | sd << "seg_mdma_" << x << "_" << y; |
---|
595 | maptabd.add(Segment(sd.str(), MDMA_BASE + offset, MDMA_SIZE, |
---|
596 | IntTab(cluster(x,y),MDMA_TGTID), false)); |
---|
597 | |
---|
598 | std::ostringstream sh; |
---|
599 | sh << "seg_memc_" << x << "_" << y; |
---|
600 | maptabd.add(Segment(sh.str(), MEMC_BASE + offset, MEMC_SIZE, |
---|
601 | IntTab(cluster(x,y),MEMC_TGTID), true)); |
---|
602 | |
---|
603 | if ( cluster(x,y) == cluster_io_id ) |
---|
604 | { |
---|
605 | maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE, |
---|
606 | IntTab(cluster(x,y),MTTY_TGTID), false)); |
---|
607 | maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE, |
---|
608 | IntTab(cluster(x,y),FBUF_TGTID), false)); |
---|
609 | maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE, |
---|
610 | IntTab(cluster(x,y),BDEV_TGTID), false)); |
---|
611 | maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE, |
---|
612 | IntTab(cluster(x,y),BROM_TGTID), true)); |
---|
613 | maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE, |
---|
614 | IntTab(cluster(x,y),MNIC_TGTID), false)); |
---|
615 | maptabd.add(Segment("seg_cdma", CDMA_BASE, CDMA_SIZE, |
---|
616 | IntTab(cluster(x,y),CDMA_TGTID), false)); |
---|
617 | maptabd.add(Segment("seg_simh", SIMH_BASE, SIMH_SIZE, |
---|
618 | IntTab(cluster(x,y),SIMH_TGTID), false)); |
---|
619 | } |
---|
620 | } |
---|
621 | } |
---|
622 | std::cout << maptabd << std::endl; |
---|
623 | |
---|
624 | // external network |
---|
625 | MappingTable maptabx(vci_address_width, |
---|
626 | IntTab(x_width+y_width), |
---|
627 | IntTab(x_width+y_width), |
---|
628 | 0xFFFF000000ULL); |
---|
629 | |
---|
630 | for (size_t x = 0; x < X_SIZE; x++) |
---|
631 | { |
---|
632 | for (size_t y = 0; y < Y_SIZE ; y++) |
---|
633 | { |
---|
634 | |
---|
635 | sc_uint<vci_address_width> offset; |
---|
636 | offset = (sc_uint<vci_address_width>)cluster(x,y) |
---|
637 | << (vci_address_width-x_width-y_width); |
---|
638 | |
---|
639 | std::ostringstream sh; |
---|
640 | sh << "x_seg_memc_" << x << "_" << y; |
---|
641 | |
---|
642 | maptabx.add(Segment(sh.str(), MEMC_BASE + offset, |
---|
643 | MEMC_SIZE, IntTab(cluster(x,y)), false)); |
---|
644 | } |
---|
645 | } |
---|
646 | std::cout << maptabx << std::endl; |
---|
647 | |
---|
648 | //////////////////// |
---|
649 | // Signals |
---|
650 | /////////////////// |
---|
651 | |
---|
652 | sc_clock signal_clk("clk"); |
---|
653 | sc_signal<bool> signal_resetn("resetn"); |
---|
654 | |
---|
655 | // Horizontal inter-clusters DSPIN signals |
---|
656 | DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_inc = |
---|
657 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE, 3); |
---|
658 | DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_dec = |
---|
659 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE, 3); |
---|
660 | DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_inc = |
---|
661 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE, 2); |
---|
662 | DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_dec = |
---|
663 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE, 2); |
---|
664 | |
---|
665 | // Vertical inter-clusters DSPIN signals |
---|
666 | DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_inc = |
---|
667 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-1, 3); |
---|
668 | DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_dec = |
---|
669 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-1, 3); |
---|
670 | DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_inc = |
---|
671 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-1, 2); |
---|
672 | DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_dec = |
---|
673 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-1, 2); |
---|
674 | |
---|
675 | // Mesh boundaries DSPIN signals |
---|
676 | DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_in = |
---|
677 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in" , X_SIZE, Y_SIZE, 4, 3); |
---|
678 | DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_out = |
---|
679 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", X_SIZE, Y_SIZE, 4, 3); |
---|
680 | DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_in = |
---|
681 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in" , X_SIZE, Y_SIZE, 4, 2); |
---|
682 | DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_out = |
---|
683 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", X_SIZE, Y_SIZE, 4, 2); |
---|
684 | |
---|
685 | //////////////////////////// |
---|
686 | // Loader |
---|
687 | //////////////////////////// |
---|
688 | |
---|
689 | soclib::common::Loader loader(soft_name); |
---|
690 | |
---|
691 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
692 | proc_iss::set_loader(loader); |
---|
693 | |
---|
694 | //////////////////////////// |
---|
695 | // Clusters construction |
---|
696 | //////////////////////////// |
---|
697 | |
---|
698 | TsarXbarCluster<dspin_cmd_width, |
---|
699 | dspin_rsp_width, |
---|
700 | vci_param_int, |
---|
701 | vci_param_ext>* clusters[X_SIZE][Y_SIZE]; |
---|
702 | |
---|
703 | #if USE_OPENMP |
---|
704 | #pragma omp parallel |
---|
705 | { |
---|
706 | #pragma omp for |
---|
707 | #endif |
---|
708 | for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) |
---|
709 | { |
---|
710 | size_t x = i / Y_SIZE; |
---|
711 | size_t y = i % Y_SIZE; |
---|
712 | |
---|
713 | #if USE_OPENMP |
---|
714 | #pragma omp critical |
---|
715 | { |
---|
716 | #endif |
---|
717 | std::cout << std::endl; |
---|
718 | std::cout << "Cluster_" << x << "_" << y << std::endl; |
---|
719 | std::cout << std::endl; |
---|
720 | |
---|
721 | std::ostringstream sc; |
---|
722 | sc << "cluster_" << x << "_" << y; |
---|
723 | clusters[x][y] = new TsarXbarCluster<dspin_cmd_width, |
---|
724 | dspin_rsp_width, |
---|
725 | vci_param_int, |
---|
726 | vci_param_ext> |
---|
727 | ( |
---|
728 | sc.str().c_str(), |
---|
729 | NB_PROCS_MAX, |
---|
730 | NB_TTY_CHANNELS, |
---|
731 | NB_DMA_CHANNELS, |
---|
732 | x, |
---|
733 | y, |
---|
734 | cluster(x,y), |
---|
735 | maptabd, |
---|
736 | maptabx, |
---|
737 | x_width, |
---|
738 | y_width, |
---|
739 | vci_srcid_width - x_width - y_width, // l_id width, |
---|
740 | MEMC_TGTID, |
---|
741 | XICU_TGTID, |
---|
742 | MDMA_TGTID, |
---|
743 | FBUF_TGTID, |
---|
744 | MTTY_TGTID, |
---|
745 | BROM_TGTID, |
---|
746 | MNIC_TGTID, |
---|
747 | CDMA_TGTID, |
---|
748 | BDEV_TGTID, |
---|
749 | SIMH_TGTID, |
---|
750 | MEMC_WAYS, |
---|
751 | MEMC_SETS, |
---|
752 | L1_IWAYS, |
---|
753 | L1_ISETS, |
---|
754 | L1_DWAYS, |
---|
755 | L1_DSETS, |
---|
756 | IRQ_PER_PROCESSOR, |
---|
757 | XRAM_LATENCY, |
---|
758 | (cluster(x,y) == cluster_io_id), |
---|
759 | FBUF_X_SIZE, |
---|
760 | FBUF_Y_SIZE, |
---|
761 | disk_name, |
---|
762 | BDEV_SECTOR_SIZE, |
---|
763 | NB_NIC_CHANNELS, |
---|
764 | nic_rx_name, |
---|
765 | nic_tx_name, |
---|
766 | NIC_TIMEOUT, |
---|
767 | NB_CMA_CHANNELS, |
---|
768 | loader, |
---|
769 | frozen_cycles, |
---|
770 | debug_from, |
---|
771 | debug_ok and (cluster(x,y) == debug_memc_id), |
---|
772 | debug_ok and (cluster(x,y) == debug_proc_id) |
---|
773 | ); |
---|
774 | |
---|
775 | #if USE_OPENMP |
---|
776 | } // end critical |
---|
777 | #endif |
---|
778 | } // end for |
---|
779 | #if USE_OPENMP |
---|
780 | } |
---|
781 | #endif |
---|
782 | |
---|
783 | /////////////////////////////////////////////////////////////// |
---|
784 | // Net-list |
---|
785 | /////////////////////////////////////////////////////////////// |
---|
786 | |
---|
787 | // Clock & RESET |
---|
788 | for (size_t x = 0; x < (X_SIZE); x++){ |
---|
789 | for (size_t y = 0; y < Y_SIZE; y++){ |
---|
790 | clusters[x][y]->p_clk (signal_clk); |
---|
791 | clusters[x][y]->p_resetn (signal_resetn); |
---|
792 | } |
---|
793 | } |
---|
794 | |
---|
795 | // Inter Clusters horizontal connections |
---|
796 | if (X_SIZE > 1){ |
---|
797 | for (size_t x = 0; x < (X_SIZE-1); x++){ |
---|
798 | for (size_t y = 0; y < Y_SIZE; y++){ |
---|
799 | for (size_t k = 0; k < 3; k++){ |
---|
800 | clusters[x][y]->p_cmd_out[EAST][k] (signal_dspin_h_cmd_inc[x][y][k]); |
---|
801 | clusters[x+1][y]->p_cmd_in[WEST][k] (signal_dspin_h_cmd_inc[x][y][k]); |
---|
802 | clusters[x][y]->p_cmd_in[EAST][k] (signal_dspin_h_cmd_dec[x][y][k]); |
---|
803 | clusters[x+1][y]->p_cmd_out[WEST][k] (signal_dspin_h_cmd_dec[x][y][k]); |
---|
804 | } |
---|
805 | |
---|
806 | for (size_t k = 0; k < 2; k++){ |
---|
807 | clusters[x][y]->p_rsp_out[EAST][k] (signal_dspin_h_rsp_inc[x][y][k]); |
---|
808 | clusters[x+1][y]->p_rsp_in[WEST][k] (signal_dspin_h_rsp_inc[x][y][k]); |
---|
809 | clusters[x][y]->p_rsp_in[EAST][k] (signal_dspin_h_rsp_dec[x][y][k]); |
---|
810 | clusters[x+1][y]->p_rsp_out[WEST][k] (signal_dspin_h_rsp_dec[x][y][k]); |
---|
811 | } |
---|
812 | } |
---|
813 | } |
---|
814 | } |
---|
815 | std::cout << std::endl << "Horizontal connections established" << std::endl; |
---|
816 | |
---|
817 | // Inter Clusters vertical connections |
---|
818 | if (Y_SIZE > 1) { |
---|
819 | for (size_t y = 0; y < (Y_SIZE-1); y++){ |
---|
820 | for (size_t x = 0; x < X_SIZE; x++){ |
---|
821 | for (size_t k = 0; k < 3; k++){ |
---|
822 | clusters[x][y]->p_cmd_out[NORTH][k] (signal_dspin_v_cmd_inc[x][y][k]); |
---|
823 | clusters[x][y+1]->p_cmd_in[SOUTH][k] (signal_dspin_v_cmd_inc[x][y][k]); |
---|
824 | clusters[x][y]->p_cmd_in[NORTH][k] (signal_dspin_v_cmd_dec[x][y][k]); |
---|
825 | clusters[x][y+1]->p_cmd_out[SOUTH][k] (signal_dspin_v_cmd_dec[x][y][k]); |
---|
826 | } |
---|
827 | |
---|
828 | for (size_t k = 0; k < 2; k++){ |
---|
829 | clusters[x][y]->p_rsp_out[NORTH][k] (signal_dspin_v_rsp_inc[x][y][k]); |
---|
830 | clusters[x][y+1]->p_rsp_in[SOUTH][k] (signal_dspin_v_rsp_inc[x][y][k]); |
---|
831 | clusters[x][y]->p_rsp_in[NORTH][k] (signal_dspin_v_rsp_dec[x][y][k]); |
---|
832 | clusters[x][y+1]->p_rsp_out[SOUTH][k] (signal_dspin_v_rsp_dec[x][y][k]); |
---|
833 | } |
---|
834 | } |
---|
835 | } |
---|
836 | } |
---|
837 | std::cout << "Vertical connections established" << std::endl; |
---|
838 | |
---|
839 | // East & West boundary cluster connections |
---|
840 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
841 | { |
---|
842 | for (size_t k = 0; k < 3; k++) |
---|
843 | { |
---|
844 | clusters[0][y]->p_cmd_in[WEST][k] (signal_dspin_false_cmd_in [0][y][WEST][k]); |
---|
845 | clusters[0][y]->p_cmd_out[WEST][k] (signal_dspin_false_cmd_out[0][y][WEST][k]); |
---|
846 | clusters[X_SIZE-1][y]->p_cmd_in[EAST][k] (signal_dspin_false_cmd_in [X_SIZE-1][y][EAST][k]); |
---|
847 | clusters[X_SIZE-1][y]->p_cmd_out[EAST][k](signal_dspin_false_cmd_out[X_SIZE-1][y][EAST][k]); |
---|
848 | } |
---|
849 | |
---|
850 | for (size_t k = 0; k < 2; k++) |
---|
851 | { |
---|
852 | clusters[0][y]->p_rsp_in[WEST][k] (signal_dspin_false_rsp_in [0][y][WEST][k]); |
---|
853 | clusters[0][y]->p_rsp_out[WEST][k] (signal_dspin_false_rsp_out[0][y][WEST][k]); |
---|
854 | clusters[X_SIZE-1][y]->p_rsp_in[EAST][k] (signal_dspin_false_rsp_in [X_SIZE-1][y][EAST][k]); |
---|
855 | clusters[X_SIZE-1][y]->p_rsp_out[EAST][k](signal_dspin_false_rsp_out[X_SIZE-1][y][EAST][k]); |
---|
856 | } |
---|
857 | } |
---|
858 | |
---|
859 | // North & South boundary clusters connections |
---|
860 | for (size_t x = 0; x < X_SIZE; x++) |
---|
861 | { |
---|
862 | for (size_t k = 0; k < 3; k++) |
---|
863 | { |
---|
864 | clusters[x][0]->p_cmd_in[SOUTH][k] (signal_dspin_false_cmd_in [x][0][SOUTH][k]); |
---|
865 | clusters[x][0]->p_cmd_out[SOUTH][k] (signal_dspin_false_cmd_out[x][0][SOUTH][k]); |
---|
866 | clusters[x][Y_SIZE-1]->p_cmd_in[NORTH][k] (signal_dspin_false_cmd_in [x][Y_SIZE-1][NORTH][k]); |
---|
867 | clusters[x][Y_SIZE-1]->p_cmd_out[NORTH][k](signal_dspin_false_cmd_out[x][Y_SIZE-1][NORTH][k]); |
---|
868 | } |
---|
869 | |
---|
870 | for (size_t k = 0; k < 2; k++) |
---|
871 | { |
---|
872 | clusters[x][0]->p_rsp_in[SOUTH][k] (signal_dspin_false_rsp_in [x][0][SOUTH][k]); |
---|
873 | clusters[x][0]->p_rsp_out[SOUTH][k] (signal_dspin_false_rsp_out[x][0][SOUTH][k]); |
---|
874 | clusters[x][Y_SIZE-1]->p_rsp_in[NORTH][k] (signal_dspin_false_rsp_in [x][Y_SIZE-1][NORTH][k]); |
---|
875 | clusters[x][Y_SIZE-1]->p_rsp_out[NORTH][k](signal_dspin_false_rsp_out[x][Y_SIZE-1][NORTH][k]); |
---|
876 | } |
---|
877 | } |
---|
878 | std::cout << "North, South, West, East connections established" << std::endl; |
---|
879 | std::cout << std::endl; |
---|
880 | |
---|
881 | |
---|
882 | //#define SC_TRACE |
---|
883 | #ifdef SC_TRACE |
---|
884 | sc_trace_file * tf = sc_create_vcd_trace_file("my_trace_file"); |
---|
885 | |
---|
886 | if (X_SIZE > 1){ |
---|
887 | for (size_t x = 0; x < (X_SIZE-1); x++){ |
---|
888 | for (size_t y = 0; y < Y_SIZE; y++){ |
---|
889 | for (size_t k = 0; k < 3; k++){ |
---|
890 | signal_dspin_h_cmd_inc[x][y][k].trace(tf, "dspin_h_cmd_inc"); |
---|
891 | signal_dspin_h_cmd_dec[x][y][k].trace(tf, "dspin_h_cmd_dec"); |
---|
892 | } |
---|
893 | |
---|
894 | for (size_t k = 0; k < 2; k++){ |
---|
895 | signal_dspin_h_rsp_inc[x][y][k].trace(tf, "dspin_h_rsp_inc"); |
---|
896 | signal_dspin_h_rsp_dec[x][y][k].trace(tf, "dspin_h_rsp_dec"); |
---|
897 | } |
---|
898 | } |
---|
899 | } |
---|
900 | } |
---|
901 | |
---|
902 | if (Y_SIZE > 1) { |
---|
903 | for (size_t y = 0; y < (Y_SIZE-1); y++){ |
---|
904 | for (size_t x = 0; x < X_SIZE; x++){ |
---|
905 | for (size_t k = 0; k < 3; k++){ |
---|
906 | signal_dspin_v_cmd_inc[x][y][k].trace(tf, "dspin_v_cmd_inc"); |
---|
907 | signal_dspin_v_cmd_dec[x][y][k].trace(tf, "dspin_v_cmd_dec"); |
---|
908 | } |
---|
909 | |
---|
910 | for (size_t k = 0; k < 2; k++){ |
---|
911 | signal_dspin_v_rsp_inc[x][y][k].trace(tf, "dspin_v_rsp_inc"); |
---|
912 | signal_dspin_v_rsp_dec[x][y][k].trace(tf, "dspin_v_rsp_dec"); |
---|
913 | } |
---|
914 | } |
---|
915 | } |
---|
916 | } |
---|
917 | |
---|
918 | for (size_t x = 0; x < (X_SIZE); x++){ |
---|
919 | for (size_t y = 0; y < Y_SIZE; y++){ |
---|
920 | std::ostringstream signame; |
---|
921 | signame << "cluster" << x << "_" << y; |
---|
922 | clusters[x][y]->trace(tf, signame.str()); |
---|
923 | } |
---|
924 | } |
---|
925 | #endif |
---|
926 | |
---|
927 | |
---|
928 | //////////////////////////////////////////////////////// |
---|
929 | // Simulation |
---|
930 | /////////////////////////////////////////////////////// |
---|
931 | |
---|
932 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
933 | signal_resetn = false; |
---|
934 | |
---|
935 | // network boundaries signals |
---|
936 | for (size_t x = 0; x < X_SIZE ; x++){ |
---|
937 | for (size_t y = 0; y < Y_SIZE ; y++){ |
---|
938 | for (size_t a = 0; a < 4; a++){ |
---|
939 | for (size_t k = 0; k < 3; k++){ |
---|
940 | signal_dspin_false_cmd_in [x][y][a][k].write = false; |
---|
941 | signal_dspin_false_cmd_in [x][y][a][k].read = true; |
---|
942 | signal_dspin_false_cmd_out[x][y][a][k].write = false; |
---|
943 | signal_dspin_false_cmd_out[x][y][a][k].read = true; |
---|
944 | } |
---|
945 | for (size_t k = 0; k < 2; k++){ |
---|
946 | signal_dspin_false_rsp_in [x][y][a][k].write = false; |
---|
947 | signal_dspin_false_rsp_in [x][y][a][k].read = true; |
---|
948 | signal_dspin_false_rsp_out[x][y][a][k].write = false; |
---|
949 | signal_dspin_false_rsp_out[x][y][a][k].read = true; |
---|
950 | } |
---|
951 | } |
---|
952 | } |
---|
953 | } |
---|
954 | |
---|
955 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
956 | signal_resetn = true; |
---|
957 | |
---|
958 | if (debug_ok) { |
---|
959 | #if USE_OPENMP |
---|
960 | assert(false && "OPEN MP should not be used with debug because of its traces"); |
---|
961 | #endif |
---|
962 | |
---|
963 | if (gettimeofday(&t1, NULL) != 0) { |
---|
964 | perror("gettimeofday"); |
---|
965 | return EXIT_FAILURE; |
---|
966 | } |
---|
967 | |
---|
968 | for (int64_t n = 1; n < ncycles && !stop_called; n++) |
---|
969 | { |
---|
970 | // Monitor a specific address for L1 & L2 caches |
---|
971 | //clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL); |
---|
972 | //clusters[1][0]->memc->copies_monitor(0x800002C000ULL); |
---|
973 | |
---|
974 | if ((n % max_cycles) == 0) |
---|
975 | { |
---|
976 | |
---|
977 | if (gettimeofday(&t2, NULL) != 0) |
---|
978 | { |
---|
979 | perror("gettimeofday"); |
---|
980 | return EXIT_FAILURE; |
---|
981 | } |
---|
982 | |
---|
983 | ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000; |
---|
984 | ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; |
---|
985 | std::cerr << "platform clock frequency " << (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl; |
---|
986 | |
---|
987 | if (gettimeofday(&t1, NULL) != 0) |
---|
988 | { |
---|
989 | perror("gettimeofday"); |
---|
990 | return EXIT_FAILURE; |
---|
991 | } |
---|
992 | } |
---|
993 | |
---|
994 | |
---|
995 | if (n == reset_counters) { |
---|
996 | for (size_t x = 0; x < (X_SIZE); x++) { |
---|
997 | for (size_t y = 0; y < Y_SIZE; y++) { |
---|
998 | clusters[x][y]->memc->reset_counters(); |
---|
999 | } |
---|
1000 | } |
---|
1001 | } |
---|
1002 | |
---|
1003 | if (n == dump_counters) { |
---|
1004 | for (size_t x = 0; x < (X_SIZE); x++) { |
---|
1005 | for (size_t y = 0; y < Y_SIZE; y++) { |
---|
1006 | clusters[x][y]->memc->print_stats(true, false); |
---|
1007 | } |
---|
1008 | } |
---|
1009 | } |
---|
1010 | |
---|
1011 | if ((n > debug_from) and (n % debug_period == 0)) |
---|
1012 | { |
---|
1013 | std::cout << "****************** cycle " << std::dec << n ; |
---|
1014 | std::cout << " ************************************************" << std::endl; |
---|
1015 | |
---|
1016 | // trace proc[debug_proc_id] |
---|
1017 | size_t l = debug_proc_id % NB_PROCS_MAX ; |
---|
1018 | size_t y = (debug_proc_id / NB_PROCS_MAX) % Y_SIZE ; |
---|
1019 | size_t x = debug_proc_id / (Y_SIZE * NB_PROCS_MAX) ; |
---|
1020 | |
---|
1021 | std::ostringstream proc_signame; |
---|
1022 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
---|
1023 | std::ostringstream p2m_signame; |
---|
1024 | p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; |
---|
1025 | std::ostringstream m2p_signame; |
---|
1026 | m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; |
---|
1027 | |
---|
1028 | //clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str()); |
---|
1029 | //clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str()); |
---|
1030 | //clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str()); |
---|
1031 | |
---|
1032 | //clusters[x][y]->signal_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD"); |
---|
1033 | //clusters[x][y]->signal_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD"); |
---|
1034 | //clusters[x][y]->signal_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP"); |
---|
1035 | //clusters[x][y]->signal_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP"); |
---|
1036 | |
---|
1037 | // trace memc[debug_memc_id] |
---|
1038 | x = debug_memc_id / Y_SIZE; |
---|
1039 | y = debug_memc_id % Y_SIZE; |
---|
1040 | |
---|
1041 | std::ostringstream smemc; |
---|
1042 | smemc << "[SIG]MEMC_" << x << "_" << y; |
---|
1043 | std::ostringstream sxram; |
---|
1044 | sxram << "[SIG]XRAM_" << x << "_" << y; |
---|
1045 | std::ostringstream sm2p; |
---|
1046 | sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ; |
---|
1047 | std::ostringstream sp2m; |
---|
1048 | sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ; |
---|
1049 | |
---|
1050 | //clusters[x][y]->memc->print_trace(); |
---|
1051 | //clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); |
---|
1052 | //clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); |
---|
1053 | //clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str()); |
---|
1054 | //clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str()); |
---|
1055 | |
---|
1056 | // trace replicated peripherals |
---|
1057 | //clusters[1][1]->mdma->print_trace(); |
---|
1058 | //clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1"); |
---|
1059 | //clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1"); |
---|
1060 | |
---|
1061 | |
---|
1062 | // trace external peripherals |
---|
1063 | //size_t io_x = cluster_io_id / Y_SIZE; |
---|
1064 | //size_t io_y = cluster_io_id % Y_SIZE; |
---|
1065 | |
---|
1066 | //clusters[io_x][io_y]->brom->print_trace(); |
---|
1067 | //clusters[io_x][io_y]->signal_vci_tgt_brom.print_trace("[SIG]BROM"); |
---|
1068 | |
---|
1069 | //clusters[io_x][io_y]->bdev->print_trace(); |
---|
1070 | //clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); |
---|
1071 | //clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); |
---|
1072 | } |
---|
1073 | |
---|
1074 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
1075 | } |
---|
1076 | } |
---|
1077 | else { |
---|
1078 | int64_t n = 0; |
---|
1079 | while (!stop_called && n != ncycles) { |
---|
1080 | if (gettimeofday(&t1, NULL) != 0) { |
---|
1081 | perror("gettimeofday"); |
---|
1082 | return EXIT_FAILURE; |
---|
1083 | } |
---|
1084 | int64_t nb_cycles = min(max_cycles, ncycles - n); |
---|
1085 | if (do_reset_counters) { |
---|
1086 | nb_cycles = min(nb_cycles, reset_counters - n); |
---|
1087 | } |
---|
1088 | if (do_dump_counters) { |
---|
1089 | nb_cycles = min(nb_cycles, dump_counters - n); |
---|
1090 | } |
---|
1091 | |
---|
1092 | sc_start(sc_core::sc_time(nb_cycles, SC_NS)); |
---|
1093 | n += nb_cycles; |
---|
1094 | |
---|
1095 | if (do_reset_counters && n == reset_counters) { |
---|
1096 | // Reseting counters |
---|
1097 | for (size_t x = 0; x < (X_SIZE); x++) { |
---|
1098 | for (size_t y = 0; y < Y_SIZE; y++) { |
---|
1099 | clusters[x][y]->memc->reset_counters(); |
---|
1100 | } |
---|
1101 | } |
---|
1102 | do_reset_counters = false; |
---|
1103 | } |
---|
1104 | |
---|
1105 | if (do_dump_counters && n == dump_counters) { |
---|
1106 | // Dumping counters |
---|
1107 | for (size_t x = 0; x < (X_SIZE); x++) { |
---|
1108 | for (size_t y = 0; y < Y_SIZE; y++) { |
---|
1109 | clusters[x][y]->memc->print_stats(true, false); |
---|
1110 | } |
---|
1111 | } |
---|
1112 | do_dump_counters = false; |
---|
1113 | } |
---|
1114 | |
---|
1115 | |
---|
1116 | if (gettimeofday(&t2, NULL) != 0) { |
---|
1117 | perror("gettimeofday"); |
---|
1118 | return EXIT_FAILURE; |
---|
1119 | } |
---|
1120 | ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000; |
---|
1121 | ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; |
---|
1122 | std::cerr << std::dec << "cycle " << n << " platform clock frequency " << (double) nb_cycles / (double) (ms2 - ms1) << "Khz" << std::endl; |
---|
1123 | } |
---|
1124 | } |
---|
1125 | |
---|
1126 | |
---|
1127 | // Free memory |
---|
1128 | for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) |
---|
1129 | { |
---|
1130 | size_t x = i / Y_SIZE; |
---|
1131 | size_t y = i % Y_SIZE; |
---|
1132 | delete clusters[x][y]; |
---|
1133 | } |
---|
1134 | |
---|
1135 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_inc, X_SIZE - 1, Y_SIZE, 3); |
---|
1136 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_dec, X_SIZE - 1, Y_SIZE, 3); |
---|
1137 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_inc, X_SIZE - 1, Y_SIZE, 2); |
---|
1138 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_dec, X_SIZE - 1, Y_SIZE, 2); |
---|
1139 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_inc, X_SIZE, Y_SIZE - 1, 3); |
---|
1140 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_dec, X_SIZE, Y_SIZE - 1, 3); |
---|
1141 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_inc, X_SIZE, Y_SIZE - 1, 2); |
---|
1142 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_dec, X_SIZE, Y_SIZE - 1, 2); |
---|
1143 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_false_cmd_in, X_SIZE, Y_SIZE, 4, 3); |
---|
1144 | dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_false_cmd_out, X_SIZE, Y_SIZE, 4, 3); |
---|
1145 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_false_rsp_in, X_SIZE, Y_SIZE, 4, 2); |
---|
1146 | dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_false_rsp_out, X_SIZE, Y_SIZE, 4, 2); |
---|
1147 | |
---|
1148 | return EXIT_SUCCESS; |
---|
1149 | } |
---|
1150 | |
---|
1151 | |
---|
1152 | void handler(int dummy = 0) { |
---|
1153 | stop_called = true; |
---|
1154 | sc_stop(); |
---|
1155 | } |
---|
1156 | |
---|
1157 | void voidhandler(int dummy = 0) {} |
---|
1158 | |
---|
1159 | int sc_main (int argc, char *argv[]) |
---|
1160 | { |
---|
1161 | signal(SIGINT, handler); |
---|
1162 | signal(SIGPIPE, voidhandler); |
---|
1163 | |
---|
1164 | try { |
---|
1165 | return _main(argc, argv); |
---|
1166 | } catch (std::exception &e) { |
---|
1167 | std::cout << e.what() << std::endl; |
---|
1168 | } catch (...) { |
---|
1169 | std::cout << "Unknown exception occured" << std::endl; |
---|
1170 | throw; |
---|
1171 | } |
---|
1172 | return 1; |
---|
1173 | } |
---|
1174 | |
---|
1175 | |
---|
1176 | // Local Variables: |
---|
1177 | // tab-width: 3 |
---|
1178 | // c-basic-offset: 3 |
---|
1179 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
1180 | // indent-tabs-mode: nil |
---|
1181 | // End: |
---|
1182 | |
---|
1183 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|