1 | ///////////////////////////////////////////////////////////////////////// |
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2 | // File: top.cpp |
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3 | // Author: Alain Greiner |
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4 | // Copyright: UPMC/LIP6 |
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5 | // Date : august 2012 |
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6 | // This program is released under the GNU public license |
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7 | ///////////////////////////////////////////////////////////////////////// |
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8 | // This file define a generic TSAR architecture with virtual memory. |
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9 | // The physical address space is 32 bits. |
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10 | // The number of clusters cannot be larger than 256. |
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11 | // The number of processors per cluster cannot be larger than 8. |
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12 | // |
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13 | // - It uses four dspin_local_crossbar per cluster as local interconnect |
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14 | // - It uses two virtual_dspin routers per cluster as global interconnect |
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15 | // - It uses the vci_cc_vcache_wrapper |
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16 | // - It uses the vci_mem_cache |
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17 | // - It contains one vci_xicu and one vci_multi_dma per cluster. |
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18 | // |
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19 | // All clusters are identical, but the cluster containing address |
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20 | // 0xBFC00000 (called io_cluster), contains 5 extra components: |
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21 | // - the boot rom (BROM) |
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22 | // - the disk controller (BDEV) |
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23 | // - the multi-channel network controller (MNIC) |
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24 | // - the multi-channel tty controller (MTTY) |
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25 | // - the frame buffer controller (FBUF) |
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26 | // |
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27 | // It is build with one single component implementing a cluster: |
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28 | // The Tsarv4ClusterMmu component is defined in files |
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29 | // tsarv4_cluster_mmu.* (with * = cpp, h, sd) |
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30 | // |
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31 | // The IRQs are connected to XICUs as follow: |
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32 | // - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters. |
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33 | // - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters. |
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34 | // - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster. |
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35 | // - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. |
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36 | // |
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37 | // The main hardware parameters must be defined in the hard_config.h file : |
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38 | // - CLUSTER_X : number of clusters in a row (power of 2) |
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39 | // - CLUSTER_Y : number of clusters in a column (power of 2) |
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40 | // - CLUSTER_SIZE : size of the segment allocated to a cluster |
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41 | // - NB_PROCS_MAX : number of processors per cluster (power of 2) |
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42 | // - NB_DMAS_MAX : number of DMA channels per cluster (< 9) |
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43 | // - NB_TTYS : number of TTY channels in I/O cluster (< 16) |
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44 | // - NB_NICS : number of NIC channels in I/O cluster (< 9) |
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45 | // |
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46 | // Some secondary hardware parameters must be defined in this top.cpp file: |
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47 | // - XRAM_LATENCY : external ram latency |
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48 | // - MEMC_WAYS : L2 cache number of ways |
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49 | // - MEMC_SETS : L2 cache number of sets |
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50 | // - L1_IWAYS |
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51 | // - L1_ISETS |
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52 | // - L1_DWAYS |
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53 | // - L1_DSETS |
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54 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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55 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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56 | // - BDEV_SECTOR_SIZE : block size for block drvice |
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57 | // - BDEV_IMAGE_NAME : file pathname for block device |
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58 | // - NIC_RX_NAME : file pathname for NIC received packets |
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59 | // - NIC_TX_NAME : file pathname for NIC transmited packets |
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60 | // - NIC_TIMEOUT : max number of cycles before closing a container |
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61 | // |
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62 | // General policy for 32 bits physical address decoding: |
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63 | // All segments base addresses are multiple of 64 Kbytes |
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64 | // Therefore the 16 address MSB bits completely define the target: |
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65 | // The (x_width + y_width) MSB bits (left aligned) define |
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66 | // the cluster index, and the 8 LSB bits define the local index: |
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67 | // | X_ID | Y_ID |---| LADR | OFFSET | |
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68 | // |x_width|y_width|---| 8 | 16 | |
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69 | // |
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70 | // General policy for hardware component indexing: |
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71 | // Each component is identified by (x_id,y_id,l_id) tuple. |
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72 | // | X_ID | Y_ID | L_ID | |
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73 | // |x_width|y_width| 4 | |
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74 | ///////////////////////////////////////////////////////////////////////// |
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75 | |
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76 | #include <systemc> |
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77 | #include <sys/time.h> |
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78 | #include <iostream> |
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79 | #include <sstream> |
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80 | #include <cstdlib> |
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81 | #include <cstdarg> |
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82 | #include <stdint.h> |
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83 | |
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84 | #include "gdbserver.h" |
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85 | #include "mapping_table.h" |
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86 | #include "tsar_xbar_cluster.h" |
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87 | #include "alloc_elems.h" |
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88 | |
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89 | /////////////////////////////////////////////////// |
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90 | // OS |
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91 | /////////////////////////////////////////////////// |
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92 | #define USE_ALMOS 0 |
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93 | |
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94 | #define almos_bootloader_pathname "bootloader.bin" |
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95 | #define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D" |
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96 | #define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D" |
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97 | |
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98 | /////////////////////////////////////////////////// |
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99 | // Parallelisation |
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100 | /////////////////////////////////////////////////// |
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101 | #define USE_OPENMP 0 |
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102 | |
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103 | #if USE_OPENMP |
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104 | #include <omp.h> |
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105 | #endif |
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106 | |
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107 | // cluster index (computed from x,y coordinates) |
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108 | #define cluster(x,y) (y + CLUSTER_Y*x) |
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109 | |
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110 | /////////////////////////////////////////////////////////// |
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111 | // DSPIN parameters |
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112 | /////////////////////////////////////////////////////////// |
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113 | |
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114 | #define cmd_width 40 |
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115 | #define rsp_width 33 |
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116 | |
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117 | /////////////////////////////////////////////////////////// |
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118 | // VCI parameters |
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119 | /////////////////////////////////////////////////////////// |
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120 | |
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121 | #define cell_width 4 |
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122 | #define address_width 32 |
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123 | #define plen_width 8 |
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124 | #define error_width 2 |
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125 | #define clen_width 1 |
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126 | #define rflag_width 1 |
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127 | #define srcid_width 14 |
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128 | #define pktid_width 4 |
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129 | #define trdid_width 4 |
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130 | #define wrplen_width 1 |
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131 | |
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132 | //////////////////////////////////////////////////////////// |
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133 | // Main Hardware Parameters values |
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134 | //////////////////////i///////////////////////////////////// |
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135 | |
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136 | #include "giet_vm/hard_config.h" |
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137 | |
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138 | //////////////////////////////////////////////////////////// |
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139 | // Secondary Hardware Parameters values |
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140 | //////////////////////i///////////////////////////////////// |
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141 | |
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142 | #define XRAM_LATENCY 0 |
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143 | |
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144 | #define MEMC_WAYS 16 |
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145 | #define MEMC_SETS 256 |
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146 | |
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147 | #define L1_IWAYS 4 |
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148 | #define L1_ISETS 64 |
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149 | |
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150 | #define L1_DWAYS 4 |
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151 | #define L1_DSETS 64 |
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152 | |
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153 | #define FBUF_X_SIZE 128 |
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154 | #define FBUF_Y_SIZE 128 |
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155 | |
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156 | #define BDEV_SECTOR_SIZE 512 |
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157 | #define BDEV_IMAGE_NAME "giet_vm/display/images.raw" |
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158 | |
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159 | #define NIC_RX_NAME "giet_vm/nic/rx_data.txt" |
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160 | #define NIC_TX_NAME "giet_vm/nic/tx_data.txt" |
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161 | #define NIC_TIMEOUT 10000 |
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162 | |
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163 | //////////////////////////////////////////////////////////// |
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164 | // Software to be loaded in ROM & RAM |
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165 | //////////////////////i///////////////////////////////////// |
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166 | |
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167 | #define BOOT_SOFT_NAME "giet_vm/soft.elf" |
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168 | |
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169 | //////////////////////////////////////////////////////////// |
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170 | // DEBUG Parameters default values |
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171 | //////////////////////i///////////////////////////////////// |
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172 | |
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173 | #define MAX_FROZEN_CYCLES 10000 |
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174 | |
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175 | #define TRACE_MEMC_ID 0 |
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176 | #define TRACE_PROC_ID 0 |
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177 | |
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178 | ///////////////////////////////////////////////////////// |
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179 | // Physical segments definition |
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180 | ///////////////////////////////////////////////////////// |
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181 | // There is 3 segments replicated in all clusters |
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182 | // and 5 specific segments in the "IO" cluster |
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183 | // (containing address 0xBF000000) |
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184 | ///////////////////////////////////////////////////////// |
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185 | |
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186 | // specific segments in "IO" cluster : absolute physical address |
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187 | |
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188 | #define BROM_BASE 0xBFC00000 |
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189 | #define BROM_SIZE 0x00100000 // 1 Mbytes |
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190 | |
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191 | #define FBUF_BASE 0xBFD00000 |
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192 | #define FBUF_SIZE 0x00200000 // 2 Mbytes |
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193 | |
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194 | #define BDEV_BASE 0xBFF10000 |
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195 | #define BDEV_SIZE 0x00001000 // 4 Kbytes |
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196 | |
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197 | #define MTTY_BASE 0xBFF20000 |
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198 | #define MTTY_SIZE 0x00001000 // 4 Kbytes |
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199 | |
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200 | #define MNIC_BASE 0xBFF80000 |
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201 | #define MNIC_SIZE 0x00002000 * (NB_NICS + 1) // 8 Kbytes per channel + 8 Kbytes |
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202 | |
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203 | // replicated segments : address is incremented by a cluster offset |
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204 | // offset = cluster(x,y) << (address_width-x_width-y_width); |
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205 | |
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206 | #define MEMC_BASE 0x00000000 |
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207 | #define MEMC_SIZE 0x00C00000 // 12 Mbytes |
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208 | |
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209 | #define XICU_BASE 0x00F00000 |
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210 | #define XICU_SIZE 0x00001000 // 4 Kbytes |
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211 | |
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212 | #define CDMA_BASE 0x00F30000 |
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213 | #define CDMA_SIZE 0x00001000 * NB_DMAS_MAX // 4 Kbytes per channel |
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214 | |
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215 | //////////////////////////////////////////////////////////////////// |
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216 | // TGTID definition in direct space |
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217 | // For all components: global TGTID = global SRCID = cluster_index |
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218 | //////////////////////////////////////////////////////////////////// |
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219 | |
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220 | #define MEMC_TGTID 0 |
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221 | #define XICU_TGTID 1 |
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222 | #define CDMA_TGTID 2 |
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223 | #define MTTY_TGTID 3 |
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224 | #define FBUF_TGTID 4 |
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225 | #define BROM_TGTID 5 |
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226 | #define BDEV_TGTID 6 |
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227 | #define MNIC_TGTID 7 |
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228 | |
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229 | ///////////////////////////////// |
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230 | int _main(int argc, char *argv[]) |
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231 | { |
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232 | using namespace sc_core; |
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233 | using namespace soclib::caba; |
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234 | using namespace soclib::common; |
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235 | |
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236 | |
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237 | char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code |
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238 | size_t ncycles = 1000000000; // simulated cycles |
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239 | char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image |
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240 | char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file |
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241 | char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file |
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242 | ssize_t threads_nr = 1; // simulator's threads number |
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243 | bool debug_ok = false; // trace activated |
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244 | size_t debug_period = 1; // trace period |
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245 | size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced (cluster_id) |
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246 | size_t debug_proc_id = TRACE_PROC_ID; // index of proc to be traced |
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247 | uint32_t debug_from = 0; // trace start cycle |
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248 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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249 | |
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250 | ////////////// command line arguments ////////////////////// |
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251 | if (argc > 1) |
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252 | { |
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253 | for (int n = 1; n < argc; n = n + 2) |
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254 | { |
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255 | if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc)) |
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256 | { |
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257 | ncycles = atoi(argv[n+1]); |
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258 | } |
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259 | else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ) |
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260 | { |
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261 | strcpy(soft_name, argv[n+1]); |
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262 | } |
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263 | else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) |
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264 | { |
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265 | strcpy(disk_name, argv[n+1]); |
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266 | } |
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267 | else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) |
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268 | { |
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269 | debug_ok = true; |
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270 | debug_from = atoi(argv[n+1]); |
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271 | } |
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272 | else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) ) |
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273 | { |
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274 | debug_memc_id = atoi(argv[n+1]); |
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275 | assert( (debug_memc_id < (CLUSTER_X*CLUSTER_Y) ) && |
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276 | "debug_memc_id larger than XMAX * YMAX" ); |
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277 | } |
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278 | else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) ) |
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279 | { |
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280 | debug_proc_id = atoi(argv[n+1]); |
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281 | assert( (debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) && |
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282 | "debug_proc_id larger than XMAX * YMAX * NB_PROCS" ); |
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283 | } |
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284 | else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) |
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285 | { |
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286 | threads_nr = atoi(argv[n+1]); |
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287 | threads_nr = (threads_nr < 1) ? 1 : threads_nr; |
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288 | } |
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289 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) |
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290 | { |
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291 | frozen_cycles = atoi(argv[n+1]); |
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292 | } |
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293 | else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)) |
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294 | { |
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295 | debug_period = atoi(argv[n+1]); |
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296 | } |
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297 | else |
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298 | { |
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299 | std::cout << " Arguments are (key,value) couples." << std::endl; |
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300 | std::cout << " The order is not important." << std::endl; |
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301 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
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302 | std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; |
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303 | std::cout << " -DISK pathname_for_disk_image" << std::endl; |
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304 | std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; |
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305 | std::cout << " -DEBUG debug_start_cycle" << std::endl; |
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306 | std::cout << " -THREADS simulator's threads number" << std::endl; |
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307 | std::cout << " -FROZEN max_number_of_lines" << std::endl; |
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308 | std::cout << " -PERIOD number_of_cycles between trace" << std::endl; |
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309 | std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; |
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310 | std::cout << " -PROCID index_proc_to_be_traced" << std::endl; |
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311 | exit(0); |
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312 | } |
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313 | } |
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314 | } |
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315 | |
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316 | // checking hardware parameters |
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317 | assert( ( (CLUSTER_X == 1) or (CLUSTER_X == 2) or (CLUSTER_X == 4) or |
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318 | (CLUSTER_X == 8) or (CLUSTER_X == 16) ) and |
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319 | "The CLUSTER_X parameter must be 1, 2, 4, 8 or 16" ); |
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320 | |
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321 | assert( ( (CLUSTER_Y == 1) or (CLUSTER_Y == 2) or (CLUSTER_Y == 4) or |
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322 | (CLUSTER_Y == 8) or (CLUSTER_Y == 16) ) and |
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323 | "The CLUSTER_Y parameter must be 1, 2, 4, 8 or 16" ); |
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324 | |
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325 | assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or |
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326 | (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and |
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327 | "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" ); |
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328 | |
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329 | assert( (NB_DMAS_MAX < 9) and |
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330 | "The NB_DMAS_MAX parameter must be smaller than 9" ); |
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331 | |
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332 | assert( (NB_TTYS < 15) and |
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333 | "The NB_TTYS parameter must be smaller than 15" ); |
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334 | |
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335 | assert( (NB_NICS < 9) and |
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336 | "The NB_NICS parameter must be smaller than 9" ); |
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337 | |
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338 | std::cout << std::endl; |
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339 | std::cout << " - CLUSTER_X = " << CLUSTER_X << std::endl; |
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340 | std::cout << " - CLUSTER_Y = " << CLUSTER_Y << std::endl; |
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341 | std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; |
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342 | std::cout << " - NB_DMAS_MAX = " << NB_DMAS_MAX << std::endl; |
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343 | std::cout << " - NB_TTYS = " << NB_TTYS << std::endl; |
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344 | std::cout << " - NB_NICS = " << NB_NICS << std::endl; |
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345 | std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; |
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346 | std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; |
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347 | std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; |
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348 | std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; |
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349 | |
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350 | std::cout << std::endl; |
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351 | |
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352 | #if USE_OPENMP |
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353 | omp_set_dynamic(false); |
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354 | omp_set_num_threads(threads_nr); |
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355 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
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356 | #endif |
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357 | |
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358 | // Define VCI parameters |
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359 | typedef soclib::caba::VciParams<cell_width, |
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360 | plen_width, |
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361 | address_width, |
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362 | error_width, |
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363 | clen_width, |
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364 | rflag_width, |
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365 | srcid_width, |
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366 | pktid_width, |
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367 | trdid_width, |
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368 | wrplen_width> vci_param; |
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369 | |
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370 | // Define parameters depending on mesh size |
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371 | size_t cluster_io_id; |
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372 | size_t x_width; |
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373 | size_t y_width; |
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374 | |
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375 | if (CLUSTER_X == 1) x_width = 0; |
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376 | else if (CLUSTER_X == 2) x_width = 1; |
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377 | else if (CLUSTER_X <= 4) x_width = 2; |
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378 | else if (CLUSTER_X <= 8) x_width = 3; |
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379 | else x_width = 4; |
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380 | |
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381 | if (CLUSTER_Y == 1) y_width = 0; |
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382 | else if (CLUSTER_Y == 2) y_width = 1; |
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383 | else if (CLUSTER_Y <= 4) y_width = 2; |
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384 | else if (CLUSTER_Y <= 8) y_width = 3; |
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385 | else y_width = 4; |
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386 | |
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387 | cluster_io_id = 0xBF >> (8 - x_width - y_width); |
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388 | |
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389 | ///////////////////// |
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390 | // Mapping Tables |
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391 | ///////////////////// |
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392 | |
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393 | // direct network |
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394 | MappingTable maptabd(address_width, |
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395 | IntTab(x_width + y_width, 16 - x_width - y_width), |
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396 | IntTab(x_width + y_width, srcid_width - x_width - y_width), |
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397 | 0x00FF0000); |
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398 | |
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399 | for (size_t x = 0; x < CLUSTER_X; x++) |
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400 | { |
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401 | for (size_t y = 0; y < CLUSTER_Y; y++) |
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402 | { |
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403 | sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); |
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404 | |
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405 | std::ostringstream sh; |
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406 | sh << "d_seg_memc_" << x << "_" << y; |
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407 | maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true)); |
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408 | |
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409 | std::ostringstream si; |
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410 | si << "d_seg_xicu_" << x << "_" << y; |
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411 | maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false)); |
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412 | |
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413 | std::ostringstream sd; |
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414 | sd << "d_seg_mdma_" << x << "_" << y; |
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415 | maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false)); |
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416 | |
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417 | if ( cluster(x,y) == cluster_io_id ) |
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418 | { |
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419 | maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false)); |
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420 | maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false)); |
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421 | maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false)); |
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422 | maptabd.add(Segment("d_seg_mnic", MNIC_BASE, MNIC_SIZE, IntTab(cluster(x,y),MNIC_TGTID), false)); |
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423 | maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true)); |
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424 | } |
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425 | } |
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426 | } |
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427 | std::cout << maptabd << std::endl; |
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428 | |
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429 | /* |
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430 | WE DONT NEED any COHERENCE MAPPING TABLE, AS THE DIRECT NETWORK |
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431 | USES DIRECT ADRESSING (XID,YID,LID) |
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432 | |
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433 | // coherence network |
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434 | // - tgtid_c_proc = srcid_c_proc = local procid |
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435 | // - tgtid_c_memc = srcid_c_memc = NB_PROCS_MAX |
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436 | MappingTable maptabc(address_width, |
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437 | IntTab(x_width + y_width, srcid_width - x_width - y_width), |
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438 | IntTab(x_width + y_width, srcid_width - x_width - y_width), |
---|
439 | 0x00FF0000); |
---|
440 | |
---|
441 | for (size_t x = 0; x < CLUSTER_X; x++) |
---|
442 | { |
---|
443 | for (size_t y = 0; y < CLUSTER_Y; y++) |
---|
444 | { |
---|
445 | sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); |
---|
446 | |
---|
447 | // cleanup requests must be routed to the memory cache |
---|
448 | std::ostringstream sh; |
---|
449 | sh << "c_seg_memc_" << x << "_" << y; |
---|
450 | maptabc.add(Segment(sh.str(), (NB_PROCS_MAX << (address_width - srcid_width)) + offset, |
---|
451 | 0x10, IntTab(cluster(x,y), NB_PROCS_MAX), false)); |
---|
452 | |
---|
453 | // update & invalidate requests must be routed to the proper processor |
---|
454 | for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++) |
---|
455 | { |
---|
456 | std::ostringstream sp; |
---|
457 | sp << "c_seg_proc_" << x << "_" << y << "_" << p; |
---|
458 | maptabc.add( Segment( sp.str() , (p << (address_width - srcid_width)) + offset , |
---|
459 | 0x10 , IntTab(cluster(x,y), p) , false)); |
---|
460 | } |
---|
461 | } |
---|
462 | } |
---|
463 | std::cout << maptabc << std::endl; |
---|
464 | |
---|
465 | */ |
---|
466 | |
---|
467 | // external network |
---|
468 | MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000); |
---|
469 | |
---|
470 | for (size_t x = 0; x < CLUSTER_X; x++) |
---|
471 | { |
---|
472 | for (size_t y = 0; y < CLUSTER_Y ; y++) |
---|
473 | { |
---|
474 | sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); |
---|
475 | std::ostringstream sh; |
---|
476 | sh << "x_seg_memc_" << x << "_" << y; |
---|
477 | maptabx.add(Segment(sh.str(), MEMC_BASE+offset, |
---|
478 | MEMC_SIZE, IntTab(cluster(x,y)), false)); |
---|
479 | } |
---|
480 | } |
---|
481 | std::cout << maptabx << std::endl; |
---|
482 | |
---|
483 | //////////////////// |
---|
484 | // Signals |
---|
485 | /////////////////// |
---|
486 | |
---|
487 | sc_clock signal_clk("clk"); |
---|
488 | sc_signal<bool> signal_resetn("resetn"); |
---|
489 | |
---|
490 | // Horizontal inter-clusters DSPIN signals |
---|
491 | DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc = |
---|
492 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2); |
---|
493 | DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec = |
---|
494 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2); |
---|
495 | DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc = |
---|
496 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2); |
---|
497 | DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec = |
---|
498 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2); |
---|
499 | |
---|
500 | // Vertical inter-clusters DSPIN signals |
---|
501 | DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc = |
---|
502 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2); |
---|
503 | DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec = |
---|
504 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2); |
---|
505 | DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc = |
---|
506 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2); |
---|
507 | DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec = |
---|
508 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2); |
---|
509 | |
---|
510 | // Mesh boundaries DSPIN signals |
---|
511 | DspinSignals<cmd_width>**** signal_dspin_false_cmd_in = |
---|
512 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4); |
---|
513 | DspinSignals<cmd_width>**** signal_dspin_false_cmd_out = |
---|
514 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4); |
---|
515 | DspinSignals<rsp_width>**** signal_dspin_false_rsp_in = |
---|
516 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4); |
---|
517 | DspinSignals<rsp_width>**** signal_dspin_false_rsp_out = |
---|
518 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4); |
---|
519 | |
---|
520 | |
---|
521 | //////////////////////////// |
---|
522 | // Loader |
---|
523 | //////////////////////////// |
---|
524 | |
---|
525 | #if USE_ALMOS |
---|
526 | soclib::common::Loader loader(almos_bootloader_pathname, |
---|
527 | almos_archinfo_pathname, |
---|
528 | almos_kernel_pathname); |
---|
529 | #else |
---|
530 | soclib::common::Loader loader(soft_name); |
---|
531 | #endif |
---|
532 | |
---|
533 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
534 | proc_iss::set_loader(loader); |
---|
535 | |
---|
536 | //////////////////////////// |
---|
537 | // Clusters construction |
---|
538 | //////////////////////////// |
---|
539 | |
---|
540 | TsarXbarCluster<vci_param, proc_iss, cmd_width, rsp_width>* clusters[CLUSTER_X][CLUSTER_Y]; |
---|
541 | |
---|
542 | #if USE_OPENMP |
---|
543 | #pragma omp parallel |
---|
544 | { |
---|
545 | #pragma omp for |
---|
546 | #endif |
---|
547 | for(size_t i = 0; i < (CLUSTER_X * CLUSTER_Y); i++) |
---|
548 | { |
---|
549 | size_t x = i / CLUSTER_Y; |
---|
550 | size_t y = i % CLUSTER_Y; |
---|
551 | |
---|
552 | #if USE_OPENMP |
---|
553 | #pragma omp critical |
---|
554 | { |
---|
555 | #endif |
---|
556 | std::ostringstream sc; |
---|
557 | sc << "cluster_" << x << "_" << y; |
---|
558 | clusters[x][y] = new TsarXbarCluster<vci_param, proc_iss, cmd_width, rsp_width> |
---|
559 | ( |
---|
560 | sc.str().c_str(), |
---|
561 | NB_PROCS_MAX, |
---|
562 | NB_TTYS, |
---|
563 | NB_DMAS_MAX, |
---|
564 | x, |
---|
565 | y, |
---|
566 | cluster(x,y), |
---|
567 | maptabd, |
---|
568 | maptabx, |
---|
569 | x_width, |
---|
570 | y_width, |
---|
571 | srcid_width - x_width - y_width, // l_id width, |
---|
572 | MEMC_TGTID, |
---|
573 | XICU_TGTID, |
---|
574 | CDMA_TGTID, |
---|
575 | FBUF_TGTID, |
---|
576 | MTTY_TGTID, |
---|
577 | BROM_TGTID, |
---|
578 | MNIC_TGTID, |
---|
579 | BDEV_TGTID, |
---|
580 | MEMC_WAYS, |
---|
581 | MEMC_SETS, |
---|
582 | L1_IWAYS, |
---|
583 | L1_ISETS, |
---|
584 | L1_DWAYS, |
---|
585 | L1_DSETS, |
---|
586 | XRAM_LATENCY, |
---|
587 | (cluster(x,y) == cluster_io_id), |
---|
588 | FBUF_X_SIZE, |
---|
589 | FBUF_Y_SIZE, |
---|
590 | disk_name, |
---|
591 | BDEV_SECTOR_SIZE, |
---|
592 | NB_NICS, |
---|
593 | nic_rx_name, |
---|
594 | nic_tx_name, |
---|
595 | NIC_TIMEOUT, |
---|
596 | loader, |
---|
597 | frozen_cycles, |
---|
598 | debug_from, |
---|
599 | debug_ok and (cluster(x,y) == debug_memc_id), |
---|
600 | debug_ok and (cluster(x,y) == debug_proc_id) |
---|
601 | ); |
---|
602 | |
---|
603 | std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; |
---|
604 | #if USE_OPENMP |
---|
605 | } // end critical |
---|
606 | #endif |
---|
607 | } // end for |
---|
608 | #if USE_OPENMP |
---|
609 | } |
---|
610 | #endif |
---|
611 | |
---|
612 | /////////////////////////////////////////////////////////////// |
---|
613 | // Net-list |
---|
614 | /////////////////////////////////////////////////////////////// |
---|
615 | |
---|
616 | // Clock & RESET |
---|
617 | for (size_t x = 0; x < (CLUSTER_X); x++){ |
---|
618 | for (size_t y = 0; y < CLUSTER_Y; y++){ |
---|
619 | clusters[x][y]->p_clk (signal_clk); |
---|
620 | clusters[x][y]->p_resetn (signal_resetn); |
---|
621 | } |
---|
622 | } |
---|
623 | |
---|
624 | // Inter Clusters horizontal connections |
---|
625 | if (CLUSTER_X > 1){ |
---|
626 | for (size_t x = 0; x < (CLUSTER_X-1); x++){ |
---|
627 | for (size_t y = 0; y < CLUSTER_Y; y++){ |
---|
628 | for (size_t k = 0; k < 2; k++){ |
---|
629 | clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]); |
---|
630 | clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]); |
---|
631 | clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]); |
---|
632 | clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]); |
---|
633 | clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]); |
---|
634 | clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]); |
---|
635 | clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]); |
---|
636 | clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]); |
---|
637 | } |
---|
638 | } |
---|
639 | } |
---|
640 | } |
---|
641 | std::cout << std::endl << "Horizontal connections established" << std::endl; |
---|
642 | |
---|
643 | // Inter Clusters vertical connections |
---|
644 | if (CLUSTER_Y > 1) { |
---|
645 | for (size_t y = 0; y < (CLUSTER_Y-1); y++){ |
---|
646 | for (size_t x = 0; x < CLUSTER_X; x++){ |
---|
647 | for (size_t k = 0; k < 2; k++){ |
---|
648 | clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]); |
---|
649 | clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]); |
---|
650 | clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]); |
---|
651 | clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]); |
---|
652 | clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]); |
---|
653 | clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]); |
---|
654 | clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]); |
---|
655 | clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]); |
---|
656 | } |
---|
657 | } |
---|
658 | } |
---|
659 | } |
---|
660 | std::cout << "Vertical connections established" << std::endl; |
---|
661 | |
---|
662 | // East & West boundary cluster connections |
---|
663 | for (size_t y = 0; y < CLUSTER_Y; y++) |
---|
664 | { |
---|
665 | for (size_t k = 0; k < 2; k++) |
---|
666 | { |
---|
667 | clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]); |
---|
668 | clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]); |
---|
669 | clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]); |
---|
670 | clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]); |
---|
671 | |
---|
672 | clusters[CLUSTER_X-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[CLUSTER_X-1][y][k][EAST]); |
---|
673 | clusters[CLUSTER_X-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[CLUSTER_X-1][y][k][EAST]); |
---|
674 | clusters[CLUSTER_X-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[CLUSTER_X-1][y][k][EAST]); |
---|
675 | clusters[CLUSTER_X-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[CLUSTER_X-1][y][k][EAST]); |
---|
676 | } |
---|
677 | } |
---|
678 | |
---|
679 | // North & South boundary clusters connections |
---|
680 | for (size_t x = 0; x < CLUSTER_X; x++) |
---|
681 | { |
---|
682 | for (size_t k = 0; k < 2; k++) |
---|
683 | { |
---|
684 | clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]); |
---|
685 | clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]); |
---|
686 | clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]); |
---|
687 | clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]); |
---|
688 | |
---|
689 | clusters[x][CLUSTER_Y-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][CLUSTER_Y-1][k][NORTH]); |
---|
690 | clusters[x][CLUSTER_Y-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][CLUSTER_Y-1][k][NORTH]); |
---|
691 | clusters[x][CLUSTER_Y-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][CLUSTER_Y-1][k][NORTH]); |
---|
692 | clusters[x][CLUSTER_Y-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][CLUSTER_Y-1][k][NORTH]); |
---|
693 | } |
---|
694 | } |
---|
695 | |
---|
696 | |
---|
697 | //////////////////////////////////////////////////////// |
---|
698 | // Simulation |
---|
699 | /////////////////////////////////////////////////////// |
---|
700 | |
---|
701 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
702 | signal_resetn = false; |
---|
703 | |
---|
704 | // network boundaries signals |
---|
705 | for (size_t x = 0; x < CLUSTER_X ; x++){ |
---|
706 | for (size_t y = 0; y < CLUSTER_Y ; y++){ |
---|
707 | for (size_t k = 0; k < 2; k++){ |
---|
708 | for (size_t a = 0; a < 4; a++){ |
---|
709 | signal_dspin_false_cmd_in[x][y][k][a].write = false; |
---|
710 | signal_dspin_false_cmd_in[x][y][k][a].read = true; |
---|
711 | signal_dspin_false_cmd_out[x][y][k][a].write = false; |
---|
712 | signal_dspin_false_cmd_out[x][y][k][a].read = true; |
---|
713 | |
---|
714 | signal_dspin_false_rsp_in[x][y][k][a].write = false; |
---|
715 | signal_dspin_false_rsp_in[x][y][k][a].read = true; |
---|
716 | signal_dspin_false_rsp_out[x][y][k][a].write = false; |
---|
717 | signal_dspin_false_rsp_out[x][y][k][a].read = true; |
---|
718 | } |
---|
719 | } |
---|
720 | } |
---|
721 | } |
---|
722 | |
---|
723 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
724 | signal_resetn = true; |
---|
725 | |
---|
726 | for (size_t n = 1; n < ncycles; n++) |
---|
727 | { |
---|
728 | |
---|
729 | if (debug_ok and (n > debug_from) and (n % debug_period == 0)) |
---|
730 | { |
---|
731 | std::cout << "****************** cycle " << std::dec << n ; |
---|
732 | std::cout << " ************************************************" << std::endl; |
---|
733 | /* |
---|
734 | clusters[0][0]->proc[0]->print_trace(); |
---|
735 | clusters[0][0]->signal_vci_ini_proc[0].print_trace("DIRECT proc_0_0_0 vci_ini"); |
---|
736 | clusters[0][0]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_0_0_0"); |
---|
737 | clusters[0][0]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_0_0_0"); |
---|
738 | clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_0_0_0"); |
---|
739 | clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_0_0_0"); |
---|
740 | clusters[0][0]->memc->print_trace(); |
---|
741 | clusters[0][0]->signal_vci_tgt_memc.print_trace("DIRECT memc_0_0_vci_tgt"); |
---|
742 | clusters[0][0]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_0_0"); |
---|
743 | clusters[0][0]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_0_0"); |
---|
744 | clusters[0][0]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_0_0"); |
---|
745 | clusters[0][0]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_0_0"); |
---|
746 | clusters[0][0]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_0_0"); |
---|
747 | clusters[0][0]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_0_0"); |
---|
748 | clusters[0][0]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_0_0"); |
---|
749 | |
---|
750 | clusters[0][1]->proc[0]->print_trace(); |
---|
751 | clusters[0][1]->signal_vci_ini_proc[0].print_trace("DIRECT proc_0_1_0 vci_ini"); |
---|
752 | clusters[0][1]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_0_1_0"); |
---|
753 | clusters[0][1]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_0_1_0"); |
---|
754 | clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_0_1_0"); |
---|
755 | clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_0_1_0"); |
---|
756 | clusters[0][1]->memc->print_trace(); |
---|
757 | clusters[0][1]->signal_vci_tgt_memc.print_trace("DIRECT memc_0_1_vci_tgt"); |
---|
758 | clusters[0][1]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_0_1"); |
---|
759 | clusters[0][1]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_0_1"); |
---|
760 | clusters[0][1]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_0_1"); |
---|
761 | clusters[0][1]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_0_1"); |
---|
762 | clusters[0][1]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_0_1"); |
---|
763 | clusters[0][1]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_0_1"); |
---|
764 | clusters[0][1]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_0_1"); |
---|
765 | |
---|
766 | clusters[1][0]->proc[0]->print_trace(); |
---|
767 | clusters[1][0]->signal_vci_ini_proc[0].print_trace("DIRECT proc_1_0_0 vci_ini"); |
---|
768 | clusters[1][0]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_1_0_0"); |
---|
769 | clusters[1][0]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_1_0_0"); |
---|
770 | clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_1_0_0"); |
---|
771 | clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_1_0_0"); |
---|
772 | clusters[1][0]->memc->print_trace(); |
---|
773 | clusters[1][0]->signal_vci_tgt_memc.print_trace("DIRECT memc_1_0_vci_tgt"); |
---|
774 | clusters[1][0]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_1_0"); |
---|
775 | clusters[1][0]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_1_0"); |
---|
776 | clusters[1][0]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_1_0"); |
---|
777 | clusters[1][0]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_1_0"); |
---|
778 | clusters[1][0]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_1_0"); |
---|
779 | clusters[1][0]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_1_0"); |
---|
780 | clusters[1][0]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_1_0"); |
---|
781 | |
---|
782 | clusters[1][1]->proc[0]->print_trace(); |
---|
783 | clusters[1][1]->signal_vci_ini_proc[0].print_trace("DIRECT proc_1_1_0 vci_ini"); |
---|
784 | clusters[1][1]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_1_1_0"); |
---|
785 | clusters[1][1]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_1_1_0"); |
---|
786 | clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_1_1_0"); |
---|
787 | clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_1_1_0"); |
---|
788 | clusters[1][1]->memc->print_trace(); |
---|
789 | clusters[1][1]->signal_vci_tgt_memc.print_trace("DIRECT memc_1_1_vci_tgt"); |
---|
790 | clusters[1][1]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_1_1"); |
---|
791 | clusters[1][1]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_1_1"); |
---|
792 | clusters[1][1]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_1_1"); |
---|
793 | clusters[1][1]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_1_1"); |
---|
794 | clusters[1][1]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_1_1"); |
---|
795 | clusters[1][1]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_1_1"); |
---|
796 | clusters[1][1]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_1_1"); |
---|
797 | */ |
---|
798 | /* |
---|
799 | // trace proc[debug_proc_id] |
---|
800 | if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) |
---|
801 | { |
---|
802 | size_t proc_x = debug_proc_id / CLUSTER_Y; |
---|
803 | size_t proc_y = debug_proc_id % CLUSTER_Y; |
---|
804 | |
---|
805 | clusters[proc_x][proc_y]->proc[0]->print_trace(); |
---|
806 | clusters[proc_x][proc_y]->signal_vci_ini_proc[0].print_trace("proc_0"); |
---|
807 | } |
---|
808 | |
---|
809 | // trace memc[debug_memc_id] |
---|
810 | if ( debug_memc_id < (CLUSTER_X * CLUSTER_Y) ) |
---|
811 | { |
---|
812 | size_t memc_x = debug_memc_id / CLUSTER_Y; |
---|
813 | size_t memc_y = debug_memc_id % CLUSTER_Y; |
---|
814 | |
---|
815 | clusters[memc_x][memc_y]->memc->print_trace(); |
---|
816 | clusters[memc_x][memc_y]->signal_vci_tgt_memc.print_trace("memc"); |
---|
817 | } |
---|
818 | */ |
---|
819 | // clusters[0][0]->signal_vci_tgt_xicu.print_trace("xicu_0_0"); |
---|
820 | // clusters[0][1]->signal_vci_tgt_xicu.print_trace("xicu_0_1"); |
---|
821 | // clusters[1][0]->signal_vci_tgt_xicu.print_trace("xicu_1_0"); |
---|
822 | // clusters[1][1]->signal_vci_tgt_xicu.print_trace("xicu_1_1"); |
---|
823 | |
---|
824 | // if ( clusters[1][1]->signal_irq_mdma[0].read() ) |
---|
825 | // std::cout << std::endl << " IRQ_DMA_1_1 activated" << std::endl; |
---|
826 | // if ( clusters[1][1]->signal_proc_it[0].read() ) |
---|
827 | // std::cout << " IRQ_PROC_1_1 activated" << std::endl << std::endl; |
---|
828 | |
---|
829 | // trace ioc component |
---|
830 | // size_t io_x = cluster_io_id / CLUSTER_Y; |
---|
831 | // size_t io_y = cluster_io_id % CLUSTER_Y; |
---|
832 | // clusters[io_x][io_y]->bdev->print_trace(); |
---|
833 | // clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("bdev_tgt "); |
---|
834 | // clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("bdev_ini "); |
---|
835 | |
---|
836 | // clusters[1][1]->mdma->print_trace(); |
---|
837 | // clusters[1][1]->signal_vci_tgt_mdma.print_trace("mdma_1_1_tgt "); |
---|
838 | // clusters[1][1]->signal_vci_ini_mdma.print_trace("mdma_1_1_ini "); |
---|
839 | |
---|
840 | } |
---|
841 | |
---|
842 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
843 | } |
---|
844 | return EXIT_SUCCESS; |
---|
845 | } |
---|
846 | |
---|
847 | int sc_main (int argc, char *argv[]) |
---|
848 | { |
---|
849 | try { |
---|
850 | return _main(argc, argv); |
---|
851 | } catch (std::exception &e) { |
---|
852 | std::cout << e.what() << std::endl; |
---|
853 | } catch (...) { |
---|
854 | std::cout << "Unknown exception occured" << std::endl; |
---|
855 | throw; |
---|
856 | } |
---|
857 | return 1; |
---|
858 | } |
---|
859 | |
---|
860 | |
---|
861 | // Local Variables: |
---|
862 | // tab-width: 3 |
---|
863 | // c-basic-offset: 3 |
---|
864 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
865 | // indent-tabs-mode: nil |
---|
866 | // End: |
---|
867 | |
---|
868 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|
869 | |
---|
870 | |
---|
871 | |
---|
872 | |
---|