source: trunk/platforms/tsar_generic_xbar/top.cpp@ 393

Last change on this file since 393 was 389, checked in by cfuguet, 13 years ago

Modifying the tsar_generic_xbar:

  • Modifying the metadata and the sources of the tsar_xbar_cluster to support two differents VCI parameters (one for the DIRECT network and another for the EXTERNAL network).

The DIRECT network use 32 bits for VCI_DATA and the EXTERNAL network use
64 bits.
File size: 33.9 KB
Line 
1/////////////////////////////////////////////////////////////////////////
2// File: top.cpp
3// Author: Alain Greiner
4// Copyright: UPMC/LIP6
5// Date : august 2012
6// This program is released under the GNU public license
7/////////////////////////////////////////////////////////////////////////
8// This file define a generic TSAR architecture with virtual memory.
9// The physical address space is 32 bits.
10// The number of clusters cannot be larger than 256.
11// The number of processors per cluster cannot be larger than 8.
12//
13// - It uses four dspin_local_crossbar per cluster as local interconnect
14// - It uses two virtual_dspin routers per cluster as global interconnect
15// - It uses the vci_cc_vcache_wrapper
16// - It uses the vci_mem_cache
17// - It contains one vci_xicu and one vci_multi_dma per cluster.
18// - It contains one vci_simple ram per cluster to model the L3 cache.
19//
20// All clusters are identical, but the cluster containing address
21// 0xBFC00000 (called io_cluster), contains 5 extra components:
22// - the boot rom (BROM)
23// - the disk controller (BDEV)
24// - the multi-channel network controller (MNIC)
25// - the multi-channel tty controller (MTTY)
26// - the frame buffer controller (FBUF)
27//
28// It is build with one single component implementing a cluster:
29// The Tsarv4ClusterMmu component is defined in files
30// tsar_xbar_cluster.* (with * = cpp, h, sd)
31//
32// The IRQs are connected to XICUs as follow:
33// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters.
34// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters.
35// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster.
36// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster.
37//
38// The main hardware parameters must be defined in the hard_config.h file :
39// - CLUSTER_X : number of clusters in a row (power of 2)
40// - CLUSTER_Y : number of clusters in a column (power of 2)
41// - CLUSTER_SIZE : size of the segment allocated to a cluster
42// - NB_PROCS_MAX : number of processors per cluster (power of 2)
43// - NB_DMAS_MAX : number of DMA channels per cluster (< 9)
44// - NB_TTYS : number of TTY channels in I/O cluster (< 16)
45// - NB_NICS : number of NIC channels in I/O cluster (< 9)
46//
47// Some secondary hardware parameters must be defined in this top.cpp file:
48// - XRAM_LATENCY : external ram latency
49// - MEMC_WAYS : L2 cache number of ways
50// - MEMC_SETS : L2 cache number of sets
51// - L1_IWAYS
52// - L1_ISETS
53// - L1_DWAYS
54// - L1_DSETS
55// - FBUF_X_SIZE : width of frame buffer (pixels)
56// - FBUF_Y_SIZE : heigth of frame buffer (lines)
57// - BDEV_SECTOR_SIZE : block size for block drvice
58// - BDEV_IMAGE_NAME : file pathname for block device
59// - NIC_RX_NAME : file pathname for NIC received packets
60// - NIC_TX_NAME : file pathname for NIC transmited packets
61// - NIC_TIMEOUT : max number of cycles before closing a container
62//
63// General policy for 32 bits physical address decoding:
64// All segments base addresses are multiple of 64 Kbytes
65// Therefore the 16 address MSB bits completely define the target:
66// The (x_width + y_width) MSB bits (left aligned) define
67// the cluster index, and the 8 LSB bits define the local index:
68// | X_ID | Y_ID |---| LADR | OFFSET |
69// |x_width|y_width|---| 8 | 16 |
70//
71// General policy for hardware component indexing:
72// Each component is identified by (x_id,y_id,l_id) tuple.
73// | X_ID | Y_ID | L_ID |
74// |x_width|y_width| 4 |
75/////////////////////////////////////////////////////////////////////////
76
77#include <systemc>
78#include <sys/time.h>
79#include <iostream>
80#include <sstream>
81#include <cstdlib>
82#include <cstdarg>
83#include <stdint.h>
84
85#include "gdbserver.h"
86#include "mapping_table.h"
87#include "tsar_xbar_cluster.h"
88#include "alloc_elems.h"
89
90///////////////////////////////////////////////////
91// OS
92///////////////////////////////////////////////////
93#define USE_ALMOS 0
94
95#define almos_bootloader_pathname "bootloader.bin"
96#define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D"
97#define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D"
98
99///////////////////////////////////////////////////
100// Parallelisation
101///////////////////////////////////////////////////
102#define USE_OPENMP 0
103
104#if USE_OPENMP
105#include <omp.h>
106#endif
107
108// cluster index (computed from x,y coordinates)
109#define cluster(x,y) (y + CLUSTER_Y*x)
110
111///////////////////////////////////////////////////////////
112// DSPIN parameters
113///////////////////////////////////////////////////////////
114
115#define cmd_width 40
116#define rsp_width 33
117
118////////////////////////////////////////////////////////////
119// Main Hardware Parameters values
120//////////////////////i/////////////////////////////////////
121
122#include "giet_vm/hard_config.h"
123
124////////////////////////////////////////////////////////////
125// Secondary Hardware Parameters values
126//////////////////////i/////////////////////////////////////
127
128#define XRAM_LATENCY 0
129
130#define MEMC_WAYS 16
131#define MEMC_SETS 256
132
133#define L1_IWAYS 4
134#define L1_ISETS 64
135
136#define L1_DWAYS 4
137#define L1_DSETS 64
138
139#define FBUF_X_SIZE 128
140#define FBUF_Y_SIZE 128
141
142#define BDEV_SECTOR_SIZE 512
143#define BDEV_IMAGE_NAME "giet_vm/display/images.raw"
144
145#define NIC_RX_NAME "giet_vm/nic/rx_packets.txt"
146#define NIC_TX_NAME "giet_vm/nic/tx_packets.txt"
147#define NIC_TIMEOUT 10000
148
149////////////////////////////////////////////////////////////
150// Software to be loaded in ROM & RAM
151//////////////////////i/////////////////////////////////////
152
153#define BOOT_SOFT_NAME "giet_vm/soft.elf"
154
155////////////////////////////////////////////////////////////
156// DEBUG Parameters default values
157//////////////////////i/////////////////////////////////////
158
159#define MAX_FROZEN_CYCLES 10000
160
161#define TRACE_MEMC_ID 0
162#define TRACE_PROC_ID 0
163
164/////////////////////////////////////////////////////////
165// Physical segments definition
166/////////////////////////////////////////////////////////
167// There is 3 segments replicated in all clusters
168// and 5 specific segments in the "IO" cluster
169// (containing address 0xBF000000)
170/////////////////////////////////////////////////////////
171
172// specific segments in "IO" cluster : absolute physical address
173
174#define BROM_BASE 0xBFC00000
175#define BROM_SIZE 0x00100000 // 1 Mbytes
176
177#define FBUF_BASE 0xBFD00000
178#define FBUF_SIZE 0x00200000 // 2 Mbytes
179
180#define BDEV_BASE 0xBFF10000
181#define BDEV_SIZE 0x00001000 // 4 Kbytes
182
183#define MTTY_BASE 0xBFF20000
184#define MTTY_SIZE 0x00001000 // 4 Kbytes
185
186#define MNIC_BASE 0xBFF80000
187#define MNIC_SIZE 0x00002000 * (NB_NICS + 1) // 8 Kbytes per channel + 8 Kbytes
188
189// replicated segments : address is incremented by a cluster offset
190// offset = cluster(x,y) << (address_width-x_width-y_width);
191
192#define MEMC_BASE 0x00000000
193#define MEMC_SIZE 0x00C00000 // 12 Mbytes
194
195#define XICU_BASE 0x00F00000
196#define XICU_SIZE 0x00001000 // 4 Kbytes
197
198#define CDMA_BASE 0x00F30000
199#define CDMA_SIZE 0x00001000 * NB_DMAS_MAX // 4 Kbytes per channel
200
201////////////////////////////////////////////////////////////////////
202// TGTID definition in direct space
203// For all components: global TGTID = global SRCID = cluster_index
204////////////////////////////////////////////////////////////////////
205
206#define MEMC_TGTID 0
207#define XICU_TGTID 1
208#define CDMA_TGTID 2
209#define MTTY_TGTID 3
210#define FBUF_TGTID 4
211#define BROM_TGTID 5
212#define BDEV_TGTID 6
213#define MNIC_TGTID 7
214
215/////////////////////////////////
216int _main(int argc, char *argv[])
217{
218 using namespace sc_core;
219 using namespace soclib::caba;
220 using namespace soclib::common;
221
222
223 char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code
224 size_t ncycles = 1000000000; // simulated cycles
225 char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image
226 char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file
227 char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file
228 ssize_t threads_nr = 1; // simulator's threads number
229 bool debug_ok = false; // trace activated
230 size_t debug_period = 1; // trace period
231 size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced (cluster_id)
232 size_t debug_proc_id = TRACE_PROC_ID; // index of proc to be traced
233 uint32_t debug_from = 0; // trace start cycle
234 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor
235
236 ////////////// command line arguments //////////////////////
237 if (argc > 1)
238 {
239 for (int n = 1; n < argc; n = n + 2)
240 {
241 if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc))
242 {
243 ncycles = atoi(argv[n+1]);
244 }
245 else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
246 {
247 strcpy(soft_name, argv[n+1]);
248 }
249 else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
250 {
251 strcpy(disk_name, argv[n+1]);
252 }
253 else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
254 {
255 debug_ok = true;
256 debug_from = atoi(argv[n+1]);
257 }
258 else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) )
259 {
260 debug_memc_id = atoi(argv[n+1]);
261 assert( (debug_memc_id < (CLUSTER_X*CLUSTER_Y) ) &&
262 "debug_memc_id larger than XMAX * YMAX" );
263 }
264 else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) )
265 {
266 debug_proc_id = atoi(argv[n+1]);
267 assert( (debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) &&
268 "debug_proc_id larger than XMAX * YMAX * NB_PROCS" );
269 }
270 else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc))
271 {
272 threads_nr = atoi(argv[n+1]);
273 threads_nr = (threads_nr < 1) ? 1 : threads_nr;
274 }
275 else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc))
276 {
277 frozen_cycles = atoi(argv[n+1]);
278 }
279 else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc))
280 {
281 debug_period = atoi(argv[n+1]);
282 }
283 else
284 {
285 std::cout << " Arguments are (key,value) couples." << std::endl;
286 std::cout << " The order is not important." << std::endl;
287 std::cout << " Accepted arguments are :" << std::endl << std::endl;
288 std::cout << " -SOFT pathname_for_embedded_soft" << std::endl;
289 std::cout << " -DISK pathname_for_disk_image" << std::endl;
290 std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
291 std::cout << " -DEBUG debug_start_cycle" << std::endl;
292 std::cout << " -THREADS simulator's threads number" << std::endl;
293 std::cout << " -FROZEN max_number_of_lines" << std::endl;
294 std::cout << " -PERIOD number_of_cycles between trace" << std::endl;
295 std::cout << " -MEMCID index_memc_to_be_traced" << std::endl;
296 std::cout << " -PROCID index_proc_to_be_traced" << std::endl;
297 exit(0);
298 }
299 }
300 }
301
302 // checking hardware parameters
303 assert( ( (CLUSTER_X == 1) or (CLUSTER_X == 2) or (CLUSTER_X == 4) or
304 (CLUSTER_X == 8) or (CLUSTER_X == 16) ) and
305 "The CLUSTER_X parameter must be 1, 2, 4, 8 or 16" );
306
307 assert( ( (CLUSTER_Y == 1) or (CLUSTER_Y == 2) or (CLUSTER_Y == 4) or
308 (CLUSTER_Y == 8) or (CLUSTER_Y == 16) ) and
309 "The CLUSTER_Y parameter must be 1, 2, 4, 8 or 16" );
310
311 assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or
312 (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and
313 "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" );
314
315 assert( (NB_DMAS_MAX < 9) and
316 "The NB_DMAS_MAX parameter must be smaller than 9" );
317
318 assert( (NB_TTYS < 15) and
319 "The NB_TTYS parameter must be smaller than 15" );
320
321 assert( (NB_NICS < 9) and
322 "The NB_NICS parameter must be smaller than 9" );
323
324 std::cout << std::endl;
325 std::cout << " - CLUSTER_X = " << CLUSTER_X << std::endl;
326 std::cout << " - CLUSTER_Y = " << CLUSTER_Y << std::endl;
327 std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl;
328 std::cout << " - NB_DMAS_MAX = " << NB_DMAS_MAX << std::endl;
329 std::cout << " - NB_TTYS = " << NB_TTYS << std::endl;
330 std::cout << " - NB_NICS = " << NB_NICS << std::endl;
331 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;
332 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;
333 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;
334 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;
335
336 std::cout << std::endl;
337
338#if USE_OPENMP
339 omp_set_dynamic(false);
340 omp_set_num_threads(threads_nr);
341 std::cerr << "Built with openmp version " << _OPENMP << std::endl;
342#endif
343
344 // Define parameters depending on mesh size
345 size_t cluster_io_id;
346 size_t x_width;
347 size_t y_width;
348
349 if (CLUSTER_X == 1) x_width = 0;
350 else if (CLUSTER_X == 2) x_width = 1;
351 else if (CLUSTER_X <= 4) x_width = 2;
352 else if (CLUSTER_X <= 8) x_width = 3;
353 else x_width = 4;
354
355 if (CLUSTER_Y == 1) y_width = 0;
356 else if (CLUSTER_Y == 2) y_width = 1;
357 else if (CLUSTER_Y <= 4) y_width = 2;
358 else if (CLUSTER_Y <= 8) y_width = 3;
359 else y_width = 4;
360
361 cluster_io_id = 0xBF >> (8 - x_width - y_width);
362
363 /////////////////////
364 // Mapping Tables
365 /////////////////////
366
367 // direct network
368 MappingTable maptabd(address_width,
369 IntTab(x_width + y_width, 16 - x_width - y_width),
370 IntTab(x_width + y_width, srcid_width - x_width - y_width),
371 0x00FF0000);
372
373 for (size_t x = 0; x < CLUSTER_X; x++)
374 {
375 for (size_t y = 0; y < CLUSTER_Y; y++)
376 {
377 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width);
378
379 std::ostringstream sh;
380 sh << "d_seg_memc_" << x << "_" << y;
381 maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
382
383 std::ostringstream si;
384 si << "d_seg_xicu_" << x << "_" << y;
385 maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false));
386
387 std::ostringstream sd;
388 sd << "d_seg_mdma_" << x << "_" << y;
389 maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false));
390
391 if ( cluster(x,y) == cluster_io_id )
392 {
393 maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false));
394 maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false));
395 maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false));
396 maptabd.add(Segment("d_seg_mnic", MNIC_BASE, MNIC_SIZE, IntTab(cluster(x,y),MNIC_TGTID), false));
397 maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true));
398 }
399 }
400 }
401 std::cout << maptabd << std::endl;
402
403 // external network
404 MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000);
405
406 for (size_t x = 0; x < CLUSTER_X; x++)
407 {
408 for (size_t y = 0; y < CLUSTER_Y ; y++)
409 {
410 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width);
411 std::ostringstream sh;
412 sh << "x_seg_memc_" << x << "_" << y;
413 maptabx.add(Segment(sh.str(), MEMC_BASE+offset,
414 MEMC_SIZE, IntTab(cluster(x,y)), false));
415 }
416 }
417 std::cout << maptabx << std::endl;
418
419 ////////////////////
420 // Signals
421 ///////////////////
422
423 sc_clock signal_clk("clk");
424 sc_signal<bool> signal_resetn("resetn");
425
426 // Horizontal inter-clusters DSPIN signals
427 DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc =
428 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2);
429 DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec =
430 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2);
431 DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc =
432 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2);
433 DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec =
434 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2);
435
436 // Vertical inter-clusters DSPIN signals
437 DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc =
438 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2);
439 DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec =
440 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2);
441 DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc =
442 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2);
443 DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec =
444 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2);
445
446 // Mesh boundaries DSPIN signals
447 DspinSignals<cmd_width>**** signal_dspin_false_cmd_in =
448 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4);
449 DspinSignals<cmd_width>**** signal_dspin_false_cmd_out =
450 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4);
451 DspinSignals<rsp_width>**** signal_dspin_false_rsp_in =
452 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4);
453 DspinSignals<rsp_width>**** signal_dspin_false_rsp_out =
454 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4);
455
456
457 ////////////////////////////
458 // Loader
459 ////////////////////////////
460
461#if USE_ALMOS
462 soclib::common::Loader loader(almos_bootloader_pathname,
463 almos_archinfo_pathname,
464 almos_kernel_pathname);
465#else
466 soclib::common::Loader loader(soft_name);
467#endif
468
469 typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
470 proc_iss::set_loader(loader);
471
472 ////////////////////////////
473 // Clusters construction
474 ////////////////////////////
475
476 TsarXbarCluster<
477 proc_iss, cmd_width, rsp_width
478 > * clusters[CLUSTER_X][CLUSTER_Y];
479
480#if USE_OPENMP
481#pragma omp parallel
482 {
483#pragma omp for
484#endif
485 for(size_t i = 0; i < (CLUSTER_X * CLUSTER_Y); i++)
486 {
487 size_t x = i / CLUSTER_Y;
488 size_t y = i % CLUSTER_Y;
489
490#if USE_OPENMP
491#pragma omp critical
492 {
493#endif
494 bool is_io_cluster = (cluster(x,y) == cluster_io_id);
495
496 std::ostringstream sc;
497 sc << "cluster_" << x << "_" << y;
498 clusters[x][y] = new TsarXbarCluster<
499 proc_iss, cmd_width, rsp_width
500 >
501 (
502 sc.str().c_str(),
503 NB_PROCS_MAX , NB_TTYS , NB_DMAS_MAX , // cluster params
504 x , y , cluster(x,y), // mesh coordinates
505 maptabd , maptabx , // mapping tables
506 x_width , y_width , srcid_width - x_width - y_width, // srcid width,
507 MEMC_TGTID , XICU_TGTID , CDMA_TGTID , //
508 FBUF_TGTID , MTTY_TGTID , BROM_TGTID , // targets ids
509 MNIC_TGTID , BDEV_TGTID, //
510 MEMC_WAYS , MEMC_SETS , // MC params
511 L1_IWAYS , L1_ISETS , L1_DWAYS , L1_DSETS, // L1 params
512 XRAM_LATENCY , //
513 is_io_cluster, // is IO cluster ?
514 FBUF_X_SIZE , FBUF_Y_SIZE , // FB params
515 disk_name , BDEV_SECTOR_SIZE, // IOC params
516 NB_NICS , nic_rx_name , nic_tx_name , NIC_TIMEOUT, // NIC params
517 loader ,
518 frozen_cycles,
519 debug_from ,
520 debug_ok and (cluster(x,y) == debug_memc_id),
521 debug_ok and (cluster(x,y) == debug_proc_id)
522 );
523
524 std::cout << std::endl;
525 std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl;
526 std::cout << std::endl;
527
528#if USE_OPENMP
529 } // end critical
530#endif
531 } // end for
532#if USE_OPENMP
533 }
534#endif
535
536 ///////////////////////////////////////////////////////////////
537 // Net-list
538 ///////////////////////////////////////////////////////////////
539
540 // Clock & RESET
541 for (size_t x = 0; x < (CLUSTER_X); x++){
542 for (size_t y = 0; y < CLUSTER_Y; y++){
543 clusters[x][y]->p_clk (signal_clk);
544 clusters[x][y]->p_resetn (signal_resetn);
545 }
546 }
547
548 // Inter Clusters horizontal connections
549 if (CLUSTER_X > 1){
550 for (size_t x = 0; x < (CLUSTER_X-1); x++){
551 for (size_t y = 0; y < CLUSTER_Y; y++){
552 for (size_t k = 0; k < 2; k++){
553 clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]);
554 clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]);
555 clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]);
556 clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]);
557 clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]);
558 clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]);
559 clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]);
560 clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]);
561 }
562 }
563 }
564 }
565 std::cout << std::endl << "Horizontal connections established" << std::endl;
566
567 // Inter Clusters vertical connections
568 if (CLUSTER_Y > 1) {
569 for (size_t y = 0; y < (CLUSTER_Y-1); y++){
570 for (size_t x = 0; x < CLUSTER_X; x++){
571 for (size_t k = 0; k < 2; k++){
572 clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]);
573 clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]);
574 clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]);
575 clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]);
576 clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]);
577 clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]);
578 clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]);
579 clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]);
580 }
581 }
582 }
583 }
584 std::cout << "Vertical connections established" << std::endl;
585
586 // East & West boundary cluster connections
587 for (size_t y = 0; y < CLUSTER_Y; y++)
588 {
589 for (size_t k = 0; k < 2; k++)
590 {
591 clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]);
592 clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]);
593 clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]);
594 clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]);
595
596 clusters[CLUSTER_X-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[CLUSTER_X-1][y][k][EAST]);
597 clusters[CLUSTER_X-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[CLUSTER_X-1][y][k][EAST]);
598 clusters[CLUSTER_X-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[CLUSTER_X-1][y][k][EAST]);
599 clusters[CLUSTER_X-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[CLUSTER_X-1][y][k][EAST]);
600 }
601 }
602
603 // North & South boundary clusters connections
604 for (size_t x = 0; x < CLUSTER_X; x++)
605 {
606 for (size_t k = 0; k < 2; k++)
607 {
608 clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]);
609 clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]);
610 clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]);
611 clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]);
612
613 clusters[x][CLUSTER_Y-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][CLUSTER_Y-1][k][NORTH]);
614 clusters[x][CLUSTER_Y-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][CLUSTER_Y-1][k][NORTH]);
615 clusters[x][CLUSTER_Y-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][CLUSTER_Y-1][k][NORTH]);
616 clusters[x][CLUSTER_Y-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][CLUSTER_Y-1][k][NORTH]);
617 }
618 }
619
620
621 ////////////////////////////////////////////////////////
622 // Simulation
623 ///////////////////////////////////////////////////////
624
625 sc_start(sc_core::sc_time(0, SC_NS));
626 signal_resetn = false;
627
628 // network boundaries signals
629 for (size_t x = 0; x < CLUSTER_X ; x++){
630 for (size_t y = 0; y < CLUSTER_Y ; y++){
631 for (size_t k = 0; k < 2; k++){
632 for (size_t a = 0; a < 4; a++){
633 signal_dspin_false_cmd_in [x][y][k][a].write = false;
634 signal_dspin_false_cmd_in [x][y][k][a].read = true;
635 signal_dspin_false_cmd_out[x][y][k][a].write = false;
636 signal_dspin_false_cmd_out[x][y][k][a].read = true;
637
638 signal_dspin_false_rsp_in [x][y][k][a].write = false;
639 signal_dspin_false_rsp_in [x][y][k][a].read = true;
640 signal_dspin_false_rsp_out[x][y][k][a].write = false;
641 signal_dspin_false_rsp_out[x][y][k][a].read = true;
642 }
643 }
644 }
645 }
646
647 sc_start(sc_core::sc_time(1, SC_NS));
648 signal_resetn = true;
649
650 for (size_t n = 1; n < ncycles; n++)
651 {
652 if (debug_ok and (n > debug_from) and (n % debug_period == 0))
653 {
654 std::cout << "****************** cycle " << std::dec << n ;
655 std::cout << " ************************************************" << std::endl;
656/*
657 clusters[0][0]->proc[0]->print_trace();
658 clusters[0][0]->signal_vci_ini_proc[0].print_trace("DIRECT proc_0_0_0 vci_ini");
659 clusters[0][0]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_0_0_0");
660 clusters[0][0]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_0_0_0");
661 clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_0_0_0");
662 clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_0_0_0");
663 clusters[0][0]->memc->print_trace();
664 clusters[0][0]->signal_vci_tgt_memc.print_trace("DIRECT memc_0_0_vci_tgt");
665 clusters[0][0]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_0_0");
666 clusters[0][0]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_0_0");
667 clusters[0][0]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_0_0");
668 clusters[0][0]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_0_0");
669 clusters[0][0]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_0_0");
670 clusters[0][0]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_0_0");
671 clusters[0][0]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_0_0");
672
673 clusters[0][1]->proc[0]->print_trace();
674 clusters[0][1]->signal_vci_ini_proc[0].print_trace("DIRECT proc_0_1_0 vci_ini");
675 clusters[0][1]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_0_1_0");
676 clusters[0][1]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_0_1_0");
677 clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_0_1_0");
678 clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_0_1_0");
679 clusters[0][1]->memc->print_trace();
680 clusters[0][1]->signal_vci_tgt_memc.print_trace("DIRECT memc_0_1_vci_tgt");
681 clusters[0][1]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_0_1");
682 clusters[0][1]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_0_1");
683 clusters[0][1]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_0_1");
684 clusters[0][1]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_0_1");
685 clusters[0][1]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_0_1");
686 clusters[0][1]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_0_1");
687 clusters[0][1]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_0_1");
688
689 clusters[1][0]->proc[0]->print_trace();
690 clusters[1][0]->signal_vci_ini_proc[0].print_trace("DIRECT proc_1_0_0 vci_ini");
691 clusters[1][0]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_1_0_0");
692 clusters[1][0]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_1_0_0");
693 clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_1_0_0");
694 clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_1_0_0");
695 clusters[1][0]->memc->print_trace();
696 clusters[1][0]->signal_vci_tgt_memc.print_trace("DIRECT memc_1_0_vci_tgt");
697 clusters[1][0]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_1_0");
698 clusters[1][0]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_1_0");
699 clusters[1][0]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_1_0");
700 clusters[1][0]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_1_0");
701 clusters[1][0]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_1_0");
702 clusters[1][0]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_1_0");
703 clusters[1][0]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_1_0");
704
705 clusters[1][1]->proc[0]->print_trace();
706 clusters[1][1]->signal_vci_ini_proc[0].print_trace("DIRECT proc_1_1_0 vci_ini");
707 clusters[1][1]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_1_1_0");
708 clusters[1][1]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_1_1_0");
709 clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_1_1_0");
710 clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_1_1_0");
711 clusters[1][1]->memc->print_trace();
712 clusters[1][1]->signal_vci_tgt_memc.print_trace("DIRECT memc_1_1_vci_tgt");
713 clusters[1][1]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_1_1");
714 clusters[1][1]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_1_1");
715 clusters[1][1]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_1_1");
716 clusters[1][1]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_1_1");
717 clusters[1][1]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_1_1");
718 clusters[1][1]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_1_1");
719 clusters[1][1]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_1_1");
720*/
721 // trace proc[debug_proc_id]
722 if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) )
723 {
724 size_t l = debug_proc_id % (CLUSTER_X * CLUSTER_Y) ;
725 size_t y = (debug_proc_id / NB_PROCS_MAX) % CLUSTER_Y ;
726 size_t x = debug_proc_id / (CLUSTER_Y * NB_PROCS_MAX) ;
727
728 std::ostringstream signame;
729 signame << "VCI signal PROC_" << x << "_" << y << "_" << l;
730
731 clusters[x][y]->proc[l]->print_trace();
732 clusters[x][y]->signal_vci_ini_proc[l].print_trace("signame");
733 }
734/*
735 // trace memc[debug_memc_id]
736 if ( debug_memc_id < (CLUSTER_X * CLUSTER_Y) )
737 {
738 size_t x = debug_memc_id / CLUSTER_Y;
739 size_t y = debug_memc_id % CLUSTER_Y;
740
741 std::ostringstream signame;
742 signame << "VCI signal MEMC_" << x << "_" << y;
743
744 clusters[memc_x][memc_y]->memc->print_trace();
745 clusters[memc_x][memc_y]->signal_vci_tgt_memc.print_trace("signame");
746 }
747*/
748 // trace external peripherals
749 size_t io_x = cluster_io_id / CLUSTER_Y;
750 size_t io_y = cluster_io_id % CLUSTER_Y;
751
752 clusters[io_x][io_y]->signal_vci_tgt_mtty.print_trace("VCI signal TTY");
753/*
754 clusters[io_x][io_y]->bdev->print_trace();
755 clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("VCI signal BDEV_TGT");
756 clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("VCI signal BDEV_INI");
757*/
758 }
759
760 sc_start(sc_core::sc_time(1, SC_NS));
761 }
762 return EXIT_SUCCESS;
763}
764
765int sc_main (int argc, char *argv[])
766{
767 try {
768 return _main(argc, argv);
769 } catch (std::exception &e) {
770 std::cout << e.what() << std::endl;
771 } catch (...) {
772 std::cout << "Unknown exception occured" << std::endl;
773 throw;
774 }
775 return 1;
776}
777
778
779// Local Variables:
780// tab-width: 3
781// c-basic-offset: 3
782// c-file-offsets:((innamespace . 0)(inline-open . 0))
783// indent-tabs-mode: nil
784// End:
785
786// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
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