1 | ////////////////////////////////////////////////////////////////////////////// |
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2 | // File: tsar_xbar_cluster.cpp |
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3 | // Author: Alain Greiner |
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4 | // Copyright: UPMC/LIP6 |
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5 | // Date : march 2011 |
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6 | // This program is released under the GNU public license |
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7 | ////////////////////////////////////////////////////////////////////////////// |
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8 | // This file define a TSAR cluster architecture with virtual memory: |
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9 | // - It uses two virtual_dspin_router as distributed global interconnect |
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10 | // - It uses four dspin_local_crossbar as local interconnect |
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11 | // - It uses the vci_cc_vcache_wrapper |
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12 | // - It uses the vci_mem_cache |
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13 | // - It contains a private RAM with a variable latency to emulate the L3 cache |
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14 | // - It can contains 1, 2 or 4 processors |
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15 | // - Each processor has a private dma channel (vci_multi_dma) |
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16 | // - It uses the vci_xicu interrupt controller |
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17 | // - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0) |
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18 | // - The Multi-TTY component controls up to 15 terminals. |
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19 | // - Each Multi-DMA component controls up to 8 DMA channels. |
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20 | // - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15] |
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21 | // - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30] |
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22 | // - The BDEV IRQ is connected to IRQ_IN[31] |
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23 | ////////////////////////////////////////////////////////////////////////////////// |
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24 | |
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25 | #include "../include/tsar_xbar_cluster.h" |
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26 | |
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27 | |
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28 | namespace soclib { |
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29 | namespace caba { |
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30 | |
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31 | //////////////////////////////////////////////////////////////////////////////////// |
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32 | template<size_t dspin_cmd_width, |
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33 | size_t dspin_rsp_width, |
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34 | typename vci_param_int, |
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35 | typename vci_param_ext> TsarXbarCluster<dspin_cmd_width, |
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36 | dspin_rsp_width, |
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37 | vci_param_int, |
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38 | vci_param_ext>::TsarXbarCluster( |
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39 | //////////////////////////////////////////////////////////////////////////////////// |
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40 | sc_module_name insname, |
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41 | size_t nb_procs, |
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42 | size_t nb_ttys, |
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43 | size_t nb_dmas, |
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44 | size_t x_id, |
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45 | size_t y_id, |
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46 | size_t cluster_id, |
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47 | const soclib::common::MappingTable &mtd, |
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48 | const soclib::common::MappingTable &mtx, |
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49 | size_t x_width, |
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50 | size_t y_width, |
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51 | size_t l_width, |
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52 | size_t p_width, |
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53 | size_t tgtid_memc, |
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54 | size_t tgtid_xicu, |
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55 | size_t tgtid_mdma, |
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56 | size_t tgtid_fbuf, |
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57 | size_t tgtid_mtty, |
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58 | size_t tgtid_brom, |
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59 | size_t tgtid_mnic, |
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60 | size_t tgtid_chbuf, |
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61 | size_t tgtid_bdev, |
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62 | size_t tgtid_simh, |
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63 | size_t memc_ways, |
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64 | size_t memc_sets, |
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65 | size_t l1_i_ways, |
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66 | size_t l1_i_sets, |
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67 | size_t l1_d_ways, |
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68 | size_t l1_d_sets, |
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69 | size_t irq_per_processor, |
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70 | size_t xram_latency, |
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71 | bool io, |
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72 | size_t xfb, |
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73 | size_t yfb, |
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74 | char* disk_name, |
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75 | size_t block_size, |
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76 | size_t nic_channels, |
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77 | char* nic_rx_name, |
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78 | char* nic_tx_name, |
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79 | uint32_t nic_timeout, |
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80 | size_t chbufdma_channels, |
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81 | const Loader & loader, |
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82 | uint32_t frozen_cycles, |
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83 | uint32_t debug_start_cycle, |
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84 | bool memc_debug_ok, |
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85 | bool proc_debug_ok) |
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86 | : soclib::caba::BaseModule(insname), |
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87 | p_clk("clk"), |
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88 | p_resetn("resetn") { |
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89 | |
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90 | n_procs = nb_procs; |
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91 | |
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92 | ///////////////////////////////////////////////////////////////////////////// |
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93 | // Vectors of ports definition and allocation |
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94 | ///////////////////////////////////////////////////////////////////////////// |
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95 | |
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96 | p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cmd_in", 4); |
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97 | p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cmd_out", 4); |
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98 | |
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99 | p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_rsp_in", 4); |
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100 | p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_rsp_out", 4); |
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101 | |
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102 | p_m2p_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_m2p_in", 4); |
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103 | p_m2p_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_m2p_out", 4); |
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104 | |
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105 | p_p2m_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_p2m_in", 4); |
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106 | p_p2m_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_p2m_out", 4); |
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107 | |
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108 | p_cla_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cla_in", 4); |
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109 | p_cla_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cla_out", 4); |
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110 | |
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111 | ///////////////////////////////////////////////////////////////////////////// |
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112 | // Components definition |
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113 | ///////////////////////////////////////////////////////////////////////////// |
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114 | |
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115 | for (size_t p = 0; p < nb_procs; p++) { |
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116 | std::ostringstream sproc; |
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117 | sproc << "proc_" << x_id << "_" << y_id << "_" << p; |
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118 | proc[p] = new VciCcVCacheWrapper<vci_param_int, |
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119 | dspin_cmd_width, |
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120 | dspin_rsp_width, |
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121 | GdbServer<Mips32ElIss> >( |
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122 | sproc.str().c_str(), |
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123 | (cluster_id << p_width) + p, // GLOBAL PROC_ID |
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124 | mtd, // Mapping Table |
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125 | IntTab(cluster_id, p), // SRCID |
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126 | (cluster_id << l_width) + p, // CC_GLOBAL_ID |
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127 | 8, // ITLB ways |
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128 | 8, // ITLB sets |
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129 | 8, // DTLB ways |
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130 | 8, // DTLB sets |
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131 | l1_i_ways,l1_i_sets, 16, // ICACHE size |
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132 | l1_d_ways,l1_d_sets, 16, // DCACHE size |
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133 | 4, // WBUF nlines |
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134 | 4, // WBUF nwords |
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135 | x_width, |
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136 | y_width, |
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137 | frozen_cycles, // max frozen cycles |
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138 | debug_start_cycle, |
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139 | proc_debug_ok); |
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140 | |
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141 | } |
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142 | |
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143 | ///////////////////////////////////////////////////////////////////////////// |
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144 | std::ostringstream smemc; |
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145 | smemc << "memc_" << x_id << "_" << y_id; |
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146 | memc = new VciMemCache<vci_param_int, |
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147 | vci_param_ext, |
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148 | dspin_rsp_width, |
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149 | dspin_cmd_width>( |
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150 | smemc.str().c_str(), |
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151 | mtd, // Mapping Table direct space |
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152 | mtx, // Mapping Table external space |
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153 | IntTab(cluster_id), // SRCID external space |
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154 | IntTab(cluster_id, tgtid_memc), // TGTID direct space |
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155 | x_width, // Number of x bits in platform |
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156 | y_width, // Number of y bits in platform |
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157 | memc_ways, memc_sets, 16, // CACHE SIZE |
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158 | 4, // MAX NUMBER OF COPIES |
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159 | 4096, // HEAP SIZE |
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160 | 8, // TRANSACTION TABLE DEPTH |
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161 | 8, // UPDATE TABLE DEPTH |
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162 | 8, // INVALIDATE TABLE DEPTH |
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163 | debug_start_cycle, |
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164 | memc_debug_ok); |
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165 | |
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166 | |
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167 | ///////////////////////////////////////////////////////////////////////////// |
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168 | std::ostringstream sxram; |
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169 | sxram << "xram_" << x_id << "_" << y_id; |
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170 | xram = new VciSimpleRam<vci_param_ext>( |
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171 | sxram.str().c_str(), |
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172 | IntTab(cluster_id), |
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173 | mtx, |
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174 | loader, |
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175 | xram_latency); |
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176 | |
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177 | ///////////////////////////////////////////////////////////////////////////// |
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178 | std::ostringstream sxicu; |
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179 | sxicu << "xicu_" << x_id << "_" << y_id; |
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180 | xicu = new VciXicu<vci_param_int>( |
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181 | sxicu.str().c_str(), |
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182 | mtd, // mapping table |
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183 | IntTab(cluster_id, tgtid_xicu), // TGTID_D |
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184 | nb_procs, // number of timer IRQs |
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185 | 32, // number of hard IRQs |
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186 | 32, // number of soft IRQs |
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187 | nb_procs * irq_per_processor); // number of output IRQs |
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188 | |
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189 | |
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190 | ///////////////////////////////////////////////////////////////////////////// |
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191 | std::ostringstream smdma; |
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192 | smdma << "mdma_" << x_id << "_" << y_id; |
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193 | mdma = new VciMultiDma<vci_param_int>( |
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194 | smdma.str().c_str(), |
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195 | mtd, |
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196 | IntTab(cluster_id, nb_procs), // SRCID |
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197 | IntTab(cluster_id, tgtid_mdma), // TGTID |
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198 | 64, // burst size |
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199 | nb_dmas); // number of IRQs |
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200 | |
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201 | |
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202 | ///////////////////////////////////////////////////////////////////////////// |
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203 | size_t nb_direct_initiators = nb_procs + 1; |
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204 | size_t nb_direct_targets = 3; |
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205 | if (io) { |
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206 | nb_direct_initiators = nb_procs + 3; |
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207 | nb_direct_targets = 10; |
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208 | } |
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209 | |
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210 | std::ostringstream sxbar; |
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211 | sxbar << "xbar_" << x_id << "_" << y_id; |
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212 | xbar_d = new VciLocalCrossbar<vci_param_int>( |
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213 | sxbar.str().c_str(), |
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214 | mtd, // mapping table |
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215 | //x_id, y_id, // cluster coordinates |
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216 | cluster_id, |
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217 | nb_direct_initiators, // number of local of sources |
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218 | nb_direct_targets, // number of local dests |
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219 | tgtid_memc); // Default target |
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220 | |
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221 | ////////////// vci_dspin wrappers |
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222 | std::ostringstream swtxbar; |
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223 | swtxbar << "wt_xbar_" << x_id << "_" << y_id; |
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224 | wt_xbar_d = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>( |
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225 | swtxbar.str().c_str(), |
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226 | x_width + y_width + l_width); |
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227 | |
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228 | std::ostringstream swixbar; |
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229 | swixbar << "wi_xbar_" << x_id << "_" << y_id; |
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230 | wi_xbar_d = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>( |
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231 | swixbar.str().c_str(), |
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232 | x_width + y_width + l_width ); |
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233 | |
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234 | ///////////////////////////////////////////////////////////////////////////// |
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235 | xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>( |
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236 | "xbar_m2p_c", |
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237 | mtd, // mapping table |
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238 | x_id, y_id, // cluster coordinates |
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239 | x_width, y_width, l_width, |
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240 | 1, // number of local sources |
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241 | nb_procs, // number of local targets |
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242 | 2, 2, // fifo depths |
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243 | true, // CMD |
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244 | false, // don't use local routing table |
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245 | true ); // broadcast |
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246 | |
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247 | ///////////////////////////////////////////////////////////////////////////// |
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248 | xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>( |
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249 | "xbar_p2m_c", |
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250 | mtd, // mapping table |
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251 | x_id, y_id, // cluster coordinates |
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252 | x_width, y_width, 0, // l_width unused on p2m network |
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253 | nb_procs, // number of local sources |
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254 | 1, // number of local dests |
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255 | 2, 2, // fifo depths |
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256 | false, // RSP |
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257 | false, // don't use local routing table |
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258 | false ); // no broadcast |
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259 | |
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260 | ///////////////////////////////////////////////////////////////////////////// |
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261 | xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>( |
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262 | "xbar_clack_c", |
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263 | mtd, // mapping table |
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264 | x_id, y_id, // cluster coordinates |
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265 | x_width, y_width, l_width, |
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266 | 1, // number of local sources |
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267 | nb_procs, // number of local targets |
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268 | 1, 1, // fifo depths |
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269 | true, // CMD |
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270 | false, // don't use local routing table |
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271 | false); // broadcast |
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272 | |
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273 | ///////////////////////////////////////////////////////////////////////////// |
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274 | std::ostringstream s_router_cmd; |
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275 | s_router_cmd << "router_cmd_" << x_id << "_" << y_id; |
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276 | router_cmd = new DspinRouter<dspin_cmd_width>( |
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277 | s_router_cmd.str().c_str(), |
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278 | x_id,y_id, // coordinate in the mesh |
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279 | x_width, y_width, // x & y fields width |
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280 | 4,4); // input & output fifo depths |
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281 | |
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282 | ///////////////////////////////////////////////////////////////////////////// |
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283 | std::ostringstream s_router_rsp; |
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284 | s_router_rsp << "router_rsp_" << x_id << "_" << y_id; |
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285 | router_rsp = new DspinRouter<dspin_rsp_width>( |
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286 | s_router_rsp.str().c_str(), |
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287 | x_id,y_id, // coordinates in mesh |
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288 | x_width, y_width, // x & y fields width |
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289 | 4,4); // input & output fifo depths |
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290 | |
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291 | ///////////////////////////////////////////////////////////////////////////// |
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292 | std::ostringstream s_router_m2p; |
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293 | s_router_m2p << "router_m2p_" << x_id << "_" << y_id; |
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294 | router_m2p = new DspinRouter<dspin_cmd_width>( |
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295 | s_router_m2p.str().c_str(), |
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296 | x_id,y_id, // coordinate in the mesh |
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297 | x_width, y_width, // x & y fields width |
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298 | 4,4, // input & output fifo depths |
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299 | true); // broadcast supported |
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300 | |
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301 | ///////////////////////////////////////////////////////////////////////////// |
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302 | std::ostringstream s_router_p2m; |
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303 | s_router_p2m << "router_p2m_" << x_id << "_" << y_id; |
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304 | router_p2m = new DspinRouter<dspin_rsp_width>( |
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305 | s_router_p2m.str().c_str(), |
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306 | x_id,y_id, // coordinates in mesh |
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307 | x_width, y_width, // x & y fields width |
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308 | 4,4); // input & output fifo depths |
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309 | |
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310 | ///////////////////////////////////////////////////////////////////////////// |
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311 | std::ostringstream s_router_cla; |
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312 | s_router_cla << "router_cla_" << x_id << "_" << y_id; |
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313 | router_cla = new DspinRouter<dspin_cmd_width>( |
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314 | s_router_cla.str().c_str(), |
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315 | x_id,y_id, // coordinate in the mesh |
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316 | x_width, y_width, // x & y fields width |
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317 | 4,4); // input & output fifo depths |
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318 | |
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319 | // IO cluster components |
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320 | if (io) { |
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321 | ///////////////////////////////////////////// |
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322 | brom = new VciSimpleRom<vci_param_int>( |
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323 | "brom", |
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324 | IntTab(cluster_id, tgtid_brom), |
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325 | mtd, |
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326 | loader); |
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327 | |
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328 | ///////////////////////////////////////////// |
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329 | fbuf = new VciFrameBuffer<vci_param_int>( |
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330 | "fbuf", |
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331 | IntTab(cluster_id, tgtid_fbuf), |
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332 | mtd, |
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333 | xfb, yfb); |
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334 | |
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335 | ///////////////////////////////////////////// |
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336 | bdev = new VciBlockDeviceTsar<vci_param_int>( |
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337 | "bdev", |
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338 | mtd, |
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339 | IntTab(cluster_id, nb_procs + 1), |
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340 | IntTab(cluster_id, tgtid_bdev), |
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341 | disk_name, |
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342 | block_size, |
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343 | 64); // burst size |
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344 | |
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345 | mnic = new VciMultiNic<vci_param_int>( |
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346 | "mnic", |
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347 | IntTab(cluster_id, tgtid_mnic), |
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348 | mtd, |
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349 | nic_channels, |
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350 | 0, // mac_4 address |
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351 | 0, // mac_2 address |
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352 | 1, // NIC_MODE_SYNTHESIS |
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353 | 12); // INTER_FRAME_GAP |
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354 | |
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355 | |
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356 | |
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357 | ///////////////////////////////////////////// |
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358 | chbuf = new VciChbufDma<vci_param_int>( |
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359 | "chbuf_dma", |
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360 | mtd, |
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361 | IntTab(cluster_id, nb_procs + 2), |
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362 | IntTab(cluster_id, tgtid_chbuf), |
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363 | 64, |
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364 | chbufdma_channels); |
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365 | |
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366 | ///////////////////////////////////////////// |
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367 | std::vector<std::string> vect_names; |
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368 | for (size_t tid = 0; tid < nb_ttys; tid++) { |
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369 | std::ostringstream term_name; |
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370 | term_name << "term" << tid; |
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371 | vect_names.push_back(term_name.str().c_str()); |
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372 | } |
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373 | mtty = new VciMultiTty<vci_param_int>( |
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374 | "mtty", |
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375 | IntTab(cluster_id, tgtid_mtty), |
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376 | mtd, |
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377 | vect_names); |
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378 | |
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379 | simhelper = new VciSimhelper<vci_param_int>( |
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380 | "sim_helper", |
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381 | IntTab(cluster_id, tgtid_simh), |
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382 | mtd); |
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383 | } |
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384 | |
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385 | //////////////////////////////////// |
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386 | // Connections are defined here |
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387 | //////////////////////////////////// |
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388 | |
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389 | //////////////////////// ROUTERS |
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390 | router_cmd->p_clk (this->p_clk); |
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391 | router_cmd->p_resetn (this->p_resetn); |
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392 | router_rsp->p_clk (this->p_clk); |
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393 | router_rsp->p_resetn (this->p_resetn); |
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394 | router_m2p->p_clk (this->p_clk); |
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395 | router_m2p->p_resetn (this->p_resetn); |
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396 | router_p2m->p_clk (this->p_clk); |
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397 | router_p2m->p_resetn (this->p_resetn); |
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398 | router_cla->p_clk (this->p_clk); |
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399 | router_cla->p_resetn (this->p_resetn); |
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400 | |
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401 | // loop on N/S/E/W ports |
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402 | for (size_t i = 0; i < 4; i++) { |
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403 | router_cmd->p_out[i] (this->p_cmd_out[i]); |
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404 | router_cmd->p_in[i] (this->p_cmd_in[i]); |
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405 | |
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406 | router_rsp->p_out[i] (this->p_rsp_out[i]); |
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407 | router_rsp->p_in[i] (this->p_rsp_in[i]); |
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408 | |
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409 | router_m2p->p_out[i] (this->p_m2p_out[i]); |
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410 | router_m2p->p_in[i] (this->p_m2p_in[i]); |
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411 | |
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412 | router_p2m->p_out[i] (this->p_p2m_out[i]); |
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413 | router_p2m->p_in[i] (this->p_p2m_in[i]); |
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414 | |
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415 | router_cla->p_out[i] (this->p_cla_out[i]); |
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416 | router_cla->p_in[i] (this->p_cla_in[i]); |
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417 | } |
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418 | |
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419 | router_cmd->p_out[4] (signal_dspin_cmd_g2l_d); |
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420 | router_cmd->p_in[4] (signal_dspin_cmd_l2g_d); |
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421 | |
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422 | router_rsp->p_out[4] (signal_dspin_rsp_g2l_d); |
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423 | router_rsp->p_in[4] (signal_dspin_rsp_l2g_d); |
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424 | |
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425 | router_m2p->p_out[4] (signal_dspin_m2p_g2l_c); |
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426 | router_m2p->p_in[4] (signal_dspin_m2p_l2g_c); |
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427 | |
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428 | router_p2m->p_out[4] (signal_dspin_p2m_g2l_c); |
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429 | router_p2m->p_in[4] (signal_dspin_p2m_l2g_c); |
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430 | |
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431 | router_cla->p_out[4] (signal_dspin_clack_g2l_c); |
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432 | router_cla->p_in[4] (signal_dspin_clack_l2g_c); |
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433 | |
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434 | std::cout << " - routers connected" << std::endl; |
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435 | |
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436 | wi_xbar_d->p_clk (this->p_clk); |
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437 | wi_xbar_d->p_resetn (this->p_resetn); |
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438 | wi_xbar_d->p_vci (signal_vci_l2g_d); |
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439 | wi_xbar_d->p_dspin_cmd (signal_dspin_cmd_l2g_d); |
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440 | wi_xbar_d->p_dspin_rsp (signal_dspin_rsp_g2l_d); |
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441 | |
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442 | std::cout << " - Wrapper Ini VCI2DSPIN Direct connected" << std::endl; |
---|
443 | |
---|
444 | wt_xbar_d->p_clk (this->p_clk); |
---|
445 | wt_xbar_d->p_resetn (this->p_resetn); |
---|
446 | wt_xbar_d->p_vci (signal_vci_g2l_d); |
---|
447 | wt_xbar_d->p_dspin_cmd (signal_dspin_cmd_g2l_d); |
---|
448 | wt_xbar_d->p_dspin_rsp (signal_dspin_rsp_l2g_d); |
---|
449 | |
---|
450 | std::cout << " - Wrapper Tgt VCI2DSPIN Direct connected" << std::endl; |
---|
451 | |
---|
452 | ///////////////////// CMD VCI local crossbar direct |
---|
453 | xbar_d->p_clk (this->p_clk); |
---|
454 | xbar_d->p_resetn (this->p_resetn); |
---|
455 | xbar_d->p_target_to_up (signal_vci_g2l_d); |
---|
456 | xbar_d->p_initiator_to_up (signal_vci_l2g_d); |
---|
457 | |
---|
458 | xbar_d->p_to_target[tgtid_memc] (signal_vci_tgt_memc); |
---|
459 | xbar_d->p_to_target[tgtid_xicu] (signal_vci_tgt_xicu); |
---|
460 | xbar_d->p_to_target[tgtid_mdma] (signal_vci_tgt_mdma); |
---|
461 | |
---|
462 | xbar_d->p_to_initiator[nb_procs] (signal_vci_ini_mdma); |
---|
463 | |
---|
464 | for (size_t p = 0; p < nb_procs; p++) { |
---|
465 | xbar_d->p_to_initiator[p] (signal_vci_ini_proc[p]); |
---|
466 | } |
---|
467 | |
---|
468 | if (io) { |
---|
469 | xbar_d->p_to_target[tgtid_mtty] (signal_vci_tgt_mtty); |
---|
470 | xbar_d->p_to_target[tgtid_brom] (signal_vci_tgt_brom); |
---|
471 | xbar_d->p_to_target[tgtid_bdev] (signal_vci_tgt_bdev); |
---|
472 | xbar_d->p_to_target[tgtid_fbuf] (signal_vci_tgt_fbuf); |
---|
473 | xbar_d->p_to_target[tgtid_mnic] (signal_vci_tgt_mnic); |
---|
474 | xbar_d->p_to_target[tgtid_chbuf] (signal_vci_tgt_chbuf); |
---|
475 | xbar_d->p_to_target[tgtid_simh] (signal_vci_tgt_simh); |
---|
476 | |
---|
477 | xbar_d->p_to_initiator[nb_procs + 1] (signal_vci_ini_bdev); |
---|
478 | xbar_d->p_to_initiator[nb_procs + 2] (signal_vci_ini_chbuf); |
---|
479 | } |
---|
480 | |
---|
481 | std::cout << " - Direct crossbar connected" << std::endl; |
---|
482 | |
---|
483 | ////////////////////// M2P DSPIN local crossbar coherence |
---|
484 | xbar_m2p_c->p_clk (this->p_clk); |
---|
485 | xbar_m2p_c->p_resetn (this->p_resetn); |
---|
486 | xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c); |
---|
487 | xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c); |
---|
488 | xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc); |
---|
489 | for (size_t p = 0; p < nb_procs; p++) { |
---|
490 | xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]); |
---|
491 | } |
---|
492 | |
---|
493 | std::cout << " - M2P Coherence crossbar connected" << std::endl; |
---|
494 | |
---|
495 | ////////////////////// CLACK DSPIN local crossbar coherence |
---|
496 | xbar_clack_c->p_clk (this->p_clk); |
---|
497 | xbar_clack_c->p_resetn (this->p_resetn); |
---|
498 | xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c); |
---|
499 | xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c); |
---|
500 | xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc); |
---|
501 | for (size_t p = 0; p < nb_procs; p++) { |
---|
502 | xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]); |
---|
503 | } |
---|
504 | |
---|
505 | std::cout << " - Clack Coherence crossbar connected" << std::endl; |
---|
506 | |
---|
507 | ////////////////////////// P2M DSPIN local crossbar coherence |
---|
508 | xbar_p2m_c->p_clk (this->p_clk); |
---|
509 | xbar_p2m_c->p_resetn (this->p_resetn); |
---|
510 | xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c); |
---|
511 | xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c); |
---|
512 | xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc); |
---|
513 | for (size_t p = 0; p < nb_procs; p++) { |
---|
514 | xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]); |
---|
515 | } |
---|
516 | |
---|
517 | std::cout << " - P2M Coherence crossbar connected" << std::endl; |
---|
518 | |
---|
519 | |
---|
520 | //////////////////////////////////// Processors |
---|
521 | for (size_t p = 0; p < nb_procs; p++) { |
---|
522 | proc[p]->p_clk (this->p_clk); |
---|
523 | proc[p]->p_resetn (this->p_resetn); |
---|
524 | proc[p]->p_vci (signal_vci_ini_proc[p]); |
---|
525 | proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]); |
---|
526 | proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]); |
---|
527 | proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]); |
---|
528 | |
---|
529 | for ( size_t i = 0; i < irq_per_processor; i++) { |
---|
530 | proc[p]->p_irq[i] (signal_proc_it[p*irq_per_processor + i]); |
---|
531 | } |
---|
532 | for ( size_t j = irq_per_processor; j < 6; j++) { |
---|
533 | // 6 = number of irqs in the MIPS |
---|
534 | proc[p]->p_irq[j] (signal_false); |
---|
535 | } |
---|
536 | |
---|
537 | } |
---|
538 | |
---|
539 | std::cout << " - Processors connected" << std::endl; |
---|
540 | |
---|
541 | ///////////////////////////////////// XICU |
---|
542 | xicu->p_clk (this->p_clk); |
---|
543 | xicu->p_resetn (this->p_resetn); |
---|
544 | xicu->p_vci (signal_vci_tgt_xicu); |
---|
545 | for (size_t p = 0; p < nb_procs * irq_per_processor; p++) { |
---|
546 | xicu->p_irq[p] (signal_proc_it[p]); |
---|
547 | } |
---|
548 | for (size_t i = 0; i < 32; i++) { |
---|
549 | if (io) { |
---|
550 | // I/O cluster |
---|
551 | if (i < 8) xicu->p_hwi[i] (signal_false); |
---|
552 | else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]); |
---|
553 | else if (i < 16) xicu->p_hwi[i] (signal_false); |
---|
554 | else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i - 16]); |
---|
555 | else if (i < 30) xicu->p_hwi[i] (signal_false); |
---|
556 | else if (i < 31) xicu->p_hwi[i] (signal_irq_memc); |
---|
557 | else xicu->p_hwi[i] (signal_irq_bdev); |
---|
558 | } |
---|
559 | else { |
---|
560 | // other clusters |
---|
561 | if (i < 8) xicu->p_hwi[i] (signal_false); |
---|
562 | else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]); |
---|
563 | else if (i < 30) xicu->p_hwi[i] (signal_false); |
---|
564 | else if (i < 31) xicu->p_hwi[i] (signal_irq_memc); |
---|
565 | else xicu->p_hwi[i] (signal_false); |
---|
566 | } |
---|
567 | } |
---|
568 | |
---|
569 | std::cout << " - XICU connected" << std::endl; |
---|
570 | |
---|
571 | //////////////////////////////////////////////// MEMC |
---|
572 | memc->p_clk (this->p_clk); |
---|
573 | memc->p_resetn (this->p_resetn); |
---|
574 | memc->p_irq (signal_irq_memc); |
---|
575 | memc->p_vci_ixr (signal_vci_xram); |
---|
576 | memc->p_vci_tgt (signal_vci_tgt_memc); |
---|
577 | memc->p_dspin_p2m (signal_dspin_p2m_memc); |
---|
578 | memc->p_dspin_m2p (signal_dspin_m2p_memc); |
---|
579 | memc->p_dspin_clack (signal_dspin_clack_memc); |
---|
580 | |
---|
581 | std::cout << " - MEMC connected" << std::endl; |
---|
582 | |
---|
583 | /////////////////////////////////////////////// XRAM |
---|
584 | xram->p_clk (this->p_clk); |
---|
585 | xram->p_resetn (this->p_resetn); |
---|
586 | xram->p_vci (signal_vci_xram); |
---|
587 | |
---|
588 | std::cout << " - XRAM connected" << std::endl; |
---|
589 | |
---|
590 | ////////////////////////////////////////////// MDMA |
---|
591 | mdma->p_clk (this->p_clk); |
---|
592 | mdma->p_resetn (this->p_resetn); |
---|
593 | mdma->p_vci_target (signal_vci_tgt_mdma); |
---|
594 | mdma->p_vci_initiator (signal_vci_ini_mdma); |
---|
595 | for (size_t i = 0; i < nb_dmas; i++) { |
---|
596 | mdma->p_irq[i] (signal_irq_mdma[i]); |
---|
597 | } |
---|
598 | |
---|
599 | std::cout << " - MDMA connected" << std::endl; |
---|
600 | |
---|
601 | /////////////////////////////// Components in I/O cluster |
---|
602 | |
---|
603 | if (io) { |
---|
604 | // BDEV |
---|
605 | bdev->p_clk (this->p_clk); |
---|
606 | bdev->p_resetn (this->p_resetn); |
---|
607 | bdev->p_irq (signal_irq_bdev); |
---|
608 | bdev->p_vci_target (signal_vci_tgt_bdev); |
---|
609 | bdev->p_vci_initiator (signal_vci_ini_bdev); |
---|
610 | |
---|
611 | std::cout << " - BDEV connected" << std::endl; |
---|
612 | |
---|
613 | // FBUF |
---|
614 | fbuf->p_clk (this->p_clk); |
---|
615 | fbuf->p_resetn (this->p_resetn); |
---|
616 | fbuf->p_vci (signal_vci_tgt_fbuf); |
---|
617 | |
---|
618 | std::cout << " - FBUF connected" << std::endl; |
---|
619 | |
---|
620 | // MNIC |
---|
621 | mnic->p_clk (this->p_clk); |
---|
622 | mnic->p_resetn (this->p_resetn); |
---|
623 | mnic->p_vci (signal_vci_tgt_mnic); |
---|
624 | for (size_t i = 0; i < nic_channels; i++) { |
---|
625 | mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); |
---|
626 | mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); |
---|
627 | } |
---|
628 | |
---|
629 | std::cout << " - MNIC connected" << std::endl; |
---|
630 | |
---|
631 | // CHBUF |
---|
632 | chbuf->p_clk (this->p_clk); |
---|
633 | chbuf->p_resetn (this->p_resetn); |
---|
634 | chbuf->p_vci_target (signal_vci_tgt_chbuf); |
---|
635 | chbuf->p_vci_initiator (signal_vci_ini_chbuf); |
---|
636 | for (size_t i = 0; i < chbufdma_channels; i++) { |
---|
637 | chbuf->p_irq[i] (signal_irq_chbuf[i]); |
---|
638 | } |
---|
639 | |
---|
640 | std::cout << " - CHBUF connected" << std::endl; |
---|
641 | |
---|
642 | // BROM |
---|
643 | brom->p_clk (this->p_clk); |
---|
644 | brom->p_resetn (this->p_resetn); |
---|
645 | brom->p_vci (signal_vci_tgt_brom); |
---|
646 | |
---|
647 | std::cout << " - BROM connected" << std::endl; |
---|
648 | |
---|
649 | // MTTY |
---|
650 | mtty->p_clk (this->p_clk); |
---|
651 | mtty->p_resetn (this->p_resetn); |
---|
652 | mtty->p_vci (signal_vci_tgt_mtty); |
---|
653 | for (size_t i = 0; i < nb_ttys; i++) { |
---|
654 | mtty->p_irq[i] (signal_irq_mtty[i]); |
---|
655 | } |
---|
656 | |
---|
657 | std::cout << " - MTTY connected" << std::endl; |
---|
658 | |
---|
659 | |
---|
660 | // Sim Helper |
---|
661 | simhelper->p_clk (this->p_clk); |
---|
662 | simhelper->p_resetn (this->p_resetn); |
---|
663 | simhelper->p_vci (signal_vci_tgt_simh); |
---|
664 | |
---|
665 | std::cout << " - SIMH connected" << std::endl; |
---|
666 | } |
---|
667 | } // end constructor |
---|
668 | |
---|
669 | |
---|
670 | |
---|
671 | template<size_t dspin_cmd_width, |
---|
672 | size_t dspin_rsp_width, |
---|
673 | typename vci_param_int, |
---|
674 | typename vci_param_ext> TsarXbarCluster<dspin_cmd_width, |
---|
675 | dspin_rsp_width, |
---|
676 | vci_param_int, |
---|
677 | vci_param_ext>::~TsarXbarCluster() { |
---|
678 | |
---|
679 | dealloc_elems<DspinInput<dspin_cmd_width> > (p_cmd_in, 4); |
---|
680 | dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cmd_out, 4); |
---|
681 | |
---|
682 | dealloc_elems<DspinInput<dspin_rsp_width> > (p_rsp_in, 4); |
---|
683 | dealloc_elems<DspinOutput<dspin_rsp_width> >(p_rsp_out, 4); |
---|
684 | |
---|
685 | dealloc_elems<DspinInput<dspin_cmd_width> > (p_m2p_in, 4); |
---|
686 | dealloc_elems<DspinOutput<dspin_cmd_width> >(p_m2p_out, 4); |
---|
687 | |
---|
688 | dealloc_elems<DspinInput<dspin_rsp_width> > (p_p2m_in, 4); |
---|
689 | dealloc_elems<DspinOutput<dspin_rsp_width> >(p_p2m_out, 4); |
---|
690 | |
---|
691 | dealloc_elems<DspinInput<dspin_cmd_width> > (p_cla_in, 4); |
---|
692 | dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cla_out, 4); |
---|
693 | |
---|
694 | for (size_t p = 0; p < n_procs; p++) { |
---|
695 | delete proc[p]; |
---|
696 | } |
---|
697 | |
---|
698 | delete memc; |
---|
699 | delete xram; |
---|
700 | delete xicu; |
---|
701 | delete mdma; |
---|
702 | delete xbar_d; |
---|
703 | delete wt_xbar_d; |
---|
704 | delete wi_xbar_d; |
---|
705 | delete xbar_m2p_c; |
---|
706 | delete xbar_p2m_c; |
---|
707 | delete xbar_clack_c; |
---|
708 | delete router_cmd; |
---|
709 | delete router_rsp; |
---|
710 | delete router_m2p; |
---|
711 | delete router_p2m; |
---|
712 | delete router_cla; |
---|
713 | if (brom != NULL) { |
---|
714 | delete brom; |
---|
715 | delete fbuf; |
---|
716 | delete bdev; |
---|
717 | delete mnic; |
---|
718 | delete chbuf; |
---|
719 | delete mtty; |
---|
720 | delete simhelper; |
---|
721 | } |
---|
722 | } |
---|
723 | |
---|
724 | |
---|
725 | template<size_t dspin_cmd_width, |
---|
726 | size_t dspin_rsp_width, |
---|
727 | typename vci_param_int, |
---|
728 | typename vci_param_ext> |
---|
729 | void TsarXbarCluster<dspin_cmd_width, |
---|
730 | dspin_rsp_width, |
---|
731 | vci_param_int, |
---|
732 | vci_param_ext>::trace(sc_core::sc_trace_file * tf, const std::string & name) { |
---|
733 | |
---|
734 | #define __trace(x) sc_core::sc_trace(tf, x, name + "_" + #x) |
---|
735 | __trace(signal_vci_l2g_d); |
---|
736 | __trace(signal_vci_g2l_d); |
---|
737 | __trace(signal_vci_tgt_memc); |
---|
738 | __trace(signal_vci_tgt_xicu); |
---|
739 | __trace(signal_vci_tgt_mdma); |
---|
740 | __trace(signal_vci_ini_mdma); |
---|
741 | |
---|
742 | for (size_t p = 0; p < n_procs; p++) { |
---|
743 | std::ostringstream signame; |
---|
744 | signame << "vci_ini_proc_" << p; |
---|
745 | sc_core::sc_trace(tf, signal_vci_ini_proc[p], signame.str()); |
---|
746 | } |
---|
747 | __trace(signal_vci_tgt_mtty); |
---|
748 | __trace(signal_vci_tgt_brom); |
---|
749 | __trace(signal_vci_tgt_bdev); |
---|
750 | __trace(signal_vci_tgt_fbuf); |
---|
751 | __trace(signal_vci_tgt_simh); |
---|
752 | __trace(signal_vci_ini_bdev); |
---|
753 | __trace(signal_vci_tgt_memc); |
---|
754 | __trace(signal_vci_xram); |
---|
755 | #undef trace |
---|
756 | |
---|
757 | } |
---|
758 | |
---|
759 | }} |
---|
760 | |
---|
761 | // Local Variables: |
---|
762 | // tab-width: 4 |
---|
763 | // c-basic-offset: 4 |
---|
764 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
765 | // indent-tabs-mode: nil |
---|
766 | // End: |
---|
767 | |
---|
768 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
769 | |
---|