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source: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp @ 485

Last change on this file since 485 was 485, checked in by lambert, 11 years ago

Fixing chbuf dma segment size
Changing the way number of chained buffer dma channels is defined top.cpp now uses the NB_CMA_CHANNELS present in hard_config.h
Adding a parameter to TsarXbarCluster? constructor: chbufdma_channels

--Cette ligne, et les suivantes ci-dessous, seront ignorées--

M top.cpp
M tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h
M tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp

File size: 36.0 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_xbar_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : march 2011
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// This file define a TSAR cluster architecture with virtual memory:
9	// - It uses two virtual_dspin_router as distributed global interconnect
10	// - It uses four dspin_local_crossbar as local interconnect
11	// - It uses the vci_cc_vcache_wrapper
12	// - It uses the vci_mem_cache
13	// - It contains a private RAM with a variable latency to emulate the L3 cache
14	// - It can contains 1, 2 or 4 processors
15	// - Each processor has a private dma channel (vci_multi_dma)
16	// - It uses the vci_xicu interrupt controller
17	// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0)
18	// - The Multi-TTY component controls up to 15 terminals.
19	// - Each Multi-DMA component controls up to 8 DMA channels.
20	// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
21	// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
22	// - The BDEV IRQ is connected to IRQ_IN[31]
23	//////////////////////////////////////////////////////////////////////////////////
24
25	#include "../include/tsar_xbar_cluster.h"
26
27
28	namespace soclib {
29	namespace caba {
30
31	////////////////////////////////////////////////////////////////////////////////////
32	template<size_t dspin_cmd_width,
33	size_t dspin_rsp_width,
34	typename vci_param_int,
35	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
36	dspin_rsp_width,
37	vci_param_int,
38	vci_param_ext>::TsarXbarCluster(
39	////////////////////////////////////////////////////////////////////////////////////
40	sc_module_name insname,
41	size_t nb_procs,
42	size_t nb_ttys,
43	size_t nb_dmas,
44	size_t x_id,
45	size_t y_id,
46	size_t cluster_id,
47	const soclib::common::MappingTable &mtd,
48	const soclib::common::MappingTable &mtx,
49	size_t x_width,
50	size_t y_width,
51	size_t l_width,
52	size_t tgtid_memc,
53	size_t tgtid_xicu,
54	size_t tgtid_mdma,
55	size_t tgtid_fbuf,
56	size_t tgtid_mtty,
57	size_t tgtid_brom,
58	size_t tgtid_mnic,
59	size_t tgtid_chbuf,
60	size_t tgtid_bdev,
61	size_t memc_ways,
62	size_t memc_sets,
63	size_t l1_i_ways,
64	size_t l1_i_sets,
65	size_t l1_d_ways,
66	size_t l1_d_sets,
67	size_t xram_latency,
68	bool io,
69	size_t xfb,
70	size_t yfb,
71	char* disk_name,
72	size_t block_size,
73	size_t nic_channels,
74	char* nic_rx_name,
75	char* nic_tx_name,
76	uint32_t nic_timeout,
77	size_t chbufdma_channels,
78	const Loader &loader,
79	uint32_t frozen_cycles,
80	uint32_t debug_start_cycle,
81	bool memc_debug_ok,
82	bool proc_debug_ok)
83	: soclib::caba::BaseModule(insname),
84	p_clk("clk"),
85	p_resetn("resetn")
86
87	{
88	// Vectors of ports definition
89	p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> >("p_cmd_in", 4, 3);
90	p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> >("p_cmd_out", 4, 3);
91	p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> >("p_rsp_in", 4, 2);
92	p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> >("p_rsp_out", 4, 2);
93
94	/////////////////////////////////////////////////////////////////////////////
95	// Components definition
96	/////////////////////////////////////////////////////////////////////////////
97
98	for (size_t p = 0; p < nb_procs; p++)
99	{
100	std::ostringstream sproc;
101	sproc << "proc_" << x_id << "_" << y_id << "_" << p;
102	proc[p] = new VciCcVCacheWrapper<vci_param_int,
103	dspin_cmd_width,
104	dspin_rsp_width,
105	GdbServer<Mips32ElIss> >(
106	sproc.str().c_str(),
107	cluster_id*nb_procs + p, // GLOBAL PROC_ID
108	mtd, // Mapping Table
109	IntTab(cluster_id,p), // SRCID
110	(cluster_id << l_width) + p, // CC_GLOBAL_ID
111	8, // ITLB ways
112	8, // ITLB sets
113	8, // DTLB ways
114	8, // DTLB sets
115	l1_i_ways,l1_i_sets,16, // ICACHE size
116	l1_d_ways,l1_d_sets,16, // DCACHE size
117	4, // WBUF nlines
118	4, // WBUF nwords
119	x_width,
120	y_width,
121	frozen_cycles, // max frozen cycles
122	debug_start_cycle,
123	proc_debug_ok);
124
125	std::ostringstream swip;
126	swip << "wi_proc_" << x_id << "_" << y_id << "_" << p;
127	wi_proc[p] = new VciDspinInitiatorWrapper<vci_param_int,
128	dspin_cmd_width,
129	dspin_rsp_width>(
130	swip.str().c_str(),
131	x_width + y_width + l_width);
132	}
133
134	/////////////////////////////////////////////////////////////////////////////
135	std::ostringstream smemc;
136	smemc << "memc_" << x_id << "_" << y_id;
137	memc = new VciMemCache<vci_param_int,
138	vci_param_ext,
139	dspin_rsp_width,
140	dspin_cmd_width>(
141	smemc.str().c_str(),
142	mtd, // Mapping Table direct space
143	mtx, // Mapping Table external space
144	IntTab(cluster_id), // SRCID external space
145	IntTab(cluster_id, tgtid_memc), // TGTID direct space
146	(cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID
147	memc_ways, memc_sets, 16, // CACHE SIZE
148	3, // MAX NUMBER OF COPIES
149	4096, // HEAP SIZE
150	8, // TRANSACTION TABLE DEPTH
151	8, // UPDATE TABLE DEPTH
152	8, // INVALIDATE TABLE DEPTH
153	debug_start_cycle,
154	memc_debug_ok );
155
156	wt_memc = new VciDspinTargetWrapper<vci_param_int,
157	dspin_cmd_width,
158	dspin_rsp_width>(
159	"wt_memc",
160	x_width + y_width + l_width);
161
162	/////////////////////////////////////////////////////////////////////////////
163	std::ostringstream sxram;
164	sxram << "xram_" << x_id << "_" << y_id;
165	xram = new VciSimpleRam<vci_param_ext>(
166	sxram.str().c_str(),
167	IntTab(cluster_id),
168	mtx,
169	loader,
170	xram_latency);
171
172	/////////////////////////////////////////////////////////////////////////////
173	std::ostringstream sxicu;
174	sxicu << "xicu_" << x_id << "_" << y_id;
175	xicu = new VciXicu<vci_param_int>(
176	sxicu.str().c_str(),
177	mtd, // mapping table
178	IntTab(cluster_id, tgtid_xicu), // TGTID_D
179	nb_procs, // number of timer IRQs
180	32, // number of hard IRQs
181	32, // number of soft IRQs
182	nb_procs); // number of output IRQs
183
184	wt_xicu = new VciDspinTargetWrapper<vci_param_int,
185	dspin_cmd_width,
186	dspin_rsp_width>(
187	"wt_xicu",
188	x_width + y_width + l_width);
189
190	/////////////////////////////////////////////////////////////////////////////
191	std::ostringstream smdma;
192	smdma << "mdma_" << x_id << "_" << y_id;
193	mdma = new VciMultiDma<vci_param_int>(
194	smdma.str().c_str(),
195	mtd,
196	IntTab(cluster_id, nb_procs), // SRCID
197	IntTab(cluster_id, tgtid_mdma), // TGTID
198	64, // burst size
199	nb_dmas); // number of IRQs
200
201	wt_mdma = new VciDspinTargetWrapper<vci_param_int,
202	dspin_cmd_width,
203	dspin_rsp_width>(
204	"wt_mdma",
205	x_width + y_width + l_width);
206
207	wi_mdma = new VciDspinInitiatorWrapper<vci_param_int,
208	dspin_cmd_width,
209	dspin_rsp_width>(
210	"wi_mdma",
211	x_width + y_width + l_width);
212
213	/////////////////////////////////////////////////////////////////////////////
214	size_t nb_direct_initiators = nb_procs + 1;
215	size_t nb_direct_targets = 3;
216	if ( io )
217	{
218	nb_direct_initiators = nb_procs + 3;
219	nb_direct_targets = 9;
220	}
221
222	xbar_cmd_d = new DspinLocalCrossbar<dspin_cmd_width>(
223	"xbar_cmd_d",
224	mtd, // mapping table
225	x_id, y_id, // cluster coordinates
226	x_width, y_width, l_width,
227	nb_direct_initiators, // number of local of sources
228	nb_direct_targets, // number of local dests
229	2, 2, // fifo depths
230	true, // CMD
231	true, // use local routing table
232	false ); // no broadcast
233
234	/////////////////////////////////////////////////////////////////////////////
235	xbar_rsp_d = new DspinLocalCrossbar<dspin_rsp_width>(
236	"xbar_rsp_d",
237	mtd, // mapping table
238	x_id, y_id, // cluster coordinates
239	x_width, y_width, l_width,
240	nb_direct_targets, // number of local sources
241	nb_direct_initiators, // number of local dests
242	2, 2, // fifo depths
243	false, // RSP
244	false, // don't use local routing table
245	false ); // no broadcast
246
247	/////////////////////////////////////////////////////////////////////////////
248	xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>(
249	"xbar_m2p_c",
250	mtd, // mapping table
251	x_id, y_id, // cluster coordinates
252	x_width, y_width, l_width,
253	1, // number of local sources
254	nb_procs, // number of local targets
255	2, 2, // fifo depths
256	true, // CMD
257	false, // don't use local routing table
258	true ); // broadcast
259
260	/////////////////////////////////////////////////////////////////////////////
261	xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>(
262	"xbar_p2m_c",
263	mtd, // mapping table
264	x_id, y_id, // cluster coordinates
265	x_width, y_width, 0, // l_width unused on p2m network
266	nb_procs, // number of local sources
267	1, // number of local dests
268	2, 2, // fifo depths
269	false, // RSP
270	false, // don't use local routing table
271	false ); // no broadcast
272
273	/////////////////////////////////////////////////////////////////////////////
274	xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
275	"xbar_clack_c",
276	mtd, // mapping table
277	x_id, y_id, // cluster coordinates
278	x_width, y_width, l_width,
279	1, // number of local sources
280	nb_procs, // number of local targets
281	1, 1, // fifo depths
282	true, // CMD
283	false, // don't use local routing table
284	false); // broadcast
285
286	/////////////////////////////////////////////////////////////////////////////
287	router_cmd = new VirtualDspinRouter<dspin_cmd_width>(
288	"router_cmd",
289	x_id,y_id, // coordinate in the mesh
290	x_width, y_width, // x & y fields width
291	3, // nb virtual channels
292	4,4); // input & output fifo depths
293
294	/////////////////////////////////////////////////////////////////////////////
295	router_rsp = new VirtualDspinRouter<dspin_rsp_width>(
296	"router_rsp",
297	x_id,y_id, // coordinates in mesh
298	x_width, y_width, // x & y fields width
299	2, // nb virtual channels
300	4,4); // input & output fifo depths
301
302	// IO cluster components
303	if ( io )
304	{
305	/////////////////////////////////////////////
306	brom = new VciSimpleRom<vci_param_int>(
307	"brom",
308	IntTab(cluster_id, tgtid_brom),
309	mtd,
310	loader);
311
312	wt_brom = new VciDspinTargetWrapper<vci_param_int,
313	dspin_cmd_width,
314	dspin_rsp_width>(
315	"wt_brom",
316	x_width + y_width + l_width);
317
318	/////////////////////////////////////////////
319	fbuf = new VciFrameBuffer<vci_param_int>(
320	"fbuf",
321	IntTab(cluster_id, tgtid_fbuf),
322	mtd,
323	xfb, yfb);
324
325	wt_fbuf = new VciDspinTargetWrapper<vci_param_int,
326	dspin_cmd_width,
327	dspin_rsp_width>(
328	"wt_fbuf",
329	x_width + y_width + l_width);
330
331	/////////////////////////////////////////////
332	bdev = new VciBlockDeviceTsar<vci_param_int>(
333	"bdev",
334	mtd,
335	IntTab(cluster_id, nb_procs+1),
336	IntTab(cluster_id, tgtid_bdev),
337	disk_name,
338	block_size,
339	64); // burst size
340
341	wt_bdev = new VciDspinTargetWrapper<vci_param_int,
342	dspin_cmd_width,
343	dspin_rsp_width>(
344	"wt_bdev",
345	x_width + y_width + l_width);
346
347	wi_bdev = new VciDspinInitiatorWrapper<vci_param_int,
348	dspin_cmd_width,
349	dspin_rsp_width>(
350	"wi_bdev",
351	x_width + y_width + l_width);
352
353	/////////////////////////////////////////////
354	int mac = 0xBEEF0000;
355	mnic = new VciMultiNic<vci_param_int>(
356	"mnic",
357	IntTab(cluster_id, tgtid_mnic),
358	mtd,
359	nic_channels,
360	nic_rx_name,
361	nic_tx_name,
362	mac, // mac_4 address
363	0xBABE ); // mac_2 address
364
365	wt_mnic = new VciDspinTargetWrapper<vci_param_int,
366	dspin_cmd_width,
367	dspin_rsp_width>(
368	"wt_mnic",
369	x_width + y_width + l_width);
370
371	/////////////////////////////////////////////
372	chbuf = new VciChbufDma<vci_param_int>(
373	"chbuf_dma",
374	mtd,
375	IntTab(cluster_id, nb_procs + 2),
376	IntTab(cluster_id, tgtid_chbuf),
377	64,
378	chbufdma_channels);
379
380	wt_chbuf = new VciDspinTargetWrapper<vci_param_int,
381	dspin_cmd_width,
382	dspin_rsp_width>(
383	"wt_chbuf",
384	x_width + y_width + l_width);
385
386	wi_chbuf = new VciDspinInitiatorWrapper<vci_param_int,
387	dspin_cmd_width,
388	dspin_rsp_width>(
389	"wi_chbuf",
390	x_width + y_width + l_width);
391
392	/////////////////////////////////////////////
393	std::vector<std::string> vect_names;
394	for( size_t tid = 0 ; tid < (nb_ttys) ; tid++ )
395	{
396	std::ostringstream term_name;
397	term_name << "term" << tid;
398	vect_names.push_back(term_name.str().c_str());
399	}
400	mtty = new VciMultiTty<vci_param_int>(
401	"mtty",
402	IntTab(cluster_id, tgtid_mtty),
403	mtd,
404	vect_names);
405
406	wt_mtty = new VciDspinTargetWrapper<vci_param_int,
407	dspin_cmd_width,
408	dspin_rsp_width>(
409	"wt_mtty",
410	x_width + y_width + l_width);
411	}
412
413	////////////////////////////////////
414	// Connections are defined here
415	////////////////////////////////////
416
417	//////////////////////// CMD ROUTER and RSP ROUTER
418	router_cmd->p_clk (this->p_clk);
419	router_cmd->p_resetn (this->p_resetn);
420	router_rsp->p_clk (this->p_clk);
421	router_rsp->p_resetn (this->p_resetn);
422
423	for(int i = 0; i < 4; i++)
424	{
425	for (int k = 0; k < 3; k++)
426	{
427	router_cmd->p_out[i][k] (this->p_cmd_out[i][k]);
428	router_cmd->p_in[i][k] (this->p_cmd_in[i][k]);
429	}
430
431	for (int k = 0; k < 2; k++)
432	{
433	router_rsp->p_out[i][k] (this->p_rsp_out[i][k]);
434	router_rsp->p_in[i][k] (this->p_rsp_in[i][k]);
435	}
436	}
437
438	router_cmd->p_out[4][0] (signal_dspin_cmd_g2l_d);
439	router_cmd->p_out[4][1] (signal_dspin_m2p_g2l_c);
440	router_cmd->p_out[4][2] (signal_dspin_clack_g2l_c);
441	router_cmd->p_in[4][0] (signal_dspin_cmd_l2g_d);
442	router_cmd->p_in[4][1] (signal_dspin_m2p_l2g_c);
443	router_cmd->p_in[4][2] (signal_dspin_clack_l2g_c);
444
445	router_rsp->p_out[4][0] (signal_dspin_rsp_g2l_d);
446	router_rsp->p_out[4][1] (signal_dspin_p2m_g2l_c);
447	router_rsp->p_in[4][0] (signal_dspin_rsp_l2g_d);
448	router_rsp->p_in[4][1] (signal_dspin_p2m_l2g_c);
449
450
451	std::cout << " - CMD & RSP routers connected" << std::endl;
452
453	///////////////////// CMD DSPIN local crossbar direct
454	xbar_cmd_d->p_clk (this->p_clk);
455	xbar_cmd_d->p_resetn (this->p_resetn);
456	xbar_cmd_d->p_global_out (signal_dspin_cmd_l2g_d);
457	xbar_cmd_d->p_global_in (signal_dspin_cmd_g2l_d);
458
459	xbar_cmd_d->p_local_out[tgtid_memc] (signal_dspin_cmd_memc_t);
460	xbar_cmd_d->p_local_out[tgtid_xicu] (signal_dspin_cmd_xicu_t);
461	xbar_cmd_d->p_local_out[tgtid_mdma] (signal_dspin_cmd_mdma_t);
462
463	xbar_cmd_d->p_local_in[nb_procs] (signal_dspin_cmd_mdma_i);
464
465	for (size_t p = 0; p < nb_procs; p++)
466	xbar_cmd_d->p_local_in[p] (signal_dspin_cmd_proc_i[p]);
467
468	if ( io )
469	{
470	xbar_cmd_d->p_local_out[tgtid_mtty] (signal_dspin_cmd_mtty_t);
471	xbar_cmd_d->p_local_out[tgtid_brom] (signal_dspin_cmd_brom_t);
472	xbar_cmd_d->p_local_out[tgtid_bdev] (signal_dspin_cmd_bdev_t);
473	xbar_cmd_d->p_local_out[tgtid_fbuf] (signal_dspin_cmd_fbuf_t);
474	xbar_cmd_d->p_local_out[tgtid_mnic] (signal_dspin_cmd_mnic_t);
475	xbar_cmd_d->p_local_out[tgtid_chbuf] (signal_dspin_cmd_chbuf_t);
476
477	xbar_cmd_d->p_local_in[nb_procs+1] (signal_dspin_cmd_bdev_i);
478	xbar_cmd_d->p_local_in[nb_procs+2] (signal_dspin_cmd_chbuf_i);
479	}
480
481	std::cout << " - Command Direct crossbar connected" << std::endl;
482
483	//////////////////////// RSP DSPIN local crossbar direct
484	xbar_rsp_d->p_clk (this->p_clk);
485	xbar_rsp_d->p_resetn (this->p_resetn);
486	xbar_rsp_d->p_global_out (signal_dspin_rsp_l2g_d);
487	xbar_rsp_d->p_global_in (signal_dspin_rsp_g2l_d);
488
489	xbar_rsp_d->p_local_in[tgtid_memc] (signal_dspin_rsp_memc_t);
490	xbar_rsp_d->p_local_in[tgtid_xicu] (signal_dspin_rsp_xicu_t);
491	xbar_rsp_d->p_local_in[tgtid_mdma] (signal_dspin_rsp_mdma_t);
492
493	xbar_rsp_d->p_local_out[nb_procs] (signal_dspin_rsp_mdma_i);
494
495	for (size_t p = 0; p < nb_procs; p++)
496	xbar_rsp_d->p_local_out[p] (signal_dspin_rsp_proc_i[p]);
497
498	if ( io )
499	{
500	xbar_rsp_d->p_local_in[tgtid_mtty] (signal_dspin_rsp_mtty_t);
501	xbar_rsp_d->p_local_in[tgtid_brom] (signal_dspin_rsp_brom_t);
502	xbar_rsp_d->p_local_in[tgtid_bdev] (signal_dspin_rsp_bdev_t);
503	xbar_rsp_d->p_local_in[tgtid_fbuf] (signal_dspin_rsp_fbuf_t);
504	xbar_rsp_d->p_local_in[tgtid_mnic] (signal_dspin_rsp_mnic_t);
505	xbar_rsp_d->p_local_in[tgtid_chbuf] (signal_dspin_rsp_chbuf_t);
506
507	xbar_rsp_d->p_local_out[nb_procs+1] (signal_dspin_rsp_bdev_i);
508	xbar_rsp_d->p_local_out[nb_procs+2] (signal_dspin_rsp_chbuf_i);
509	}
510
511	std::cout << " - Response Direct crossbar connected" << std::endl;
512
513	////////////////////// M2P DSPIN local crossbar coherence
514	xbar_m2p_c->p_clk (this->p_clk);
515	xbar_m2p_c->p_resetn (this->p_resetn);
516	xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c);
517	xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c);
518	xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc);
519	for (size_t p = 0; p < nb_procs; p++)
520	xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]);
521
522	std::cout << " - M2P Coherence crossbar connected" << std::endl;
523
524	////////////////////// CLACK DSPIN local crossbar coherence
525	xbar_clack_c->p_clk (this->p_clk);
526	xbar_clack_c->p_resetn (this->p_resetn);
527	xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c);
528	xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c);
529	xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc);
530	for (size_t p = 0; p < nb_procs; p++)
531	xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]);
532
533	std::cout << " - Clack Coherence crossbar connected" << std::endl;
534
535	////////////////////////// P2M DSPIN local crossbar coherence
536	xbar_p2m_c->p_clk (this->p_clk);
537	xbar_p2m_c->p_resetn (this->p_resetn);
538	xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c);
539	xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c);
540	xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc);
541	for (size_t p = 0; p < nb_procs; p++)
542	xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]);
543
544	std::cout << " - P2M Coherence crossbar connected" << std::endl;
545
546
547	//////////////////////////////////// Processors
548	for (size_t p = 0; p < nb_procs; p++)
549	{
550	proc[p]->p_clk (this->p_clk);
551	proc[p]->p_resetn (this->p_resetn);
552	proc[p]->p_vci (signal_vci_ini_proc[p]);
553	proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]);
554	proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]);
555	proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]);
556	proc[p]->p_irq[0] (signal_proc_it[p]);
557	for ( size_t j = 1 ; j < 6 ; j++)
558	{
559	proc[p]->p_irq[j] (signal_false);
560	}
561
562	wi_proc[p]->p_clk (this->p_clk);
563	wi_proc[p]->p_resetn (this->p_resetn);
564	wi_proc[p]->p_dspin_cmd (signal_dspin_cmd_proc_i[p]);
565	wi_proc[p]->p_dspin_rsp (signal_dspin_rsp_proc_i[p]);
566	wi_proc[p]->p_vci (signal_vci_ini_proc[p]);
567	}
568
569	std::cout << " - Processors connected" << std::endl;
570
571	///////////////////////////////////// XICU
572	xicu->p_clk (this->p_clk);
573	xicu->p_resetn (this->p_resetn);
574	xicu->p_vci (signal_vci_tgt_xicu);
575	for ( size_t p=0 ; p<nb_procs ; p++)
576	{
577	xicu->p_irq[p] (signal_proc_it[p]);
578	}
579	for ( size_t i=0 ; i<32 ; i++)
580	{
581	if ( io ) // I/O cluster
582	{
583	if (i < 8) xicu->p_hwi[i] (signal_false);
584	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]);
585	else if (i < 16) xicu->p_hwi[i] (signal_false);
586	else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i-16]);
587	else if (i < 31) xicu->p_hwi[i] (signal_false);
588	else xicu->p_hwi[i] (signal_irq_bdev);
589	}
590	else // other clusters
591	{
592	if (i < 8) xicu->p_hwi[i] (signal_false);
593	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]);
594	else xicu->p_hwi[i] (signal_false);
595	}
596	}
597
598	// wrapper XICU
599	wt_xicu->p_clk (this->p_clk);
600	wt_xicu->p_resetn (this->p_resetn);
601	wt_xicu->p_dspin_cmd (signal_dspin_cmd_xicu_t);
602	wt_xicu->p_dspin_rsp (signal_dspin_rsp_xicu_t);
603	wt_xicu->p_vci (signal_vci_tgt_xicu);
604
605	std::cout << " - XICU connected" << std::endl;
606
607	//////////////////////////////////////////////// MEMC
608	memc->p_clk (this->p_clk);
609	memc->p_resetn (this->p_resetn);
610	memc->p_vci_ixr (signal_vci_xram);
611	memc->p_vci_tgt (signal_vci_tgt_memc);
612	memc->p_dspin_p2m (signal_dspin_p2m_memc);
613	memc->p_dspin_m2p (signal_dspin_m2p_memc);
614	memc->p_dspin_clack (signal_dspin_clack_memc);
615
616	// wrapper MEMC
617	wt_memc->p_clk (this->p_clk);
618	wt_memc->p_resetn (this->p_resetn);
619	wt_memc->p_dspin_cmd (signal_dspin_cmd_memc_t);
620	wt_memc->p_dspin_rsp (signal_dspin_rsp_memc_t);
621	wt_memc->p_vci (signal_vci_tgt_memc);
622
623	std::cout << " - MEMC connected" << std::endl;
624
625	/////////////////////////////////////////////// XRAM
626	xram->p_clk (this->p_clk);
627	xram->p_resetn (this->p_resetn);
628	xram->p_vci (signal_vci_xram);
629
630	std::cout << " - XRAM connected" << std::endl;
631
632	////////////////////////////////////////////// MDMA
633	mdma->p_clk (this->p_clk);
634	mdma->p_resetn (this->p_resetn);
635	mdma->p_vci_target (signal_vci_tgt_mdma);
636	mdma->p_vci_initiator (signal_vci_ini_mdma);
637	for (size_t i=0 ; i<nb_dmas ; i++)
638	mdma->p_irq[i] (signal_irq_mdma[i]);
639
640	// wrapper tgt MDMA
641	wt_mdma->p_clk (this->p_clk);
642	wt_mdma->p_resetn (this->p_resetn);
643	wt_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_t);
644	wt_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_t);
645	wt_mdma->p_vci (signal_vci_tgt_mdma);
646
647	// wrapper ini MDMA
648	wi_mdma->p_clk (this->p_clk);
649	wi_mdma->p_resetn (this->p_resetn);
650	wi_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_i);
651	wi_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_i);
652	wi_mdma->p_vci (signal_vci_ini_mdma);
653
654	std::cout << " - MDMA connected" << std::endl;
655
656	/////////////////////////////// Components in I/O cluster
657
658	if ( io )
659	{
660	// BDEV
661	bdev->p_clk (this->p_clk);
662	bdev->p_resetn (this->p_resetn);
663	bdev->p_irq (signal_irq_bdev);
664	bdev->p_vci_target (signal_vci_tgt_bdev);
665	bdev->p_vci_initiator (signal_vci_ini_bdev);
666
667	// wrapper tgt BDEV
668	wt_bdev->p_clk (this->p_clk);
669	wt_bdev->p_resetn (this->p_resetn);
670	wt_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_t);
671	wt_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_t);
672	wt_bdev->p_vci (signal_vci_tgt_bdev);
673
674	// wrapper ini BDEV
675	wi_bdev->p_clk (this->p_clk);
676	wi_bdev->p_resetn (this->p_resetn);
677	wi_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_i);
678	wi_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_i);
679	wi_bdev->p_vci (signal_vci_ini_bdev);
680
681	std::cout << " - BDEV connected" << std::endl;
682
683	// FBUF
684	fbuf->p_clk (this->p_clk);
685	fbuf->p_resetn (this->p_resetn);
686	fbuf->p_vci (signal_vci_tgt_fbuf);
687
688	// wrapper tgt FBUF
689	wt_fbuf->p_clk (this->p_clk);
690	wt_fbuf->p_resetn (this->p_resetn);
691	wt_fbuf->p_dspin_cmd (signal_dspin_cmd_fbuf_t);
692	wt_fbuf->p_dspin_rsp (signal_dspin_rsp_fbuf_t);
693	wt_fbuf->p_vci (signal_vci_tgt_fbuf);
694
695	std::cout << " - FBUF connected" << std::endl;
696
697	// MNIC
698	mnic->p_clk (this->p_clk);
699	mnic->p_resetn (this->p_resetn);
700	mnic->p_vci (signal_vci_tgt_mnic);
701	for ( size_t i=0 ; i<nic_channels ; i++ )
702	{
703	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
704	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
705	}
706
707	// wrapper tgt MNIC
708	wt_mnic->p_clk (this->p_clk);
709	wt_mnic->p_resetn (this->p_resetn);
710	wt_mnic->p_dspin_cmd (signal_dspin_cmd_mnic_t);
711	wt_mnic->p_dspin_rsp (signal_dspin_rsp_mnic_t);
712	wt_mnic->p_vci (signal_vci_tgt_mnic);
713
714	std::cout << " - MNIC connected" << std::endl;
715
716	// CHBUF
717	chbuf->p_clk (this->p_clk);
718	chbuf->p_resetn (this->p_resetn);
719	chbuf->p_vci_target (signal_vci_tgt_chbuf);
720	chbuf->p_vci_initiator (signal_vci_ini_chbuf);
721	for ( size_t i=0 ; i < chbufdma_channels ; i++ )
722	{
723	chbuf->p_irq[i] (signal_irq_chbuf[i]);
724	}
725
726	// wrapper tgt CHBUF
727	wt_chbuf->p_clk (this->p_clk);
728	wt_chbuf->p_resetn (this->p_resetn);
729	wt_chbuf->p_dspin_cmd (signal_dspin_cmd_chbuf_t);
730	wt_chbuf->p_dspin_rsp (signal_dspin_rsp_chbuf_t);
731	wt_chbuf->p_vci (signal_vci_tgt_chbuf);
732
733	// wrapper ini CHBUF
734	wi_chbuf->p_clk (this->p_clk);
735	wi_chbuf->p_resetn (this->p_resetn);
736	wi_chbuf->p_dspin_cmd (signal_dspin_cmd_chbuf_i);
737	wi_chbuf->p_dspin_rsp (signal_dspin_rsp_chbuf_i);
738	wi_chbuf->p_vci (signal_vci_ini_chbuf);
739
740	std::cout << " - CHBUF connected" << std::endl;
741
742	// BROM
743	brom->p_clk (this->p_clk);
744	brom->p_resetn (this->p_resetn);
745	brom->p_vci (signal_vci_tgt_brom);
746
747	// wrapper tgt BROM
748	wt_brom->p_clk (this->p_clk);
749	wt_brom->p_resetn (this->p_resetn);
750	wt_brom->p_dspin_cmd (signal_dspin_cmd_brom_t);
751	wt_brom->p_dspin_rsp (signal_dspin_rsp_brom_t);
752	wt_brom->p_vci (signal_vci_tgt_brom);
753
754	std::cout << " - BROM connected" << std::endl;
755
756	// MTTY
757	mtty->p_clk (this->p_clk);
758	mtty->p_resetn (this->p_resetn);
759	mtty->p_vci (signal_vci_tgt_mtty);
760	for ( size_t i=0 ; i<nb_ttys ; i++ )
761	{
762	mtty->p_irq[i] (signal_irq_mtty[i]);
763	}
764
765	// wrapper tgt MTTY
766	wt_mtty->p_clk (this->p_clk);
767	wt_mtty->p_resetn (this->p_resetn);
768	wt_mtty->p_dspin_cmd (signal_dspin_cmd_mtty_t);
769	wt_mtty->p_dspin_rsp (signal_dspin_rsp_mtty_t);
770	wt_mtty->p_vci (signal_vci_tgt_mtty);
771
772	std::cout << " - MTTY connected" << std::endl;
773	}
774	} // end constructor
775
776	}}
777
778	// Local Variables:
779	// tab-width: 3
780	// c-basic-offset: 3
781	// c-file-offsets:((innamespace . 0)(inline-open . 0))
782	// indent-tabs-mode: nil
783	// End:
784
785	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
786
787
788

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Project-Id-Version: Trac 0.12
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