1 | #!/usr/bin/env python |
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2 | |
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3 | from math import log, ceil |
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4 | from mapping import * |
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5 | |
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6 | ############################################################################### |
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7 | # file : arch.py (for the tsar_monocluster_fpga architecture) |
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8 | # date : March 2015 |
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9 | # author : Cesar Fuguet |
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10 | ############################################################################### |
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11 | # This file contains a mapping generator for the "tsar_mono_fpga" |
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12 | # platform. |
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13 | # This includes both the hardware architecture (clusters, processors, |
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14 | # peripherals, physical space segmentation) and the mapping of all boot |
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15 | # and kernel objects (global vsegs). |
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16 | # |
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17 | # It is inspired on the tsar_mono_fpga platform but includes a ROM in the |
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18 | # cluster. |
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19 | # |
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20 | # The others hardware parameters are: |
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21 | # - fbf_width : frame_buffer width = frame_buffer heigth |
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22 | # - nb_ttys : number of TTY channels |
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23 | # - nb_nics : number of NIC channels |
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24 | # - nb_cmas : number of CMA channels |
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25 | # - irq_per_proc : number of input IRQs per processor |
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26 | # - use_ramdisk : use a RAMDISK when True |
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27 | # - peri_increment : address increment for replicated peripherals |
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28 | ############################################################################### |
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29 | |
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30 | ######################## |
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31 | def arch( x_size = 1, |
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32 | y_size = 1, |
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33 | nb_procs = 2, |
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34 | nb_ttys = 1, |
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35 | fbf_width = 480, |
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36 | ioc_type = 'BDV' ): |
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37 | |
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38 | ### define architecture constants |
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39 | |
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40 | x_io = 0 |
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41 | y_io = 0 |
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42 | x_width = 4 |
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43 | y_width = 4 |
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44 | p_width = 2 |
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45 | paddr_width = 40 |
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46 | irq_per_proc = 4 |
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47 | use_ramdisk = False |
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48 | peri_increment = 0x10000 # distributed peripherals vbase increment |
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49 | reset_address = 0xFF000000 # wired preloader pbase address |
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50 | use_backup_peri = True |
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51 | |
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52 | ### parameters checking |
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53 | |
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54 | assert( nb_procs <= (1 << p_width) ) |
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55 | assert( (x_size == 1) and (y_size == 1) ); |
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56 | |
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57 | ### define type and name |
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58 | |
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59 | platform_type = 'tsar_fpga' |
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60 | platform_name = '%s_%d' % (platform_type, nb_procs ) |
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61 | |
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62 | ### define physical segments replicated in all clusters |
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63 | ### the base address is extended by the cluster_xy (8 bits) |
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64 | |
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65 | ram_base = 0x00000000 |
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66 | ram_size = 0x8000000 # 128 Mbytes |
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67 | |
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68 | xcu_base = 0xF0000000 |
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69 | xcu_size = 0x1000 # 4 Kbytes |
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70 | |
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71 | mmc_base = 0xF1000000 |
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72 | mmc_size = 0x1000 # 4 Kbytes |
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73 | |
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74 | rom_base = 0xFF000000 |
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75 | rom_size = 0x10000 # 64 Kbytes |
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76 | |
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77 | bdv_base = 0xF2000000 |
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78 | bdv_size = 0x1000 # 4kbytes |
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79 | |
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80 | tty_base = 0xF4000000 |
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81 | tty_size = 0x4000 # 16 Kbytes |
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82 | |
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83 | fbf_base = 0xF3000000 |
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84 | fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes |
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85 | |
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86 | ### define preloader & bootloader vsegs base addresses and sizes |
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87 | ### We want to pack these 5 vsegs in the same big page |
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88 | ### => boot cost is one BPP in cluster[0][0] |
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89 | |
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90 | preloader_vbase = reset_address # ident |
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91 | preloader_size = 0x00010000 # 64 Kbytes |
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92 | |
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93 | boot_mapping_vbase = 0x00010000 # ident |
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94 | boot_mapping_size = 0x00080000 # 512 Kbytes |
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95 | |
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96 | boot_code_vbase = 0x00090000 # ident |
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97 | boot_code_size = 0x00040000 # 256 Kbytes |
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98 | |
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99 | boot_data_vbase = 0x000D0000 # ident |
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100 | boot_data_size = 0x000B0000 # 704 Kbytes |
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101 | |
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102 | boot_stack_vbase = 0x00180000 # ident |
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103 | boot_stack_size = 0x00080000 # 512 Kbytes |
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104 | |
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105 | ### define ramdisk vseg / must be identity mapping in cluster[0][0] |
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106 | ### occupies 15 BPP after the boot |
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107 | ramdisk_vbase = 0x00200000 |
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108 | ramdisk_size = 0x02000000 # 32 Mbytes |
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109 | |
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110 | ### define kernel vsegs base addresses and sizes |
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111 | ### code, init, ptab, heap & sched vsegs are replicated in all clusters. |
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112 | ### data & uncdata vsegs are only mapped in cluster[0][0]. |
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113 | |
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114 | kernel_code_vbase = 0x80000000 |
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115 | kernel_code_size = 0x00100000 # 1 Mbytes per cluster |
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116 | |
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117 | kernel_init_vbase = 0x80100000 |
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118 | kernel_init_size = 0x00100000 # 1 Mbytes per cluster |
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119 | |
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120 | kernel_data_vbase = 0x90000000 |
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121 | kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0][0] |
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122 | |
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123 | kernel_ptab_vbase = 0xE0000000 |
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124 | kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster |
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125 | |
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126 | kernel_heap_vbase = 0xD0000000 |
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127 | kernel_heap_size = 0x00200000 # 2 Mbytes per cluster |
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128 | |
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129 | kernel_sched_vbase = 0xA0000000 |
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130 | kernel_sched_size = 0x00002000 * nb_procs # 8 kbytes per proc per cluster |
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131 | |
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132 | ##################### |
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133 | ### create mapping |
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134 | ##################### |
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135 | |
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136 | mapping = Mapping( name = platform_name, |
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137 | x_size = x_size, |
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138 | y_size = y_size, |
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139 | nprocs = nb_procs, |
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140 | x_width = x_width, |
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141 | y_width = y_width, |
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142 | p_width = p_width, |
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143 | paddr_width = paddr_width, |
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144 | coherence = True, |
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145 | irq_per_proc = irq_per_proc, |
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146 | use_ramdisk = use_ramdisk, |
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147 | x_io = x_io, |
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148 | y_io = y_io, |
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149 | peri_increment = peri_increment, |
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150 | reset_address = reset_address, |
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151 | ram_base = ram_base, |
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152 | ram_size = ram_size ) |
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153 | |
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154 | ########################### |
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155 | ### Hardware Description |
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156 | ########################### |
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157 | |
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158 | ### components replicated in all clusters but the upper row |
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159 | ram = mapping.addRam( 'RAM', base = ram_base, size = ram_size ) |
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160 | |
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161 | xcu = mapping.addPeriph( 'XCU', base = xcu_base, size = xcu_size, |
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162 | ptype = 'XCU', channels = nb_procs * irq_per_proc, |
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163 | arg0 = 16, arg1 = 16, arg2 = 16 ) |
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164 | |
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165 | mmc = mapping.addPeriph( 'MMC', base = mmc_base, size = mmc_size, |
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166 | ptype = 'MMC' ) |
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167 | |
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168 | mapping.addIrq( xcu, index = 8 , src = mmc, isrtype = 'ISR_MMC' ) |
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169 | |
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170 | for p in xrange ( nb_procs ): mapping.addProc( 0, 0, p ) |
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171 | |
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172 | bdv = mapping.addPeriph( 'BDV0', base = bdv_base, size = bdv_size, |
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173 | ptype = 'IOC', subtype = 'BDV' ) |
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174 | |
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175 | mapping.addIrq( xcu, index = 9 , src = bdv, isrtype = 'ISR_BDV' ) |
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176 | |
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177 | tty = mapping.addPeriph( 'TTY0', base = tty_base, size = tty_size, |
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178 | ptype = 'TTY', channels = nb_ttys ) |
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179 | |
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180 | mapping.addIrq( xcu, index = 10, src = tty, isrtype = 'ISR_TTY_RX' ) |
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181 | |
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182 | rom = mapping.addPeriph( 'ROM', base = rom_base, size = rom_size, |
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183 | ptype = 'ROM' ) |
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184 | |
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185 | fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, |
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186 | ptype = 'FBF', arg0 = fbf_width , arg1 = fbf_width) |
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187 | |
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188 | ################################### |
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189 | ### boot & kernel vsegs mapping |
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190 | ################################### |
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191 | |
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192 | ### global vsegs for preloader & boot_loader are mapped in cluster[0][0] |
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193 | ### => same flags CXW_ / identity mapping / non local / big page |
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194 | |
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195 | mapping.addGlobal( 'seg_preloader', preloader_vbase, preloader_size, |
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196 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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197 | identity = True, local = False, big = True ) |
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198 | |
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199 | mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size, |
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200 | 'CXW_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', |
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201 | identity = True, local = False, big = True ) |
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202 | |
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203 | mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size, |
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204 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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205 | identity = True, local = False, big = True ) |
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206 | |
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207 | mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size, |
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208 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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209 | identity = True, local = False, big = True ) |
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210 | |
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211 | mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size, |
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212 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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213 | identity = True, local = False, big = True ) |
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214 | |
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215 | ### global vseg for RAM-DISK in cluster[0][0] |
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216 | ### identity mapping / non local / big pages |
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217 | if use_ramdisk: |
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218 | |
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219 | mapping.addGlobal( 'seg_ramdisk', ramdisk_vbase, ramdisk_size, |
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220 | 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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221 | identity = True, local = True, big = True ) |
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222 | |
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223 | ### global vsegs kernel_code, kernel_init : local / big page |
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224 | ### replicated in all clusters containing processors |
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225 | ### same content => same name / same vbase |
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226 | mapping.addGlobal( 'seg_kernel_code', |
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227 | kernel_code_vbase, kernel_code_size, |
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228 | 'CXW_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', |
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229 | binpath = 'build/kernel/kernel.elf', |
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230 | local = True, big = True ) |
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231 | |
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232 | mapping.addGlobal( 'seg_kernel_init', |
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233 | kernel_init_vbase, kernel_init_size, |
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234 | 'CXW_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', |
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235 | binpath = 'build/kernel/kernel.elf', |
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236 | local = True, big = True ) |
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237 | |
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238 | ### global vseg kernel_data: non local / big page |
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239 | ### Only mapped in cluster[0][0] |
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240 | mapping.addGlobal( 'seg_kernel_data', |
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241 | kernel_data_vbase, kernel_data_size, |
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242 | 'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', |
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243 | binpath = 'build/kernel/kernel.elf', |
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244 | local = False, big = True ) |
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245 | |
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246 | ### Global vsegs kernel_ptab_x_y: non local / big page |
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247 | ### replicated in all clusters containing processors |
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248 | ### different content => name & vbase indexed by (x,y) |
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249 | mapping.addGlobal( 'seg_kernel_ptab', |
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250 | kernel_ptab_vbase, kernel_ptab_size, |
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251 | 'CXW_', vtype = 'PTAB', x = 0, y = 0, pseg = 'RAM', |
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252 | local = False, big = True ) |
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253 | |
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254 | ### global vsegs kernel_heap_x_y : non local / big pages |
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255 | ### distributed in all clusters containing processors |
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256 | ### different content => name & vbase indexed by (x,y) |
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257 | mapping.addGlobal( 'seg_kernel_heap', |
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258 | kernel_heap_vbase, kernel_heap_size, |
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259 | 'C_W_', vtype = 'HEAP', x = 0 , y = 0 , pseg = 'RAM', |
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260 | local = False, big = True ) |
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261 | |
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262 | ### global vsegs for external peripherals: non local / big page |
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263 | ### only mapped in cluster_io |
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264 | mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, |
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265 | '__W_', vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', |
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266 | local = False, big = True ) |
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267 | |
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268 | mapping.addGlobal( 'seg_tty', tty_base, tty_size, |
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269 | '__W_', vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', |
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270 | local = False, big = True ) |
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271 | |
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272 | mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, |
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273 | '__W_', vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', |
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274 | local = False, big = True ) |
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275 | |
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276 | ### global vsegs for internal peripherals : non local / small pages |
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277 | ### allocated in all clusters containing processors |
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278 | ### name and vbase indexed by (x,y) |
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279 | mapping.addGlobal( 'seg_xcu', |
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280 | xcu_base, xcu_size, |
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281 | '__W_', vtype = 'PERI' , x = 0 , y = 0 , pseg = 'XCU', |
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282 | local = False, big = False ) |
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283 | |
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284 | mapping.addGlobal( 'seg_mmc', |
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285 | mmc_base, mmc_size, |
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286 | '__W_', vtype = 'PERI' , x = 0 , y = 0 , pseg = 'MMC', |
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287 | local = False, big = False ) |
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288 | |
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289 | ### global vsegs kernel_sched : non local / small pages |
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290 | ### allocated in all clusters containing processors |
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291 | ### different content => name & vbase indexed by (x,y) |
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292 | mapping.addGlobal( 'seg_kernel_sched', |
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293 | kernel_sched_vbase, kernel_sched_size, |
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294 | 'C_W_', vtype = 'SCHED', x = 0, y = 0, pseg = 'RAM', |
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295 | local = False, big = False ) |
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296 | |
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297 | return mapping |
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298 | |
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299 | ########################## platform test ############################################# |
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300 | |
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301 | if __name__ == '__main__': |
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302 | mapping = arch( x_size = 1, |
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303 | y_size = 1, |
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304 | nb_procs = 2 ) |
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305 | |
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306 | # print mapping.netbsd_dts() |
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307 | |
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308 | print mapping.xml() |
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309 | |
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310 | # print mapping.giet_vsegs() |
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311 | |
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312 | |
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313 | # Local Variables: |
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314 | # tab-width: 4; |
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315 | # c-basic-offset: 4; |
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316 | # c-file-offsets:((innamespace . 0)(inline-open . 0)); |
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317 | # indent-tabs-mode: nil; |
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318 | # End: |
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319 | # |
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320 | # vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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321 | |
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