| 1 | #!/usr/bin/env python |
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| 2 | |
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| 3 | from math import log, ceil |
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| 4 | from mapping import * |
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| 5 | |
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| 6 | ############################################################################### |
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| 7 | # file : arch.py (for the tsar_monocluster_fpga architecture) |
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| 8 | # date : March 2015 |
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| 9 | # author : Cesar Fuguet |
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| 10 | ############################################################################### |
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| 11 | # This file contains a mapping generator for the "tsar_mono_fpga" |
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| 12 | # platform. |
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| 13 | # This includes both the hardware architecture (clusters, processors, |
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| 14 | # peripherals, physical space segmentation) and the mapping of all boot |
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| 15 | # and kernel objects (global vsegs). |
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| 16 | # |
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| 17 | # It is inspired on the tsar_mono_fpga platform but includes a ROM in the |
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| 18 | # cluster. |
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| 19 | # |
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| 20 | # The others hardware parameters are: |
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| 21 | # - fbf_width : frame_buffer width = frame_buffer heigth |
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| 22 | # - nb_ttys : number of TTY channels |
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| 23 | # - nb_nics : number of NIC channels |
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| 24 | # - nb_cmas : number of CMA channels |
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| 25 | # - irq_per_proc : number of input IRQs per processor |
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| 26 | # - use_ramdisk : use a RAMDISK when True |
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| 27 | # - peri_increment : address increment for replicated peripherals |
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| 28 | ############################################################################### |
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| 29 | |
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| 30 | ######################## |
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| 31 | def arch( x_size = 1, |
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| 32 | y_size = 1, |
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| 33 | nb_procs = 2, |
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| 34 | nb_ttys = 1, |
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| 35 | fbf_width = 480 ): |
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| 36 | |
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| 37 | ### define architecture constants |
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| 38 | |
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| 39 | x_io = 0 |
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| 40 | y_io = 0 |
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| 41 | x_width = 4 |
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| 42 | y_width = 4 |
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| 43 | p_width = 2 |
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| 44 | paddr_width = 40 |
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| 45 | irq_per_proc = 4 |
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| 46 | use_ramdisk = False |
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| 47 | peri_increment = 0x10000 # distributed peripherals vbase increment |
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| 48 | reset_address = 0xFF000000 # wired preloader pbase address |
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| 49 | use_backup_peri = True |
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| 50 | |
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| 51 | ### parameters checking |
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| 52 | |
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| 53 | assert( nb_procs <= (1 << p_width) ) |
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| 54 | assert( (x_size == 1) and (y_size == 1) ); |
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| 55 | |
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| 56 | ### define type and name |
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| 57 | |
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| 58 | platform_type = 'tsar_fpga' |
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| 59 | platform_name = '%s_%d' % (platform_type, nb_procs ) |
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| 60 | |
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| 61 | ### define physical segments replicated in all clusters |
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| 62 | ### the base address is extended by the cluster_xy (8 bits) |
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| 63 | |
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| 64 | ram_base = 0x00000000 |
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| 65 | ram_size = 0x8000000 # 128 Mbytes |
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| 66 | |
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| 67 | xcu_base = 0xF0000000 |
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| 68 | xcu_size = 0x1000 # 4 Kbytes |
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| 69 | |
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| 70 | mmc_base = 0xF1000000 |
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| 71 | mmc_size = 0x1000 # 4 Kbytes |
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| 72 | |
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| 73 | rom_base = 0xFF000000 |
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| 74 | rom_size = 0x10000 # 64 Kbytes |
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| 75 | |
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| 76 | bdv_base = 0xF2000000 |
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| 77 | bdv_size = 0x1000 # 4kbytes |
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| 78 | |
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| 79 | tty_base = 0xF4000000 |
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| 80 | tty_size = 0x4000 # 16 Kbytes |
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| 81 | |
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| 82 | fbf_base = 0xF3000000 |
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| 83 | fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes |
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| 84 | |
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| 85 | ### define preloader & bootloader vsegs base addresses and sizes |
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| 86 | ### We want to pack these 5 vsegs in the same big page |
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| 87 | ### => boot cost is one BPP in cluster[0][0] |
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| 88 | |
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| 89 | preloader_vbase = reset_address # ident |
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| 90 | preloader_size = 0x00010000 # 64 Kbytes |
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| 91 | |
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| 92 | boot_mapping_vbase = 0x00010000 # ident |
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| 93 | boot_mapping_size = 0x00080000 # 512 Kbytes |
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| 94 | |
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| 95 | boot_code_vbase = 0x00090000 # ident |
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| 96 | boot_code_size = 0x00040000 # 256 Kbytes |
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| 97 | |
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| 98 | boot_data_vbase = 0x000D0000 # ident |
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| 99 | boot_data_size = 0x000B0000 # 704 Kbytes |
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| 100 | |
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| 101 | boot_stack_vbase = 0x00180000 # ident |
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| 102 | boot_stack_size = 0x00080000 # 512 Kbytes |
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| 103 | |
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| 104 | ### define ramdisk vseg / must be identity mapping in cluster[0][0] |
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| 105 | ### occupies 15 BPP after the boot |
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| 106 | ramdisk_vbase = 0x00200000 |
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| 107 | ramdisk_size = 0x02000000 # 32 Mbytes |
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| 108 | |
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| 109 | ### define kernel vsegs base addresses and sizes |
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| 110 | ### code, init, ptab, heap & sched vsegs are replicated in all clusters. |
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| 111 | ### data & uncdata vsegs are only mapped in cluster[0][0]. |
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| 112 | |
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| 113 | kernel_code_vbase = 0x80000000 |
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| 114 | kernel_code_size = 0x00100000 # 1 Mbytes per cluster |
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| 115 | |
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| 116 | kernel_init_vbase = 0x80100000 |
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| 117 | kernel_init_size = 0x00100000 # 1 Mbytes per cluster |
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| 118 | |
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| 119 | kernel_data_vbase = 0x90000000 |
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| 120 | kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0][0] |
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| 121 | |
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| 122 | kernel_ptab_vbase = 0xE0000000 |
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| 123 | kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster |
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| 124 | |
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| 125 | kernel_heap_vbase = 0xD0000000 |
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| 126 | kernel_heap_size = 0x00200000 # 2 Mbytes per cluster |
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| 127 | |
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| 128 | kernel_sched_vbase = 0xA0000000 |
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| 129 | kernel_sched_size = 0x00002000 * nb_procs # 8 kbytes per proc per cluster |
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| 130 | |
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| 131 | ##################### |
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| 132 | ### create mapping |
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| 133 | ##################### |
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| 134 | |
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| 135 | mapping = Mapping( name = platform_name, |
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| 136 | x_size = x_size, |
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| 137 | y_size = y_size, |
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| 138 | nprocs = nb_procs, |
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| 139 | x_width = x_width, |
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| 140 | y_width = y_width, |
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| 141 | p_width = p_width, |
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| 142 | paddr_width = paddr_width, |
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| 143 | coherence = True, |
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| 144 | irq_per_proc = irq_per_proc, |
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| 145 | use_ramdisk = use_ramdisk, |
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| 146 | x_io = x_io, |
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| 147 | y_io = y_io, |
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| 148 | peri_increment = peri_increment, |
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| 149 | reset_address = reset_address, |
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| 150 | ram_base = ram_base, |
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| 151 | ram_size = ram_size ) |
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| 152 | |
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| 153 | ########################### |
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| 154 | ### Hardware Description |
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| 155 | ########################### |
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| 156 | |
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| 157 | ### components replicated in all clusters but the upper row |
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| 158 | ram = mapping.addRam( 'RAM', base = ram_base, size = ram_size ) |
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| 159 | |
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| 160 | xcu = mapping.addPeriph( 'XCU', base = xcu_base, size = xcu_size, |
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| 161 | ptype = 'XCU', channels = nb_procs * irq_per_proc, |
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| 162 | arg0 = 16, arg1 = 16, arg2 = 16 ) |
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| 163 | |
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| 164 | mmc = mapping.addPeriph( 'MMC', base = mmc_base, size = mmc_size, |
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| 165 | ptype = 'MMC' ) |
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| 166 | |
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| 167 | mapping.addIrq( xcu, index = 8 , isrtype = 'ISR_MMC' ) |
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| 168 | |
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| 169 | for p in xrange ( nb_procs ): mapping.addProc( 0, 0, p ) |
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| 170 | |
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| 171 | bdv = mapping.addPeriph( 'BDV0', base = bdv_base, size = bdv_size, |
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| 172 | ptype = 'IOC', subtype = 'BDV' ) |
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| 173 | |
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| 174 | mapping.addIrq( xcu, index = 9 , isrtype = 'ISR_BDV' ) |
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| 175 | |
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| 176 | tty = mapping.addPeriph( 'TTY0', base = tty_base, size = tty_size, |
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| 177 | ptype = 'TTY', channels = nb_ttys ) |
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| 178 | |
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| 179 | mapping.addIrq( xcu, index = 10, isrtype = 'ISR_TTY_RX' ) |
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| 180 | |
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| 181 | rom = mapping.addPeriph( 'ROM', base = rom_base, size = rom_size, |
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| 182 | ptype = 'ROM' ) |
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| 183 | |
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| 184 | fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, |
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| 185 | ptype = 'FBF', arg0 = fbf_width , arg1 = fbf_width) |
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| 186 | |
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| 187 | ################################### |
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| 188 | ### boot & kernel vsegs mapping |
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| 189 | ################################### |
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| 190 | |
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| 191 | ### global vsegs for preloader & boot_loader are mapped in cluster[0][0] |
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| 192 | ### => same flags CXW_ / identity mapping / non local / big page |
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| 193 | |
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| 194 | mapping.addGlobal( 'seg_preloader', preloader_vbase, preloader_size, |
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| 195 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 196 | identity = True, local = False, big = True ) |
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| 197 | |
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| 198 | mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size, |
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| 199 | 'CXW_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', |
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| 200 | identity = True, local = False, big = True ) |
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| 201 | |
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| 202 | mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size, |
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| 203 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 204 | identity = True, local = False, big = True ) |
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| 205 | |
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| 206 | mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size, |
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| 207 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 208 | identity = True, local = False, big = True ) |
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| 209 | |
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| 210 | mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size, |
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| 211 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 212 | identity = True, local = False, big = True ) |
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| 213 | |
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| 214 | ### global vseg for RAM-DISK in cluster[0][0] |
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| 215 | ### identity mapping / non local / big pages |
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| 216 | if use_ramdisk: |
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| 217 | |
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| 218 | mapping.addGlobal( 'seg_ramdisk', ramdisk_vbase, ramdisk_size, |
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| 219 | 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 220 | identity = True, local = True, big = True ) |
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| 221 | |
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| 222 | ### global vsegs kernel_code, kernel_init : local / big page |
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| 223 | ### replicated in all clusters containing processors |
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| 224 | ### same content => same name / same vbase |
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| 225 | mapping.addGlobal( 'seg_kernel_code', |
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| 226 | kernel_code_vbase, kernel_code_size, |
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| 227 | 'CXW_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', |
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| 228 | binpath = 'build/kernel/kernel.elf', |
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| 229 | local = True, big = True ) |
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| 230 | |
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| 231 | mapping.addGlobal( 'seg_kernel_init', |
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| 232 | kernel_init_vbase, kernel_init_size, |
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| 233 | 'CXW_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', |
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| 234 | binpath = 'build/kernel/kernel.elf', |
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| 235 | local = True, big = True ) |
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| 236 | |
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| 237 | ### global vseg kernel_data: non local / big page |
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| 238 | ### Only mapped in cluster[0][0] |
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| 239 | mapping.addGlobal( 'seg_kernel_data', |
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| 240 | kernel_data_vbase, kernel_data_size, |
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| 241 | 'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', |
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| 242 | binpath = 'build/kernel/kernel.elf', |
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| 243 | local = False, big = True ) |
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| 244 | |
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| 245 | ### Global vsegs kernel_ptab_x_y: non local / big page |
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| 246 | ### replicated in all clusters containing processors |
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| 247 | ### different content => name & vbase indexed by (x,y) |
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| 248 | mapping.addGlobal( 'seg_kernel_ptab', |
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| 249 | kernel_ptab_vbase, kernel_ptab_size, |
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| 250 | 'CXW_', vtype = 'PTAB', x = 0, y = 0, pseg = 'RAM', |
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| 251 | local = False, big = True ) |
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| 252 | |
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| 253 | ### global vsegs kernel_heap_x_y : non local / big pages |
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| 254 | ### distributed in all clusters containing processors |
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| 255 | ### different content => name & vbase indexed by (x,y) |
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| 256 | mapping.addGlobal( 'seg_kernel_heap', |
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| 257 | kernel_heap_vbase, kernel_heap_size, |
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| 258 | 'C_W_', vtype = 'HEAP', x = 0 , y = 0 , pseg = 'RAM', |
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| 259 | local = False, big = True ) |
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| 260 | |
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| 261 | ### global vsegs for external peripherals: non local / big page |
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| 262 | ### only mapped in cluster_io |
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| 263 | mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, |
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| 264 | '__W_', vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', |
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| 265 | local = False, big = True ) |
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| 266 | |
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| 267 | mapping.addGlobal( 'seg_tty', tty_base, tty_size, |
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| 268 | '__W_', vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', |
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| 269 | local = False, big = True ) |
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| 270 | |
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| 271 | mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, |
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| 272 | '__W_', vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', |
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| 273 | local = False, big = True ) |
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| 274 | |
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| 275 | ### global vsegs for internal peripherals : non local / small pages |
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| 276 | ### allocated in all clusters containing processors |
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| 277 | ### name and vbase indexed by (x,y) |
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| 278 | mapping.addGlobal( 'seg_xcu', |
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| 279 | xcu_base, xcu_size, |
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| 280 | '__W_', vtype = 'PERI' , x = 0 , y = 0 , pseg = 'XCU', |
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| 281 | local = False, big = False ) |
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| 282 | |
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| 283 | mapping.addGlobal( 'seg_mmc', |
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| 284 | mmc_base, mmc_size, |
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| 285 | '__W_', vtype = 'PERI' , x = 0 , y = 0 , pseg = 'MMC', |
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| 286 | local = False, big = False ) |
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| 287 | |
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| 288 | ### global vsegs kernel_sched : non local / small pages |
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| 289 | ### allocated in all clusters containing processors |
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| 290 | ### different content => name & vbase indexed by (x,y) |
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| 291 | mapping.addGlobal( 'seg_kernel_sched', |
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| 292 | kernel_sched_vbase, kernel_sched_size, |
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| 293 | 'C_W_', vtype = 'SCHED', x = 0, y = 0, pseg = 'RAM', |
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| 294 | local = False, big = False ) |
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| 295 | |
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| 296 | return mapping |
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| 297 | |
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| 298 | ########################## platform test ############################################# |
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| 299 | |
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| 300 | if __name__ == '__main__': |
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| 301 | mapping = arch( x_size = 1, |
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| 302 | y_size = 1, |
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| 303 | nb_procs = 2 ) |
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| 304 | |
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| 305 | # print mapping.netbsd_dts() |
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| 306 | |
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| 307 | print mapping.xml() |
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| 308 | |
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| 309 | # print mapping.giet_vsegs() |
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| 310 | |
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| 311 | |
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| 312 | # Local Variables: |
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| 313 | # tab-width: 4; |
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| 314 | # c-basic-offset: 4; |
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| 315 | # c-file-offsets:((innamespace . 0)(inline-open . 0)); |
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| 316 | # indent-tabs-mode: nil; |
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| 317 | # End: |
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| 318 | # |
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| 319 | # vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 320 | |
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