source: trunk/platforms/tsar_mono_fpga/tsar_fpga_cluster/caba/source/include/tsar_fpga_cluster.h @ 957

Last change on this file since 957 was 957, checked in by cfuguet, 9 years ago

Introduce a SocLib? platform implementing the FPGA mono cluster platform

  • This mono cluster platform is the one used for NetBSD and Linux on TSAR demonstrators.
  • It is based on the LETI platform but it contains an internal ROM and all the DSPIN routers have been removed.
File size: 5.3 KB
Line 
1//////////////////////////////////////////////////////////////////////////////
2// File: tsar_fpga_cluster.h
3// Author: Cesar Fuguet
4// Copyright: UPMC/LIP6
5// Date : march 2013
6// This program is released under the GNU public license
7//////////////////////////////////////////////////////////////////////////////
8#ifndef SOCLIB_CABA_TSAR_FPGA_CLUSTER_H
9#define SOCLIB_CABA_TSAR_FPGA_CLUSTER_H
10
11#include <systemc>
12#include <sys/time.h>
13#include <iostream>
14#include <sstream>
15#include <cstdlib>
16#include <cstdarg>
17
18#include "gdbserver.h"
19#include "mapping_table.h"
20#include "mips32.h"
21#include "vci_simple_ram.h"
22#include "vci_xicu.h"
23#include "vci_local_crossbar.h"
24#include "dspin_local_crossbar.h"
25#include "vci_dspin_initiator_wrapper.h"
26#include "vci_dspin_target_wrapper.h"
27#include "vci_multi_tty.h"
28#include "vci_block_device_tsar.h"
29#include "vci_simple_rom.h"
30#include "vci_mem_cache.h"
31#include "vci_cc_vcache_wrapper.h"
32
33namespace soclib { namespace caba {
34
35///////////////////////////////////////////////////////////////////////////
36template<size_t dspin_cmd_width,
37         size_t dspin_rsp_width,
38         typename vci_param_int,
39         typename vci_param_ext>  class TsarFpgaCluster
40///////////////////////////////////////////////////////////////////////////
41    : public soclib::caba::BaseModule
42{
43    public:
44
45    // Used in destructor
46    size_t m_nprocs;
47
48    // Ports
49    sc_in<bool> p_clk;
50    sc_in<bool> p_resetn;
51
52    soclib::caba::DspinOutput<dspin_cmd_width> p_cmd_out;
53    soclib::caba::DspinInput<dspin_cmd_width> p_cmd_in;
54    soclib::caba::DspinOutput<dspin_rsp_width> p_rsp_out;
55    soclib::caba::DspinInput<dspin_rsp_width> p_rsp_in;
56    soclib::caba::DspinOutput<dspin_cmd_width> p_m2p_out;
57    soclib::caba::DspinInput<dspin_cmd_width> p_m2p_in;
58    soclib::caba::DspinOutput<dspin_rsp_width> p_p2m_out;
59    soclib::caba::DspinInput<dspin_rsp_width> p_p2m_in;
60    soclib::caba::DspinOutput<dspin_cmd_width> p_cla_out;
61    soclib::caba::DspinInput<dspin_cmd_width> p_cla_in;
62
63    // interrupt signals
64    sc_signal<bool> signal_false;
65    sc_signal<bool> signal_proc_irq[16];
66    sc_signal<bool> signal_irq_mtty;
67    sc_signal<bool> signal_irq_memc;
68    sc_signal<bool> signal_irq_bdev;
69
70    // Direct VCI signals
71    VciSignals<vci_param_int> signal_vci_ini_proc[4];
72    VciSignals<vci_param_int> signal_vci_ini_bdev;
73    VciSignals<vci_param_int> signal_vci_tgt_memc;
74    VciSignals<vci_param_int> signal_vci_tgt_xicu;
75    VciSignals<vci_param_int> signal_vci_tgt_mtty;
76    VciSignals<vci_param_int> signal_vci_tgt_bdev;
77    VciSignals<vci_param_int> signal_vci_tgt_xrom;
78    VciSignals<vci_param_int> signal_vci_tgt_fbuf;
79    VciSignals<vci_param_int> signal_vci_g2l;
80    VciSignals<vci_param_int> signal_vci_l2g;
81
82    // Coherence DSPIN signals to local crossbar
83    DspinSignals<dspin_cmd_width> signal_dspin_m2p_memc;
84    DspinSignals<dspin_cmd_width> signal_dspin_clack_memc;
85    DspinSignals<dspin_rsp_width> signal_dspin_p2m_memc;
86    DspinSignals<dspin_cmd_width> signal_dspin_m2p_proc[4];
87    DspinSignals<dspin_cmd_width> signal_dspin_clack_proc[4];
88    DspinSignals<dspin_rsp_width> signal_dspin_p2m_proc[4];
89
90    // external RAM to MEMC VCI signal
91    VciSignals<vci_param_ext> signal_vci_xram;
92
93    // Components
94    VciCcVCacheWrapper<vci_param_int,
95                       dspin_cmd_width,
96                       dspin_rsp_width,
97                       GdbServer<Mips32ElIss> >* proc[4];
98
99    VciMemCache<vci_param_int,
100                vci_param_ext,
101                dspin_rsp_width,
102                dspin_cmd_width>* memc;
103
104    VciXicu<vci_param_int>* xicu;
105    VciSimpleRam<vci_param_ext>* xram;
106    VciMultiTty<vci_param_int>* mtty;
107    VciBlockDeviceTsar<vci_param_int>* bdev;
108    VciSimpleRom<vci_param_int>* xrom;
109    VciLocalCrossbar<vci_param_int>* xbar_cmd;
110
111    VciDspinInitiatorWrapper<vci_param_int,
112                             dspin_cmd_width,
113                             dspin_rsp_width>* wi_gate;
114
115    VciDspinTargetWrapper<vci_param_int,
116                          dspin_cmd_width,
117                          dspin_rsp_width>* wt_gate;
118
119    DspinLocalCrossbar<dspin_cmd_width>* xbar_m2p;
120    DspinLocalCrossbar<dspin_rsp_width>* xbar_p2m;
121    DspinLocalCrossbar<dspin_cmd_width>* xbar_cla;
122
123    TsarFpgaCluster( sc_module_name insname,
124                     size_t nb_procs,                           // processors
125                     const soclib::common::MappingTable &mtd,   // internal
126                     const soclib::common::MappingTable &mtx,   // external
127                     uint32_t reset_address,                    // boot address
128                     size_t x_width, size_t y_width, size_t l_width,
129                     size_t tgtid_memc,
130                     size_t tgtid_xicu,
131                     size_t tgtid_mtty,
132                     size_t tgtid_bdev,
133                     size_t tgtid_xrom,
134                     const char* disk_pathname,
135                     size_t memc_ways, size_t memc_sets,
136                     size_t l1_i_ways, size_t l1_i_sets,
137                     size_t l1_d_ways, size_t l1_d_sets,
138                     size_t xram_latency,
139                     const Loader &loader,
140                     uint32_t frozen_cycles,
141                     uint32_t trace_start_cycle,
142                     bool trace_proc_ok, uint32_t trace_proc_id,
143                     bool trace_memc_ok );
144
145    ~TsarFpgaCluster();
146
147};
148}}
149
150#endif
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