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top.cpp @ 877

Last change on this file since 877 was 602, checked in by cfuguet, 11 years ago

Adding IRQ from memory cache for error signalization.

In the tsar_xbar_generic platform, the IRQ has been
connected to the port HWI 30.

In the tsar_mono_mmu, the IRQ has been connected to
the port HWI 2.

File size: 18.4 KB

Line
1
2	#include <systemc>
3	#include <sys/time.h>
4	#include <iostream>
5	#include <cstdlib>
6	#include <cstdarg>
7	#ifdef _OPENMP
8	#include <omp.h>
9	#endif
10
11	#include "mapping_table.h"
12	#include "mips32.h"
13	#include "vci_simple_ram.h"
14	#include "vci_multi_tty.h"
15	#include "vci_mem_cache.h"
16	#include "vci_cc_vcache_wrapper.h"
17	#include "vci_logger.h"
18	#include "vci_xicu.h"
19	#include "vci_multi_dma.h"
20	#include "vci_simhelper.h"
21	#include "dspin_local_crossbar.h"
22	#include "vci_dspin_initiator_wrapper.h"
23	#include "vci_dspin_target_wrapper.h"
24
25	// Define VCI parameters
26	#define cell_width 4
27	#define cell_width_ext 8
28	#define address_width 32
29	#define plen_width 8
30	#define error_width 1
31	#define clen_width 1
32	#define rflag_width 1
33	#define srcid_width 14
34	#define pktid_width 4
35	#define trdid_width 4
36	#define wrplen_width 1
37
38	#define dspin_cmd_width 39
39	#define dspin_rsp_width 32
40	// segments definition in direct space
41
42	#define XICU_BASE 0xd8200000
43	#define XICU_SIZE 0x00001000
44
45	#define MDMA_BASE 0xe8000000
46	#define MDMA_SIZE 0x00000014
47
48	#define MTTY_BASE 0xd0200000
49	#define MTTY_SIZE 0x00000010
50
51	#define EXIT_BASE 0xe0000000
52	#define EXIT_SIZE 0x00000010
53
54	#define BOOT_BASE 0xbfc00000
55	#define BOOT_SIZE 0x00040000
56
57	#define MEMC_BASE 0x00000000
58	#define MEMC_SIZE 0x02000000
59
60	int _main(int argc, char *argv[])
61	{
62	using namespace sc_core;
63	// Avoid repeating these everywhere
64	using soclib::common::IntTab;
65	using soclib::common::Segment;
66	using namespace soclib::caba;
67	#ifdef _OPENMP
68	omp_set_dynamic(false);
69	omp_set_num_threads(1);
70	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
71	#endif
72	char soft_name[256] = "test.elf"; // pathname to binary code
73	size_t ncycles = 1000000000; // max number of simulation cycles
74
75	bool trace_ok = false;
76	size_t from_cycle = 0; // debug start cycle
77	size_t max_frozen = 100000; // max number of frozen cycles
78
79	/////////////// command line arguments ////////////////
80	if (argc > 1)
81	{
82	for( int n=1 ; n<argc ; n=n+2 )
83	{
84	if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
85	{
86	ncycles = atoi(argv[n+1]);
87	}
88	else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
89	{
90	strcpy(soft_name, argv[n+1]);
91	}
92	else if( (strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) )
93	{
94	trace_ok = true;
95	from_cycle = atoi(argv[n+1]);
96	}
97	else if( (strcmp(argv[n],"-MAXFROZEN") == 0) && (n+1<argc) )
98	{
99	max_frozen = atoi(argv[n+1]);
100	}
101	else
102	{
103	std::cout << " Arguments on the command line are (key,value) couples." << std::endl;
104	std::cout << " The order is not important." << std::endl;
105	std::cout << " Accepted arguments are :" << std::endl << std::endl;
106	std::cout << " -SOFT pathname_for_embedded_soft" << std::endl;
107	std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
108	std::cout << " -TRACE debug_start_cycle" << std::endl;
109	exit(0);
110	}
111	}
112	}
113
114	typedef soclib::caba::VciParams<cell_width,
115	plen_width,
116	address_width,
117	error_width,
118	clen_width,
119	rflag_width,
120	srcid_width,
121	pktid_width,
122	trdid_width,
123	wrplen_width> vci_param;
124	typedef soclib::caba::VciParams<cell_width_ext,
125	plen_width,
126	address_width,
127	error_width,
128	clen_width,
129	rflag_width,
130	srcid_width,
131	pktid_width,
132	trdid_width,
133	wrplen_width> vci_param_ext;
134	typedef soclib::common::Mips32ElIss proc_iss;
135
136	// Direct DSPIN signals to local crossbars
137	DspinSignals<dspin_cmd_width> signal_dspin_cmd_proc0_i;
138	DspinSignals<dspin_rsp_width> signal_dspin_rsp_proc0_i;
139	DspinSignals<dspin_cmd_width> signal_dspin_cmd_dma_i;
140	DspinSignals<dspin_rsp_width> signal_dspin_rsp_dma_i;
141
142	DspinSignals<dspin_cmd_width> signal_dspin_cmd_memc_t;
143	DspinSignals<dspin_rsp_width> signal_dspin_rsp_memc_t;
144	DspinSignals<dspin_cmd_width> signal_dspin_cmd_xicu_t;
145	DspinSignals<dspin_rsp_width> signal_dspin_rsp_xicu_t;
146	DspinSignals<dspin_cmd_width> signal_dspin_cmd_dma_t;
147	DspinSignals<dspin_rsp_width> signal_dspin_rsp_dma_t;
148	DspinSignals<dspin_cmd_width> signal_dspin_cmd_tty_t;
149	DspinSignals<dspin_rsp_width> signal_dspin_rsp_tty_t;
150	DspinSignals<dspin_cmd_width> signal_dspin_cmd_rom_t;
151	DspinSignals<dspin_rsp_width> signal_dspin_rsp_rom_t;
152	DspinSignals<dspin_cmd_width> signal_dspin_cmd_simh_t;
153	DspinSignals<dspin_rsp_width> signal_dspin_rsp_simh_t;
154
155	// Coherence DSPIN signals to local crossbar
156	DspinSignals<dspin_cmd_width> signal_dspin_cmd_l2g_c;
157	DspinSignals<dspin_cmd_width> signal_dspin_cmd_g2l_c;
158	DspinSignals<dspin_rsp_width> signal_dspin_rsp_l2g_c;
159	DspinSignals<dspin_rsp_width> signal_dspin_rsp_g2l_c;
160	DspinSignals<dspin_cmd_width> signal_dspin_m2p_l2g_c;
161	DspinSignals<dspin_cmd_width> signal_dspin_m2p_g2l_c;
162	DspinSignals<dspin_rsp_width> signal_dspin_p2m_l2g_c;
163	DspinSignals<dspin_rsp_width> signal_dspin_p2m_g2l_c;
164	DspinSignals<dspin_cmd_width> signal_dspin_clack_l2g_c;
165	DspinSignals<dspin_cmd_width> signal_dspin_clack_g2l_c;
166
167	DspinSignals<dspin_cmd_width> signal_dspin_m2p_memc;
168	DspinSignals<dspin_cmd_width> signal_dspin_clack_memc;
169	DspinSignals<dspin_rsp_width> signal_dspin_p2m_memc;
170	DspinSignals<dspin_cmd_width> signal_dspin_m2p_proc[1];
171	DspinSignals<dspin_cmd_width> signal_dspin_clack_proc[1];
172	DspinSignals<dspin_rsp_width> signal_dspin_p2m_proc[1];
173
174	// Mapping table
175
176	soclib::common::MappingTable maptabp(32, IntTab(0, 16), IntTab(0, srcid_width), 0xF0000000);
177
178	maptabp.add(Segment("mc_m" , MEMC_BASE , MEMC_SIZE , IntTab(0, 0), true));
179	maptabp.add(Segment("boot", BOOT_BASE, BOOT_SIZE, IntTab(0, 1), true));
180	maptabp.add(Segment("tty" , MTTY_BASE , MTTY_SIZE , IntTab(0, 2), false));
181	maptabp.add(Segment("xicu" , XICU_BASE , XICU_SIZE , IntTab(0, 3), false));
182	maptabp.add(Segment("dma", MDMA_BASE, MDMA_SIZE, IntTab(0, 4), false));
183	maptabp.add(Segment("simh", EXIT_BASE, EXIT_SIZE, IntTab(0, 5), false));
184
185	std::cout << maptabp << std::endl;
186
187	soclib::common::MappingTable maptabx(32, IntTab(8), IntTab(8), 0x30000000);
188	maptabx.add(Segment("xram" , MEMC_BASE , MEMC_SIZE , IntTab(0), false));
189
190
191	std::cout << maptabx << std::endl;
192
193	// Signals
194
195	sc_clock signal_clk ("clk");
196	sc_signal<bool> signal_resetn("resetn");
197
198	sc_signal<bool> signal_proc0_it0("signal_proc0_it0");
199	sc_signal<bool> signal_proc0_it1("signal_proc0_it1");
200	sc_signal<bool> signal_proc0_it2("signal_proc0_it2");
201	sc_signal<bool> signal_proc0_it3("signal_proc0_it3");
202	sc_signal<bool> signal_proc0_it4("signal_proc0_it4");
203	sc_signal<bool> signal_proc0_it5("signal_proc0_it5");
204
205	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc0
206	("vci_ini_rw_proc0");
207	soclib::caba::VciSignals<vci_param> signal_vci_tty
208	("signal_vci_tty");
209	soclib::caba::VciSignals<vci_param> signal_vci_simh
210	("signal_vci_simh");
211
212	soclib::caba::VciSignals<vci_param> signal_vci_xicu
213	("signal_vci_xicu");
214	soclib::caba::VciSignals<vci_param> signal_vci_dmai
215	("signal_vci_dmai");
216	soclib::caba::VciSignals<vci_param> signal_vci_dmat
217	("signal_vci_dmat");
218	soclib::caba::VciSignals<vci_param> signal_vci_tgt_rom
219	("vci_tgt_rom");
220
221	soclib::caba::VciSignals<vci_param_ext> signal_vci_ixr_memc
222	("vci_ixr_memc");
223	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc
224	("vci_tgt_memc");
225	sc_signal<bool> signal_icu_irq0("signal_icu_irq0");
226	sc_signal<bool> signal_icu_irq1("signal_icu_irq1");
227	sc_signal<bool> signal_icu_irq2("signal_icu_irq2");
228
229	soclib::common::Loader loader("test.elf");
230
231	// init_rw init_c tgt
232	soclib::caba::VciCcVCacheWrapper<vci_param, dspin_cmd_width, dspin_rsp_width, proc_iss > *proc0;
233	soclib::caba::VciSimpleRam<vci_param> *rom;
234	soclib::caba::VciSimpleRam<vci_param_ext> *xram;
235	soclib::caba::VciMemCache<vci_param, vci_param_ext, dspin_rsp_width, dspin_cmd_width> *memc;
236	soclib::caba::VciXicu<vci_param> *vcixicu;
237	soclib::caba::VciMultiTty<vci_param> *vcitty;
238	soclib::caba::VciSimhelper<vci_param> *vcisimh;
239	soclib::caba::VciMultiDma<vci_param> *vcidma;
240	DspinLocalCrossbar<dspin_cmd_width>* xbar_cmd_d;
241	DspinLocalCrossbar<dspin_rsp_width>* xbar_rsp_d;
242	DspinLocalCrossbar<dspin_cmd_width>* xbar_m2p_c;
243	DspinLocalCrossbar<dspin_rsp_width>* xbar_p2m_c;
244	DspinLocalCrossbar<dspin_cmd_width>* xbar_clack_c;
245
246	proc0 = new soclib::caba::VciCcVCacheWrapper<vci_param, dspin_cmd_width, dspin_rsp_width, proc_iss >
247	("proc0", 0, maptabp, IntTab(0, 0), 0,
248	8,8,8,8,4,64,16,4,64,16,4, 4, 0, 0, max_frozen, from_cycle, trace_ok);
249	VciDspinInitiatorWrapper<vci_param, dspin_cmd_width, dspin_rsp_width>
250	wi_proc0("wi_proc0", srcid_width);
251
252	vcisimh = new soclib::caba::VciSimhelper<vci_param>
253	("vcisimh", IntTab(0, 5), maptabp);
254	VciDspinTargetWrapper<vci_param, dspin_cmd_width, dspin_rsp_width>
255	wt_simh("wt_simh", srcid_width);
256
257	vcidma = new soclib::caba::VciMultiDma<vci_param>
258	("vcidma", maptabp, IntTab(0, 1), IntTab(0, 4), 64, 1);//(1<<(vci_param::K-1)));
259	VciDspinInitiatorWrapper<vci_param, dspin_cmd_width, dspin_rsp_width>
260	wi_dma("wi_dma", srcid_width);
261	VciDspinTargetWrapper<vci_param, dspin_cmd_width, dspin_rsp_width>
262	wt_dma("wt_dma", srcid_width);
263
264	vcitty = new soclib::caba::VciMultiTty<vci_param>
265	("vcitty", IntTab(0, 2), maptabp, "vcitty0", NULL);
266	VciDspinTargetWrapper<vci_param, dspin_cmd_width, dspin_rsp_width>
267	wt_tty("wt_tty", srcid_width);
268
269	rom = new soclib::caba::VciSimpleRam<vci_param>
270	("rom", IntTab(0, 1), maptabp, loader);
271	VciDspinTargetWrapper<vci_param, dspin_cmd_width, dspin_rsp_width>
272	wt_rom("wt_rom", srcid_width);
273
274	vcixicu = new soclib::caba::VciXicu<vci_param>
275	("vcixicu", maptabp, IntTab(0, 3), 4 /* npti /, 2 / nhwi /, 4 / nwti /, 6 / nirq */);
276	VciDspinTargetWrapper<vci_param, dspin_cmd_width, dspin_rsp_width>
277	wt_xicu("wt_xicu", srcid_width);
278
279	xram = new soclib::caba::VciSimpleRam<vci_param_ext>
280	("xram", IntTab(0), maptabx, loader);
281	memc = new soclib::caba::VciMemCache<vci_param, vci_param_ext, dspin_rsp_width, dspin_cmd_width>
282	("memc",maptabp,maptabx,IntTab(0),IntTab(0, 0), 0, 0,16,256,16, 3, 4096, 8, 8, 8, from_cycle, trace_ok);
283	VciDspinTargetWrapper<vci_param, dspin_cmd_width, dspin_rsp_width>
284	wt_memc("wt_memc", srcid_width);
285
286	xbar_cmd_d = new DspinLocalCrossbar<dspin_cmd_width>(
287	"xbar_cmd_d",
288	maptabp, // mapping table
289	0, 0, // cluster coordinates
290	0, 0, srcid_width,
291	2, // number of local of sources
292	6, // number of local dests
293	2, 2, // fifo depths
294	true, // CMD
295	true, // use local routing table
296	false ); // no broadcast
297
298	xbar_rsp_d = new DspinLocalCrossbar<dspin_rsp_width>(
299	"xbar_rsp_d",
300	maptabp, // mapping table
301	0, 0, // cluster coordinates
302	0, 0, srcid_width,
303	6, // number of local sources
304	2, // number of local dests
305	2, 2, // fifo depths
306	false, // RSP
307	false, // don't use local routing table
308	false ); // no broadcast
309
310	xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>(
311	"xbar_m2p_c", maptabp, 0, 0, 0, 0, srcid_width,
312	1, 1, 2, 2, true, false, true);
313	xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>(
314	"xbar_p2m_c", maptabp, 0, 0, 0, 0, 0,
315	1, 1, 2, 2, false, false, false);
316	xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
317	"xbar_clack_c", maptabp, 0, 0, 0, 0, srcid_width,
318	1, 1, 1, 1, true, false, false);
319	#ifdef VCI_LOGGER_ON_L1
320	soclib::caba::VciLogger<vci_param> vci_logger0("vci_logger0",maptabp);
321	#endif
322	#ifdef VCI_LOGGER_ON_ROM
323	soclib::caba::VciLogger<vci_param> vci_logger1("vci_logger1",maptabp);
324	#endif
325	#ifdef VCI_LOGGER_ON_L1_TGT
326	soclib::caba::VciLogger<vci_param> vci_logger2("vci_logger2",maptabp);
327	#endif
328	proc0->p_clk(signal_clk);
329	proc0->p_resetn(signal_resetn);
330	proc0->p_irq[0](signal_proc0_it0);
331	proc0->p_irq[1](signal_proc0_it1);
332	proc0->p_irq[2](signal_proc0_it2);
333	proc0->p_irq[3](signal_proc0_it3);
334	proc0->p_irq[4](signal_proc0_it4);
335	proc0->p_irq[5](signal_proc0_it5);
336	proc0->p_vci(signal_vci_ini_rw_proc0);
337	proc0->p_dspin_m2p(signal_dspin_m2p_proc[0]);
338	proc0->p_dspin_p2m(signal_dspin_p2m_proc[0]);
339	proc0->p_dspin_clack(signal_dspin_clack_proc[0]);
340	wi_proc0.p_clk(signal_clk);
341	wi_proc0.p_resetn(signal_resetn);
342	wi_proc0.p_vci(signal_vci_ini_rw_proc0);
343	wi_proc0.p_dspin_cmd(signal_dspin_cmd_proc0_i);
344	wi_proc0.p_dspin_rsp(signal_dspin_rsp_proc0_i);
345
346	rom->p_clk(signal_clk);
347	rom->p_resetn(signal_resetn);
348	rom->p_vci(signal_vci_tgt_rom);
349	wt_rom.p_clk(signal_clk);
350	wt_rom.p_resetn(signal_resetn);
351	wt_rom.p_vci(signal_vci_tgt_rom);
352	wt_rom.p_dspin_cmd(signal_dspin_cmd_rom_t);
353	wt_rom.p_dspin_rsp(signal_dspin_rsp_rom_t);
354
355	vcixicu->p_resetn(signal_resetn);
356	vcixicu->p_clk(signal_clk);
357	vcixicu->p_vci(signal_vci_xicu);
358	vcixicu->p_hwi[0](signal_icu_irq0);
359	vcixicu->p_hwi[1](signal_icu_irq1);
360	vcixicu->p_hwi[2](signal_icu_irq2);
361	vcixicu->p_irq[0](signal_proc0_it0);
362	vcixicu->p_irq[1](signal_proc0_it1);
363	vcixicu->p_irq[2](signal_proc0_it2);
364	vcixicu->p_irq[3](signal_proc0_it3);
365	vcixicu->p_irq[4](signal_proc0_it4);
366	vcixicu->p_irq[5](signal_proc0_it5);
367	wt_xicu.p_clk(signal_clk);
368	wt_xicu.p_resetn(signal_resetn);
369	wt_xicu.p_vci(signal_vci_xicu);
370	wt_xicu.p_dspin_cmd(signal_dspin_cmd_xicu_t);
371	wt_xicu.p_dspin_rsp(signal_dspin_rsp_xicu_t);
372
373	vcidma->p_clk(signal_clk);
374	vcidma->p_resetn(signal_resetn);
375	vcidma->p_irq[0](signal_icu_irq1);
376	vcidma->p_vci_target(signal_vci_dmat);
377	vcidma->p_vci_initiator(signal_vci_dmai);
378	wt_dma.p_clk(signal_clk);
379	wt_dma.p_resetn(signal_resetn);
380	wt_dma.p_vci(signal_vci_dmat);
381	wt_dma.p_dspin_cmd(signal_dspin_cmd_dma_t);
382	wt_dma.p_dspin_rsp(signal_dspin_rsp_dma_t);
383	wi_dma.p_clk(signal_clk);
384	wi_dma.p_resetn(signal_resetn);
385	wi_dma.p_vci(signal_vci_dmai);
386	wi_dma.p_dspin_cmd(signal_dspin_cmd_dma_i);
387	wi_dma.p_dspin_rsp(signal_dspin_rsp_dma_i);
388
389
390	#ifdef VCI_LOGGER_ON_L1
391	vci_logger0.p_clk(signal_clk);
392	vci_logger0.p_resetn(signal_resetn);
393	vci_logger0.p_vci(signal_vci_ini_rw_proc0);
394	#endif
395
396	#ifdef VCI_LOGGER_ON_ROM
397	vci_logger1.p_clk(signal_clk);
398	vci_logger1.p_resetn(signal_resetn);
399	vci_logger1.p_vci(signal_vci_tgt_rom);
400	#endif
401
402	#ifdef VCI_LOGGER_ON_L1_TGT
403	vci_logger2.p_clk(signal_clk);
404	vci_logger2.p_resetn(signal_resetn);
405	#endif
406
407	vcitty->p_clk(signal_clk);
408	vcitty->p_resetn(signal_resetn);
409	vcitty->p_vci(signal_vci_tty);
410	vcitty->p_irq[0](signal_icu_irq0);
411	wt_tty.p_clk(signal_clk);
412	wt_tty.p_resetn(signal_resetn);
413	wt_tty.p_vci(signal_vci_tty);
414	wt_tty.p_dspin_cmd(signal_dspin_cmd_tty_t);
415	wt_tty.p_dspin_rsp(signal_dspin_rsp_tty_t);
416
417	vcisimh->p_clk(signal_clk);
418	vcisimh->p_resetn(signal_resetn);
419	vcisimh->p_vci(signal_vci_simh);
420	wt_simh.p_clk(signal_clk);
421	wt_simh.p_resetn(signal_resetn);
422	wt_simh.p_vci(signal_vci_simh);
423	wt_simh.p_dspin_cmd(signal_dspin_cmd_simh_t);
424	wt_simh.p_dspin_rsp(signal_dspin_rsp_simh_t);
425
426	memc->p_clk(signal_clk);
427	memc->p_resetn(signal_resetn);
428	memc->p_irq(signal_icu_irq2);
429	memc->p_vci_tgt(signal_vci_tgt_memc);
430	memc->p_dspin_p2m(signal_dspin_p2m_memc);
431	memc->p_dspin_m2p(signal_dspin_m2p_memc);
432	memc->p_dspin_clack(signal_dspin_clack_memc);
433	memc->p_vci_ixr(signal_vci_ixr_memc);
434	wt_memc.p_clk(signal_clk);
435	wt_memc.p_resetn(signal_resetn);
436	wt_memc.p_vci(signal_vci_tgt_memc);
437	wt_memc.p_dspin_cmd(signal_dspin_cmd_memc_t);
438	wt_memc.p_dspin_rsp(signal_dspin_rsp_memc_t);
439
440	xram->p_clk(signal_clk);
441	xram->p_resetn(signal_resetn);
442	xram->p_vci(signal_vci_ixr_memc);
443
444
445	xbar_cmd_d->p_clk(signal_clk);
446	xbar_cmd_d->p_resetn(signal_resetn);
447	xbar_rsp_d->p_clk(signal_clk);
448	xbar_rsp_d->p_resetn(signal_resetn);
449	xbar_m2p_c->p_clk(signal_clk);
450	xbar_m2p_c->p_resetn(signal_resetn);
451	xbar_clack_c->p_clk(signal_clk);
452	xbar_clack_c->p_resetn(signal_resetn);
453	xbar_p2m_c->p_clk(signal_clk);
454	xbar_p2m_c->p_resetn(signal_resetn);
455
456	xbar_cmd_d->p_global_out(signal_dspin_cmd_l2g_c);
457	xbar_cmd_d->p_global_in(signal_dspin_cmd_g2l_c);
458	xbar_rsp_d->p_global_out(signal_dspin_rsp_l2g_c);
459	xbar_rsp_d->p_global_in(signal_dspin_rsp_g2l_c);
460	xbar_m2p_c->p_global_out(signal_dspin_m2p_l2g_c);
461	xbar_m2p_c->p_global_in(signal_dspin_m2p_g2l_c);
462	xbar_clack_c->p_global_out(signal_dspin_clack_l2g_c);
463	xbar_clack_c->p_global_in(signal_dspin_clack_g2l_c);
464	xbar_p2m_c->p_global_out(signal_dspin_p2m_l2g_c);
465	xbar_p2m_c->p_global_in(signal_dspin_p2m_g2l_c);
466
467	xbar_cmd_d->p_local_in[0](signal_dspin_cmd_proc0_i);
468	xbar_cmd_d->p_local_in[1](signal_dspin_cmd_dma_i);
469	xbar_cmd_d->p_local_out[0](signal_dspin_cmd_memc_t);
470	xbar_cmd_d->p_local_out[1](signal_dspin_cmd_rom_t);
471	xbar_cmd_d->p_local_out[2](signal_dspin_cmd_tty_t);
472	xbar_cmd_d->p_local_out[3](signal_dspin_cmd_xicu_t);
473	xbar_cmd_d->p_local_out[4](signal_dspin_cmd_dma_t);
474	xbar_cmd_d->p_local_out[5](signal_dspin_cmd_simh_t);
475
476	xbar_rsp_d->p_local_out[0](signal_dspin_rsp_proc0_i);
477	xbar_rsp_d->p_local_out[1](signal_dspin_rsp_dma_i);
478	xbar_rsp_d->p_local_in[0](signal_dspin_rsp_memc_t);
479	xbar_rsp_d->p_local_in[1](signal_dspin_rsp_rom_t);
480	xbar_rsp_d->p_local_in[2](signal_dspin_rsp_tty_t);
481	xbar_rsp_d->p_local_in[3](signal_dspin_rsp_xicu_t);
482	xbar_rsp_d->p_local_in[4](signal_dspin_rsp_dma_t);
483	xbar_rsp_d->p_local_in[5](signal_dspin_rsp_simh_t);
484
485	xbar_m2p_c->p_local_in[0](signal_dspin_m2p_memc);
486	xbar_m2p_c->p_local_out[0](signal_dspin_m2p_proc[0]);
487
488	xbar_clack_c->p_local_in[0](signal_dspin_clack_memc);
489	xbar_clack_c->p_local_out[0](signal_dspin_clack_proc[0]);
490
491	xbar_p2m_c->p_local_out[0](signal_dspin_p2m_memc);
492	xbar_p2m_c->p_local_in[0](signal_dspin_p2m_proc[0]);
493
494	sc_start(sc_core::sc_time(0, SC_NS));
495	signal_resetn = false;
496
497	sc_start(sc_core::sc_time(1, SC_NS));
498	signal_resetn = true;
499
500
501	for ( size_t n=1 ; n<ncycles ; n++ )
502	{
503	if ( trace_ok and (n > from_cycle) )
504	{
505	std::cout << "****************** cycle " << std::dec << n
506	<< " ************************************************" << std::endl;
507	proc0->print_trace();
508	memc->print_trace();
509	signal_vci_ini_rw_proc0.print_trace("signal_vci_ini_rw_proc0");
510	signal_vci_tgt_memc.print_trace("signal_vci_tgt_memc");
511	signal_vci_ixr_memc.print_trace("signal_vci_ixr_memc");
512	}
513	sc_start(sc_core::sc_time(1, SC_NS));
514	}
515	return EXIT_FAILURE;
516
517	}
518
519	int sc_main (int argc, char *argv[])
520	{
521	try {
522	return _main(argc, argv);
523	} catch (std::exception &e) {
524	std::cout << e.what() << std::endl;
525	} catch (...) {
526	std::cout << "Unknown exception occured" << std::endl;
527	throw;
528	}
529	return 1;
530	}
531

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source: trunk/platforms/tsar_mono_mmu/top.cpp @ 877

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