[117] | 1 | ///////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsarv4_dspin_generic_32_top.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : november 5 2010 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ///////////////////////////////////////////////////////////////////////// |
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| 8 | // This file define a generic TSAR architecture without virtual memory. |
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| 9 | // - It uses the virtual_dspin network as global interconnect |
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| 10 | // - It uses the vci_local_ring_fast as local interconnect |
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| 11 | // - It uses the vci_cc_xcache (No MMU) |
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| 12 | // The physical address space is 32 bits. |
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| 13 | // The number of clusters cannot be larger than 256. |
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| 14 | // The three parameters are |
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| 15 | // - xmax : number of clusters in a row |
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| 16 | // - ymax : number of clusters in a column |
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| 17 | // - nprocs : number of processor per cluster |
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| 18 | // |
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| 19 | // Each cluster contains nprocs processors, one Memory Cache, |
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| 20 | // and one XICU component. |
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| 21 | // The peripherals BDEV, CDMA, FBUF, MTTY and the boot BROM |
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| 22 | // are in the cluster containing address 0xBFC00000. |
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| 23 | // - The bdev_irq is connected to IRQ_IN[0] |
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| 24 | // - The cdma_irq is connected to IRQ_IN[1] |
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| 25 | // - The tty_irq[i] is connected to IRQ_IN[i+2] |
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| 26 | // For all clusters, the XICU component contains nprocs timers. |
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| 27 | // |
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| 28 | // As we target up to 256 clusters, each cluster can contain |
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| 29 | // at most 16 Mbytes (in a 4Gbytes address space). |
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| 30 | // - Each memory cache contains 9 Mbytes. |
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| 31 | // - The Frame buffer contains 2 Mbytes. |
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| 32 | // - The Boot ROM contains 1 Mbytes. |
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| 33 | // |
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| 34 | // General policy for 32 bits address decoding: |
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| 35 | // To simplifly, all segments base addresses are aligned |
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| 36 | // on 1 Mbyte adresses. Therefore the 12 address MSB bits |
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| 37 | // define the target in the direct address space. |
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| 38 | // In these 12 bits, the (x_width + y_width) MSB bits define |
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| 39 | // the cluster index, and the 4 LSB bits define the local index: |
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| 40 | // |
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| 41 | // | X_ID | Y_ID |---| L_ID | OFFSET | |
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| 42 | // |x_width|y_width|---| 4 | 20 | |
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| 43 | ///////////////////////////////////////////////////////////////////////// |
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| 44 | |
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| 45 | #include <systemc> |
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| 46 | #include <sys/time.h> |
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| 47 | #include <iostream> |
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| 48 | #include <sstream> |
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| 49 | #include <cstdlib> |
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| 50 | #include <cstdarg> |
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| 51 | |
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| 52 | #include "mapping_table.h" |
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| 53 | #include "mips32.h" |
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| 54 | #include "vci_simple_ram.h" |
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| 55 | #include "vci_multi_tty.h" |
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| 56 | #include "vci_mem_cache_v4.h" |
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| 57 | #include "vci_cc_xcache_wrapper_v4.h" |
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| 58 | #include "vci_xicu.h" |
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| 59 | #include "vci_vgmn.h" |
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| 60 | #include "vci_local_ring_fast.h" |
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| 61 | #include "virtual_dspin_router.h" |
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| 62 | #include "vci_framebuffer.h" |
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| 63 | #include "vci_dma_tsar_v2.h" |
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| 64 | #include "vci_block_device_tsar_v2.h" |
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| 65 | #include "gdbserver.h" |
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| 66 | |
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| 67 | #define SECTOR_SIZE 2048 |
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| 68 | |
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| 69 | #define FBUF_XSIZE 960 |
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| 70 | #define FBUF_YSIZE 960 |
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| 71 | |
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| 72 | #define N_TTYS 4 |
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| 73 | |
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| 74 | ////////////////////////////////////////////// |
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| 75 | // segments definition in direct space. |
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| 76 | // There is 16 Mbytes address space per cluster. |
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| 77 | // The 8 MSB bits define the cluster index (x,y), |
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| 78 | // even if the number of clusters is less than 256. |
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| 79 | // Each memory cache contains up to 9 Mbytes. |
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| 80 | // There is one MEMC segment and one XICU segment per cluster |
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| 81 | // The peripherals BDEV, FBUF, MTTY, CDMA and the boot BROM |
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| 82 | // are mapped in cluster containing address 0xBFC00000 |
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| 83 | |
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| 84 | #define MEMC_BASE 0x00000000 |
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| 85 | #define MEMC_SIZE 0x00900000 |
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| 86 | |
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| 87 | #define XICU_BASE 0x00900000 |
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| 88 | #define XICU_SIZE 0x00001000 |
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| 89 | |
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| 90 | #define FBUF_BASE 0xBFA00000 |
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| 91 | #define FBUF_SIZE 0x00200000 |
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| 92 | |
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| 93 | #define BROM_BASE 0xBFC00000 |
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| 94 | #define BROM_SIZE 0x00100000 |
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| 95 | |
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| 96 | #define BDEV_BASE 0xBFD00000 |
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| 97 | #define BDEV_SIZE 0x00000100 |
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| 98 | |
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| 99 | #define MTTY_BASE 0xBFE00000 |
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| 100 | #define MTTY_SIZE 0x00000100 |
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| 101 | |
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| 102 | #define CDMA_BASE 0xBFF00000 |
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| 103 | #define CDMA_SIZE 0x00000100 |
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| 104 | |
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| 105 | /////////////////////////////////////////////////////////// |
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| 106 | // TGTID & SRCID definition in direct space |
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| 107 | // For all components: global TGTID = global SRCID = cluster_index |
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| 108 | // For processors, the local SRCID is between 0 & nprocs-1 |
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| 109 | |
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| 110 | #define MEMC_TGTID 0 |
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| 111 | #define XICU_TGTID 1 |
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| 112 | #define FBUF_TGTID 2 |
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| 113 | #define MTTY_TGTID 3 |
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| 114 | #define BROM_TGTID 4 |
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| 115 | #define BDEV_TGTID 5 |
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| 116 | #define CDMA_TGTID 6 |
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| 117 | |
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| 118 | #define PROC_SRCID 0 |
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| 119 | #define BDEV_SRCID nprocs |
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| 120 | #define CDMA_SRCID (nprocs+1) |
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| 121 | |
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| 122 | //////////////////////////////////////////////////////// |
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| 123 | // Local TGTID & SRCID definition in coherence space |
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| 124 | // (The global TGTID & SRCID is the cluster index) |
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| 125 | // For MEMC, the local SRCID is 0 |
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| 126 | // For processors, the local SRCID is between 1 & nprocs |
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| 127 | |
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| 128 | ///////////////////////// |
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| 129 | // Router ports index |
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| 130 | |
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| 131 | #define NORTH 0 |
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| 132 | #define SOUTH 1 |
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| 133 | #define EAST 2 |
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| 134 | #define WEST 3 |
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| 135 | #define LOCAL 4 |
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| 136 | |
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| 137 | /////////////////////////////////// |
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| 138 | // flit widths for the DSPIN network |
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| 139 | |
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| 140 | #define cmd_width 40 |
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| 141 | #define rsp_width 33 |
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| 142 | |
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| 143 | ////////////////// |
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| 144 | // VCI format |
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| 145 | |
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| 146 | #define cell_width 4 |
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| 147 | #define address_width 32 |
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| 148 | #define plen_width 8 |
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| 149 | #define error_width 1 |
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| 150 | #define clen_width 1 |
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| 151 | #define rflag_width 1 |
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| 152 | #define srcid_width 14 |
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| 153 | #define pktid_width 4 |
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| 154 | #define trdid_width 4 |
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| 155 | #define wrplen_width 1 |
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| 156 | |
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| 157 | // cluster index (computed from x,y coordinates) |
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| 158 | #define cluster(x,y) (y + ymax*x) |
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| 159 | |
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| 160 | ///////////////////////////////// |
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| 161 | int _main(int argc, char *argv[]) |
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| 162 | { |
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| 163 | using namespace sc_core; |
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| 164 | using namespace soclib::caba; |
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| 165 | using namespace soclib::common; |
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| 166 | |
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| 167 | char soft_name[128] = "undefined_binary_file"; // pathname to binary code |
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| 168 | char disk_name[128] = "undefined_disk_image"; // pathname to the disk image |
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| 169 | size_t ncycles = 1000000000; // simulated cycles |
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| 170 | size_t xmax = 2; // number of clusters in a row |
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| 171 | size_t ymax = 2; // number of clusters in a column |
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| 172 | size_t nprocs = 1; // number of processors per cluster |
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| 173 | bool debug_ok = false; // debug activated |
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| 174 | size_t from_cycle = 0; // debug start cycle |
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| 175 | size_t to_cycle = 1000000000; // debug end cycle |
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| 176 | |
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| 177 | ////////////// command line arguments ////////////////////// |
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| 178 | if (argc > 1) |
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| 179 | { |
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| 180 | for( int n=1 ; n<argc ; n=n+2 ) |
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| 181 | { |
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| 182 | if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) ) |
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| 183 | { |
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| 184 | ncycles = atoi(argv[n+1]); |
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| 185 | } |
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| 186 | else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) ) |
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| 187 | { |
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| 188 | nprocs = atoi(argv[n+1]); |
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| 189 | assert( (nprocs <= 8) && "The number of processors per cluster cannot be larger than 8"); |
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| 190 | } |
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| 191 | else if( (strcmp(argv[n],"-XMAX") == 0) && (n+1<argc) ) |
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| 192 | { |
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| 193 | xmax = atoi(argv[n+1]); |
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| 194 | assert( ((xmax >= 2) && (xmax <= 16)) |
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| 195 | && "The XMAX parameter (number of clusters in a row) must be in the range [2,16]" ); |
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| 196 | } |
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| 197 | else if( (strcmp(argv[n],"-YMAX") == 0) && (n+1<argc) ) |
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| 198 | { |
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| 199 | ymax = atoi(argv[n+1]); |
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| 200 | assert( ((ymax >= 2) && (ymax <= 16)) |
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| 201 | && "The YMAX parameter (number of clusters in a column) must be in the range [2,16]" ); |
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| 202 | } |
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| 203 | else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ) |
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| 204 | { |
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| 205 | strcpy(soft_name, argv[n+1]); |
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| 206 | } |
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| 207 | else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) |
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| 208 | { |
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| 209 | strcpy(disk_name, argv[n+1]); |
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| 210 | } |
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| 211 | else if( (strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) |
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| 212 | { |
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| 213 | debug_ok = true; |
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| 214 | from_cycle = atoi(argv[n+1]); |
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| 215 | } |
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| 216 | else if( (strcmp(argv[n],"-TOCYCLE") == 0) && (n+1<argc) ) |
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| 217 | { |
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| 218 | to_cycle = atoi(argv[n+1]); |
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| 219 | } |
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| 220 | else |
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| 221 | { |
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| 222 | std::cout << " Arguments on the command line are (key,value) couples." << std::endl; |
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| 223 | std::cout << " The order is not important." << std::endl; |
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| 224 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
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| 225 | std::cout << " -SOFT elf_file_name" << std::endl; |
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| 226 | std::cout << " -DISK disk_image_file_name" << std::endl; |
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| 227 | std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; |
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| 228 | std::cout << " -NPROCS number_of_processors_per_cluster" << std::endl; |
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| 229 | std::cout << " -XMAX number_of_clusters_in_a_row" << std::endl; |
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| 230 | std::cout << " -YMAX number_of_clusters_in_a_column" << std::endl; |
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| 231 | std::cout << " -DEBUG debug_start_cycle" << std::endl; |
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| 232 | std::cout << " -TOCYCLE debug_end_cycle" << std::endl; |
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| 233 | exit(0); |
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| 234 | } |
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| 235 | } |
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| 236 | } |
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| 237 | |
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| 238 | std::cout << std::endl << "*********** TSAR ARCHITECTURE **************" << std::endl |
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| 239 | << " - Interconnect = DSPIN & RING" << std::endl |
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| 240 | << " - Number of clusters = " << xmax << " * " << ymax << std::endl |
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| 241 | << " - Number of processors per cluster = " << nprocs << std::endl |
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| 242 | << "**********************************************" << std::endl |
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| 243 | << std::endl; |
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| 244 | |
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| 245 | // Define VCI parameters |
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| 246 | typedef soclib::caba::VciParams<cell_width, |
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| 247 | plen_width, |
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| 248 | address_width, |
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| 249 | error_width, |
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| 250 | clen_width, |
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| 251 | rflag_width, |
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| 252 | srcid_width, |
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| 253 | pktid_width, |
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| 254 | trdid_width, |
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| 255 | wrplen_width> vci_param; |
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| 256 | |
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| 257 | size_t cluster_io_index; |
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| 258 | size_t x_width; |
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| 259 | size_t y_width; |
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| 260 | |
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| 261 | if (xmax == 2) x_width = 1; |
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| 262 | else if (xmax <= 4) x_width = 2; |
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| 263 | else if (xmax <= 8) x_width = 3; |
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| 264 | else x_width = 4; |
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| 265 | |
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| 266 | if (ymax == 2) y_width = 1; |
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| 267 | else if (ymax <= 4) y_width = 2; |
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| 268 | else if (ymax <= 8) y_width = 3; |
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| 269 | else y_width = 4; |
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| 270 | |
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| 271 | cluster_io_index = 0xBF >> (8 - x_width - y_width); |
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| 272 | |
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| 273 | ///////////////////// |
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| 274 | // Mapping Tables |
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| 275 | ///////////////////// |
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| 276 | |
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| 277 | // direct network |
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| 278 | MappingTable maptabd(address_width, |
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| 279 | IntTab(x_width + y_width, 12 - x_width - y_width), |
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| 280 | IntTab(x_width + y_width, srcid_width - x_width - y_width), |
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| 281 | 0x00F00000); |
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| 282 | for ( size_t x = 0 ; x < xmax ; x++) |
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| 283 | { |
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| 284 | for ( size_t y = 0 ; y < ymax ; y++) |
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| 285 | { |
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| 286 | sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); |
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| 287 | std::ostringstream sm; |
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| 288 | sm << "d_seg_memc_" << x << "_" << y; |
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| 289 | maptabd.add(Segment(sm.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true)); |
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| 290 | std::ostringstream si; |
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| 291 | si << "d_seg_xicu_" << x << "_" << y; |
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| 292 | maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false)); |
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| 293 | if ( cluster(x,y) == cluster_io_index ) |
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| 294 | { |
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| 295 | maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false)); |
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| 296 | maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false)); |
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| 297 | maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false)); |
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| 298 | maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true)); |
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| 299 | maptabd.add(Segment("d_seg_cdma", CDMA_BASE, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false)); |
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| 300 | } |
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| 301 | } |
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| 302 | } |
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| 303 | std::cout << maptabd << std::endl; |
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| 304 | |
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| 305 | // coherence network |
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| 306 | MappingTable maptabc(address_width, |
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| 307 | IntTab(x_width + y_width, 12 - x_width - y_width), |
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| 308 | IntTab(x_width + y_width, srcid_width - x_width - y_width), |
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| 309 | 0xF0000000); |
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| 310 | |
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| 311 | for ( size_t x = 0 ; x < xmax ; x++) |
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| 312 | { |
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| 313 | for ( size_t y = 0 ; y < ymax ; y++) |
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| 314 | { |
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| 315 | sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); |
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| 316 | |
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| 317 | std::ostringstream sm; |
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| 318 | sm << "c_seg_memc_" << x << "_" << y; |
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| 319 | maptabc.add(Segment(sm.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y), nprocs), false)); |
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| 320 | // the segment base and size will be modified |
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| 321 | // when the segmentation of the coherence space will be simplified |
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| 322 | |
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| 323 | if ( cluster(x,y) == cluster_io_index ) |
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| 324 | { |
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| 325 | std::ostringstream sr; |
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| 326 | sr << "c_seg_brom_" << x << "_" << y; |
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| 327 | maptabc.add(Segment(sr.str(), BROM_BASE, BROM_SIZE, IntTab(cluster(x,y), nprocs), false)); |
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| 328 | } |
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| 329 | |
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| 330 | sc_uint<address_width> avoid_collision = 0; |
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| 331 | for ( size_t p = 0 ; p < nprocs ; p++) |
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| 332 | { |
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| 333 | sc_uint<address_width> base = MEMC_SIZE + (p*0x100000) + offset; |
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| 334 | // the following test is to avoid a collision between the c_seg_brom segment |
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| 335 | // and a c_seg_proc segment (all segments base addresses being multiple of 1Mbytes) |
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| 336 | if ( base == BROM_BASE ) avoid_collision = 0x100000; |
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| 337 | std::ostringstream sp; |
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| 338 | sp << "c_seg_proc_" << x << "_" << y << "_" << p; |
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| 339 | maptabc.add(Segment(sp.str(), base + avoid_collision, 0x20, IntTab(cluster(x,y), p), false, |
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| 340 | true, IntTab(cluster(x,y), p))); |
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| 341 | // the two last arguments will be removed |
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| 342 | // when the segmentation of the coherence space will be simplified |
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| 343 | } |
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| 344 | } |
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| 345 | } |
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| 346 | std::cout << maptabc << std::endl; |
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| 347 | |
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| 348 | // external network |
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| 349 | MappingTable maptabx(address_width, IntTab(1), IntTab(10), 0xF0000000); |
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| 350 | for ( size_t x = 0 ; x < xmax ; x++) |
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| 351 | { |
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| 352 | for ( size_t y = 0 ; y < ymax ; y++) |
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| 353 | { |
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| 354 | sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); |
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| 355 | std::ostringstream sx; |
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| 356 | sx << "seg_xram_" << x << "_" << y; |
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| 357 | maptabx.add(Segment(sx.str(), MEMC_BASE + offset, MEMC_SIZE, IntTab(0), false)); |
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| 358 | } |
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| 359 | } |
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| 360 | std::cout << maptabx << std::endl; |
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| 361 | |
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| 362 | //////////////////// |
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| 363 | // Signals |
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| 364 | /////////////////// |
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| 365 | |
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| 366 | sc_clock signal_clk("clk"); |
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| 367 | sc_signal<bool> signal_resetn("resetn"); |
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| 368 | sc_signal<bool> signal_false; |
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| 369 | |
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| 370 | // IRQ signals (one signal per proc) |
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| 371 | |
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[140] | 372 | sc_signal<bool>**** signal_proc_it = |
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| 373 | alloc_elems<sc_signal<bool> >("signal_proc_it", 1,xmax, ymax, nprocs); |
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[117] | 374 | |
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| 375 | sc_signal<bool>* signal_irq_mtty = |
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| 376 | alloc_elems<sc_signal<bool> >("signal_irq_mtty", N_TTYS); |
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| 377 | |
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| 378 | sc_signal<bool> signal_irq_bdev; |
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| 379 | sc_signal<bool> signal_irq_cdma; |
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| 380 | |
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| 381 | // Direct VCI signals |
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| 382 | |
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| 383 | VciSignals<vci_param>*** signal_vci_ini_d_proc = |
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| 384 | alloc_elems<VciSignals<vci_param> >("signal_vci_ini_d_proc", xmax, ymax, nprocs); |
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| 385 | |
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| 386 | VciSignals<vci_param>** signal_vci_tgt_d_memc = |
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| 387 | alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_d_memc", xmax, ymax); |
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| 388 | |
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| 389 | VciSignals<vci_param>** signal_vci_tgt_d_xicu = |
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| 390 | alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_d_xicu", xmax, ymax); |
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| 391 | |
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| 392 | VciSignals<vci_param> signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"); |
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| 393 | VciSignals<vci_param> signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"); |
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| 394 | VciSignals<vci_param> signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"); |
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| 395 | VciSignals<vci_param> signal_vci_tgt_d_cdma("signal_vci_tgt_d_cdma"); |
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| 396 | VciSignals<vci_param> signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"); |
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| 397 | |
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| 398 | VciSignals<vci_param> signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"); |
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| 399 | VciSignals<vci_param> signal_vci_ini_d_cdma("signal_vci_ini_d_cdma"); |
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| 400 | |
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| 401 | // Coherence VCI signals |
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| 402 | |
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| 403 | VciSignals<vci_param>*** signal_vci_ini_c_proc = |
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| 404 | alloc_elems<VciSignals<vci_param> >("signal_vci_ini_c_proc", xmax, ymax, nprocs); |
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| 405 | |
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| 406 | VciSignals<vci_param>*** signal_vci_tgt_c_proc = |
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| 407 | alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_c_proc", xmax, ymax, nprocs); |
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| 408 | |
---|
| 409 | VciSignals<vci_param>** signal_vci_ini_c_memc = |
---|
| 410 | alloc_elems<VciSignals<vci_param> >("signal_vci_ini_c_memc", xmax, ymax); |
---|
| 411 | |
---|
| 412 | VciSignals<vci_param>** signal_vci_tgt_c_memc = |
---|
| 413 | alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_c_memc", xmax, ymax); |
---|
| 414 | |
---|
| 415 | // DSPIN signals between local ring & global interconnects |
---|
| 416 | |
---|
| 417 | DspinSignals<cmd_width>** signal_dspin_cmd_l2g_d = |
---|
| 418 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_cmd_l2g_d", xmax, ymax); |
---|
| 419 | DspinSignals<cmd_width>** signal_dspin_cmd_g2l_d = |
---|
| 420 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_cmd_g2l_d", xmax, ymax); |
---|
| 421 | |
---|
| 422 | DspinSignals<cmd_width>** signal_dspin_cmd_l2g_c = |
---|
| 423 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_cmd_l2g_c", xmax, ymax); |
---|
| 424 | DspinSignals<cmd_width>** signal_dspin_cmd_g2l_c = |
---|
| 425 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_cmd_g2l_c", xmax, ymax); |
---|
| 426 | |
---|
| 427 | DspinSignals<rsp_width>** signal_dspin_rsp_l2g_d = |
---|
| 428 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_rsp_l2g_d", xmax, ymax); |
---|
| 429 | DspinSignals<rsp_width>** signal_dspin_rsp_g2l_d = |
---|
| 430 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_rsp_g2l_d", xmax, ymax); |
---|
| 431 | |
---|
| 432 | DspinSignals<rsp_width>** signal_dspin_rsp_l2g_c = |
---|
| 433 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_rsp_l2g_c", xmax, ymax); |
---|
| 434 | DspinSignals<rsp_width>** signal_dspin_rsp_g2l_c = |
---|
| 435 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_rsp_g2l_c", xmax, ymax); |
---|
| 436 | |
---|
| 437 | // Horizontal inter-clusters DSPIN signals |
---|
| 438 | DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc = |
---|
| 439 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", xmax-1, ymax, 2); |
---|
| 440 | DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec = |
---|
| 441 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", xmax-1, ymax, 2); |
---|
| 442 | DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc = |
---|
| 443 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2); |
---|
| 444 | DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec = |
---|
| 445 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2); |
---|
| 446 | |
---|
| 447 | // Vertical inter-clusters DSPIN signals |
---|
| 448 | DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc = |
---|
| 449 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", xmax, ymax-1, 2); |
---|
| 450 | DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec = |
---|
| 451 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", xmax, ymax-1, 2); |
---|
| 452 | DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc = |
---|
| 453 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2); |
---|
| 454 | DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec = |
---|
| 455 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2); |
---|
| 456 | |
---|
| 457 | // Mesh boundaries DSPIN signals |
---|
| 458 | DspinSignals<cmd_width>**** signal_dspin_false_cmd_in = |
---|
| 459 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", xmax, ymax, 2, 2); |
---|
| 460 | DspinSignals<cmd_width>**** signal_dspin_false_cmd_out = |
---|
| 461 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", xmax, ymax, 2, 2); |
---|
| 462 | DspinSignals<rsp_width>**** signal_dspin_false_rsp_in = |
---|
| 463 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", xmax, ymax, 2, 2); |
---|
| 464 | DspinSignals<rsp_width>**** signal_dspin_false_rsp_out = |
---|
| 465 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", xmax, ymax, 2, 2); |
---|
| 466 | |
---|
| 467 | // Xternal network VCI signals |
---|
| 468 | VciSignals<vci_param> signal_vci_tgt_x_xram("signal_vci_tgt_x_xram"); |
---|
| 469 | VciSignals<vci_param>** signal_vci_ini_x_memc = |
---|
| 470 | alloc_elems<VciSignals<vci_param> >("signal_vci_ini_x_memc", xmax, ymax); |
---|
| 471 | |
---|
| 472 | //////////////////////////// |
---|
| 473 | // Components |
---|
| 474 | //////////////////////////// |
---|
| 475 | |
---|
| 476 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
| 477 | |
---|
| 478 | soclib::common::Loader loader(soft_name); |
---|
| 479 | proc_iss::set_loader(loader); |
---|
| 480 | |
---|
| 481 | // External RAM |
---|
| 482 | VciSimpleRam<vci_param> xram( |
---|
| 483 | "xram", |
---|
| 484 | IntTab(0), |
---|
| 485 | maptabx, |
---|
| 486 | loader); |
---|
| 487 | |
---|
| 488 | // External network |
---|
| 489 | VciVgmn<vci_param> xnoc( |
---|
| 490 | "xnoc", |
---|
| 491 | maptabx, |
---|
| 492 | xmax*ymax, |
---|
| 493 | 1, |
---|
| 494 | 2, 2); |
---|
| 495 | |
---|
| 496 | // Peripherals : TTY, Frame Buffer, Block Device, DMA & Boot ROM |
---|
| 497 | VciSimpleRam<vci_param> brom( |
---|
| 498 | "brom", |
---|
| 499 | IntTab(cluster_io_index, BROM_TGTID), |
---|
| 500 | maptabd, |
---|
| 501 | loader); |
---|
| 502 | |
---|
| 503 | VciMultiTty<vci_param> mtty( |
---|
| 504 | "mtty", |
---|
| 505 | IntTab(cluster_io_index, MTTY_TGTID), |
---|
| 506 | maptabd, |
---|
| 507 | "tty0","tty1","tty2","tty3",NULL); |
---|
| 508 | |
---|
| 509 | VciFrameBuffer<vci_param> fbuf( |
---|
| 510 | "fbuf", |
---|
| 511 | IntTab(cluster_io_index, FBUF_TGTID), |
---|
| 512 | maptabd, |
---|
| 513 | FBUF_XSIZE, |
---|
| 514 | FBUF_YSIZE); |
---|
| 515 | |
---|
| 516 | VciBlockDeviceTsarV2<vci_param> bdev( |
---|
| 517 | "bdev", |
---|
| 518 | maptabd, |
---|
| 519 | IntTab(cluster_io_index, BDEV_SRCID), // SRCID_D |
---|
| 520 | IntTab(cluster_io_index, BDEV_TGTID), // TGTID_D |
---|
| 521 | disk_name, |
---|
| 522 | SECTOR_SIZE); |
---|
| 523 | |
---|
| 524 | VciDmaTsarV2<vci_param> cdma( |
---|
| 525 | "cdma", |
---|
| 526 | maptabd, |
---|
| 527 | IntTab(cluster_io_index,CDMA_SRCID), // SRCID_D |
---|
| 528 | IntTab(cluster_io_index,CDMA_TGTID), // TGTID_D |
---|
| 529 | 64); |
---|
| 530 | |
---|
| 531 | // processors (nprocs per cluster) |
---|
| 532 | VciCcXCacheWrapperV4<vci_param, proc_iss> *proc[xmax][ymax][nprocs]; |
---|
| 533 | |
---|
| 534 | for( size_t x = 0 ; x < xmax ; x++ ) |
---|
| 535 | { |
---|
| 536 | for( size_t y = 0 ; y < ymax ; y++ ) |
---|
| 537 | { |
---|
| 538 | for ( size_t p = 0 ; p < nprocs ; p++ ) |
---|
| 539 | { |
---|
| 540 | std::ostringstream sp; |
---|
| 541 | sp << "proc_" << x << "_" << y << "_" << p; |
---|
| 542 | |
---|
| 543 | proc[x][y][p] = new VciCcXCacheWrapperV4<vci_param, proc_iss>( |
---|
| 544 | sp.str().c_str(), |
---|
| 545 | p+nprocs*cluster(x,y), |
---|
| 546 | maptabd, maptabc, |
---|
| 547 | IntTab(cluster(x,y),PROC_SRCID+p), // SRCID_D |
---|
| 548 | IntTab(cluster(x,y),PROC_SRCID+p), // SRCID_C |
---|
| 549 | IntTab(cluster(x,y),PROC_SRCID+p), // TGTID_C |
---|
[140] | 550 | 1,1, |
---|
[134] | 551 | 4,64,16,4,64,16, // Icache and Dcache sizes |
---|
| 552 | 4,8,16); |
---|
[117] | 553 | } |
---|
| 554 | } |
---|
| 555 | } |
---|
| 556 | |
---|
| 557 | // memory caches (one per cluster) |
---|
| 558 | VciMemCacheV4<vci_param>* memc[xmax][ymax]; |
---|
| 559 | |
---|
| 560 | for( size_t x = 0 ; x < xmax ; x++ ) |
---|
| 561 | { |
---|
| 562 | for( size_t y = 0 ; y < ymax ; y++ ) |
---|
| 563 | { |
---|
| 564 | std::ostringstream sm; |
---|
| 565 | sm << "memc_" << x << "_" << y; |
---|
| 566 | memc[x][y] = new VciMemCacheV4<vci_param>( |
---|
| 567 | sm.str().c_str(), |
---|
| 568 | maptabd, maptabc, maptabx, |
---|
| 569 | IntTab(cluster(x,y)), // SRCID_X |
---|
| 570 | IntTab(cluster(x,y), nprocs), // SRCID_C |
---|
| 571 | IntTab(cluster(x,y),MEMC_TGTID), // TGTID_D |
---|
| 572 | IntTab(cluster(x,y), nprocs), // TGTID_C |
---|
| 573 | 16,256,16, // CACHE SIZE |
---|
| 574 | 4096); // HEAP SIZE |
---|
| 575 | } |
---|
| 576 | } |
---|
| 577 | |
---|
| 578 | // XICU (one per cluster) |
---|
| 579 | VciXicu<vci_param>* xicu[xmax][ymax]; |
---|
| 580 | |
---|
| 581 | for( size_t x = 0 ; x < xmax ; x++ ) |
---|
| 582 | { |
---|
| 583 | for( size_t y = 0 ; y < ymax ; y++ ) |
---|
| 584 | { |
---|
| 585 | std::ostringstream si; |
---|
| 586 | si << "xicu_" << x << "_" << y; |
---|
| 587 | size_t nhwi; |
---|
| 588 | if ( cluster(x,y) == cluster_io_index ) nhwi = 2 + N_TTYS; |
---|
| 589 | else nhwi = 0; |
---|
| 590 | xicu[x][y] = new VciXicu<vci_param>( |
---|
| 591 | si.str().c_str(), |
---|
| 592 | maptabd, |
---|
| 593 | IntTab(cluster(x,y), XICU_TGTID), // TGTID_D |
---|
| 594 | nprocs, // number of TIMERS |
---|
| 595 | nhwi, // number of hard IRQs |
---|
| 596 | nprocs, // number of soft IRQs |
---|
| 597 | nprocs); // number of output IRQ lines |
---|
| 598 | } |
---|
| 599 | } |
---|
| 600 | |
---|
| 601 | // Local interconnects : one direct ring & one coherence ring per cluster |
---|
| 602 | VciLocalRingFast<vci_param,cmd_width,rsp_width>* ringd[xmax][ymax]; |
---|
| 603 | VciLocalRingFast<vci_param,cmd_width,rsp_width>* ringc[xmax][ymax]; |
---|
| 604 | |
---|
| 605 | for( size_t x = 0 ; x < xmax ; x++ ) |
---|
| 606 | { |
---|
| 607 | for( size_t y = 0 ; y < ymax ; y++ ) |
---|
| 608 | { |
---|
| 609 | std::ostringstream sd; |
---|
| 610 | sd << "ringd_" << x << "_" << y; |
---|
| 611 | size_t nb_direct_initiators = nprocs; |
---|
| 612 | size_t nb_direct_targets = 2; |
---|
| 613 | if ( cluster(x,y) == cluster_io_index ) |
---|
| 614 | { |
---|
| 615 | nb_direct_initiators = nprocs + 2; |
---|
| 616 | nb_direct_targets = 7; |
---|
| 617 | } |
---|
| 618 | ringd[x][y] = new VciLocalRingFast<vci_param,cmd_width,rsp_width>( |
---|
| 619 | sd.str().c_str(), |
---|
| 620 | maptabd, |
---|
| 621 | IntTab(cluster(x,y)), // cluster index |
---|
| 622 | 4, // wrapper fifo depth |
---|
| 623 | 18, // gateway fifo depth |
---|
| 624 | nb_direct_initiators, // number of initiators |
---|
| 625 | nb_direct_targets); // number of targets |
---|
| 626 | |
---|
| 627 | std::ostringstream sc; |
---|
| 628 | sc << "ringc_" << x << "_" << y; |
---|
| 629 | ringc[x][y] = new VciLocalRingFast<vci_param,cmd_width,rsp_width>( |
---|
| 630 | sc.str().c_str(), |
---|
| 631 | maptabc, |
---|
| 632 | IntTab(cluster(x,y)), // cluster index |
---|
| 633 | 4, // wrapper fifo depth |
---|
| 634 | 18, // gateway fifo depth |
---|
| 635 | nprocs+1, // number of initiators |
---|
| 636 | nprocs+1); // number of targets |
---|
| 637 | } |
---|
| 638 | } |
---|
| 639 | |
---|
| 640 | // Distributed Global Interconnect : one cmd router & one rsp router per cluster |
---|
| 641 | VirtualDspinRouter<cmd_width>* cmdrouter[xmax][ymax]; |
---|
| 642 | VirtualDspinRouter<rsp_width>* rsprouter[xmax][ymax]; |
---|
| 643 | |
---|
| 644 | for ( size_t x = 0 ; x < xmax ; x++ ) |
---|
| 645 | { |
---|
| 646 | for ( size_t y = 0 ; y < ymax ; y++ ) |
---|
| 647 | { |
---|
| 648 | std::ostringstream scmd; |
---|
| 649 | scmd << "cmdrouter_" << x << "_" << y; |
---|
| 650 | cmdrouter[x][y] = new VirtualDspinRouter<cmd_width>( |
---|
| 651 | scmd.str().c_str(), |
---|
| 652 | x,y, // coordinate in the mesh |
---|
| 653 | x_width, y_width, // x & y fields width |
---|
| 654 | 4,4); // input & output fifo depths |
---|
| 655 | |
---|
| 656 | std::ostringstream srsp; |
---|
| 657 | srsp << "rsprouter_" << x << "_" << y; |
---|
| 658 | rsprouter[x][y] = new VirtualDspinRouter<rsp_width>( |
---|
| 659 | srsp.str().c_str(), |
---|
| 660 | x,y, // coordinates in mesh |
---|
| 661 | x_width, y_width, // x & y fields width |
---|
| 662 | 4,4); // input & output fifo depths |
---|
| 663 | } |
---|
| 664 | } |
---|
| 665 | |
---|
| 666 | /////////////////////////////////////////////////////////////// |
---|
| 667 | // Net-list |
---|
| 668 | /////////////////////////////////////////////////////////////// |
---|
| 669 | |
---|
| 670 | // External Ram (one instance) |
---|
| 671 | xram.p_clk (signal_clk); |
---|
| 672 | xram.p_resetn (signal_resetn); |
---|
| 673 | xram.p_vci (signal_vci_tgt_x_xram); |
---|
| 674 | |
---|
| 675 | // External Network (one instance) |
---|
| 676 | xnoc.p_clk (signal_clk); |
---|
| 677 | xnoc.p_resetn (signal_resetn); |
---|
| 678 | xnoc.p_to_target[0] (signal_vci_tgt_x_xram); |
---|
| 679 | for ( size_t x = 0 ; x < xmax ; x++ ) |
---|
| 680 | { |
---|
| 681 | for ( size_t y = 0 ; y < ymax ; y++ ) |
---|
| 682 | { |
---|
| 683 | xnoc.p_to_initiator[cluster(x,y)] (signal_vci_ini_x_memc[x][y]); |
---|
| 684 | } |
---|
| 685 | } |
---|
| 686 | |
---|
| 687 | // Distributed components (in clusters) |
---|
| 688 | |
---|
| 689 | for ( size_t x = 0 ; x < xmax ; x++ ) |
---|
| 690 | { |
---|
| 691 | for ( size_t y = 0 ; y < ymax ; y++ ) |
---|
| 692 | { |
---|
| 693 | // cmd DSPIN router |
---|
| 694 | cmdrouter[x][y]->p_clk (signal_clk); |
---|
| 695 | cmdrouter[x][y]->p_resetn (signal_resetn); |
---|
| 696 | cmdrouter[x][y]->p_out[0][LOCAL] (signal_dspin_cmd_g2l_d[x][y]); |
---|
| 697 | cmdrouter[x][y]->p_out[1][LOCAL] (signal_dspin_cmd_g2l_c[x][y]); |
---|
| 698 | cmdrouter[x][y]->p_in[0][LOCAL] (signal_dspin_cmd_l2g_d[x][y]); |
---|
| 699 | cmdrouter[x][y]->p_in[1][LOCAL] (signal_dspin_cmd_l2g_c[x][y]); |
---|
| 700 | |
---|
| 701 | // rsp DSPIN router |
---|
| 702 | rsprouter[x][y]->p_clk (signal_clk); |
---|
| 703 | rsprouter[x][y]->p_resetn (signal_resetn); |
---|
| 704 | rsprouter[x][y]->p_out[0][LOCAL] (signal_dspin_rsp_g2l_d[x][y]); |
---|
| 705 | rsprouter[x][y]->p_out[1][LOCAL] (signal_dspin_rsp_g2l_c[x][y]); |
---|
| 706 | rsprouter[x][y]->p_in[0][LOCAL] (signal_dspin_rsp_l2g_d[x][y]); |
---|
| 707 | rsprouter[x][y]->p_in[1][LOCAL] (signal_dspin_rsp_l2g_c[x][y]); |
---|
| 708 | |
---|
| 709 | // direct ring |
---|
| 710 | ringd[x][y]->p_clk (signal_clk); |
---|
| 711 | ringd[x][y]->p_resetn (signal_resetn); |
---|
| 712 | ringd[x][y]->p_gate_cmd_out (signal_dspin_cmd_l2g_d[x][y]); |
---|
| 713 | ringd[x][y]->p_gate_cmd_in (signal_dspin_cmd_g2l_d[x][y]); |
---|
| 714 | ringd[x][y]->p_gate_rsp_out (signal_dspin_rsp_l2g_d[x][y]); |
---|
| 715 | ringd[x][y]->p_gate_rsp_in (signal_dspin_rsp_g2l_d[x][y]); |
---|
| 716 | ringd[x][y]->p_to_target[MEMC_TGTID] (signal_vci_tgt_d_memc[x][y]); |
---|
| 717 | ringd[x][y]->p_to_target[XICU_TGTID] (signal_vci_tgt_d_xicu[x][y]); |
---|
| 718 | for ( size_t p = 0 ; p < nprocs ; p++ ) |
---|
| 719 | { |
---|
| 720 | ringd[x][y]->p_to_initiator[p] (signal_vci_ini_d_proc[x][y][p]); |
---|
| 721 | } |
---|
| 722 | |
---|
| 723 | // coherence ring |
---|
| 724 | ringc[x][y]->p_clk (signal_clk); |
---|
| 725 | ringc[x][y]->p_resetn (signal_resetn); |
---|
| 726 | ringc[x][y]->p_gate_cmd_out (signal_dspin_cmd_l2g_c[x][y]); |
---|
| 727 | ringc[x][y]->p_gate_cmd_in (signal_dspin_cmd_g2l_c[x][y]); |
---|
| 728 | ringc[x][y]->p_gate_rsp_out (signal_dspin_rsp_l2g_c[x][y]); |
---|
| 729 | ringc[x][y]->p_gate_rsp_in (signal_dspin_rsp_g2l_c[x][y]); |
---|
| 730 | ringc[x][y]->p_to_initiator[nprocs] (signal_vci_ini_c_memc[x][y]); |
---|
| 731 | ringc[x][y]->p_to_target[nprocs] (signal_vci_tgt_c_memc[x][y]); |
---|
| 732 | for ( size_t p = 0 ; p < nprocs ; p++ ) |
---|
| 733 | { |
---|
| 734 | ringc[x][y]->p_to_target[p] (signal_vci_tgt_c_proc[x][y][p]); |
---|
| 735 | ringc[x][y]->p_to_initiator[p] (signal_vci_ini_c_proc[x][y][p]); |
---|
| 736 | } |
---|
| 737 | |
---|
| 738 | // Processors |
---|
| 739 | for ( size_t p = 0 ; p < nprocs ; p++ ) |
---|
| 740 | { |
---|
| 741 | proc[x][y][p]->p_clk (signal_clk); |
---|
| 742 | proc[x][y][p]->p_resetn (signal_resetn); |
---|
| 743 | proc[x][y][p]->p_vci_ini_rw (signal_vci_ini_d_proc[x][y][p]); |
---|
| 744 | proc[x][y][p]->p_vci_ini_c (signal_vci_ini_c_proc[x][y][p]); |
---|
| 745 | proc[x][y][p]->p_vci_tgt (signal_vci_tgt_c_proc[x][y][p]); |
---|
[140] | 746 | proc[x][y][p]->p_irq[0][0] (signal_proc_it[0][x][y][p]); |
---|
[117] | 747 | for ( size_t j = 1 ; j < 6 ; j++ ) |
---|
| 748 | { |
---|
[140] | 749 | proc[x][y][p]->p_irq[0][j] (signal_false); |
---|
[117] | 750 | } |
---|
| 751 | } |
---|
| 752 | |
---|
| 753 | // XICU |
---|
| 754 | xicu[x][y]->p_clk (signal_clk); |
---|
| 755 | xicu[x][y]->p_resetn (signal_resetn); |
---|
| 756 | xicu[x][y]->p_vci (signal_vci_tgt_d_xicu[x][y]); |
---|
| 757 | for ( size_t p = 0 ; p < nprocs ; p++ ) |
---|
| 758 | { |
---|
[140] | 759 | xicu[x][y]->p_irq[p] (signal_proc_it[0][x][y][p]); |
---|
[117] | 760 | } |
---|
| 761 | |
---|
| 762 | // MEMC |
---|
| 763 | memc[x][y]->p_clk (signal_clk); |
---|
| 764 | memc[x][y]->p_resetn (signal_resetn); |
---|
| 765 | memc[x][y]->p_vci_tgt (signal_vci_tgt_d_memc[x][y]); |
---|
| 766 | memc[x][y]->p_vci_ini (signal_vci_ini_c_memc[x][y]); |
---|
| 767 | memc[x][y]->p_vci_tgt_cleanup (signal_vci_tgt_c_memc[x][y]); |
---|
| 768 | memc[x][y]->p_vci_ixr (signal_vci_ini_x_memc[x][y]); |
---|
| 769 | |
---|
| 770 | // I/O peripherals |
---|
| 771 | if ( cluster(x,y) == cluster_io_index ) |
---|
| 772 | { |
---|
| 773 | bdev.p_clk (signal_clk); |
---|
| 774 | bdev.p_resetn (signal_resetn); |
---|
| 775 | bdev.p_irq (signal_irq_bdev); |
---|
| 776 | bdev.p_vci_target (signal_vci_tgt_d_bdev); |
---|
| 777 | bdev.p_vci_initiator (signal_vci_ini_d_bdev); |
---|
| 778 | |
---|
| 779 | cdma.p_clk (signal_clk); |
---|
| 780 | cdma.p_resetn (signal_resetn); |
---|
| 781 | cdma.p_irq (signal_irq_cdma); |
---|
| 782 | cdma.p_vci_target (signal_vci_tgt_d_cdma); |
---|
| 783 | cdma.p_vci_initiator (signal_vci_ini_d_cdma); |
---|
| 784 | |
---|
| 785 | fbuf.p_clk (signal_clk); |
---|
| 786 | fbuf.p_resetn (signal_resetn); |
---|
| 787 | fbuf.p_vci (signal_vci_tgt_d_fbuf); |
---|
| 788 | |
---|
| 789 | brom.p_clk (signal_clk); |
---|
| 790 | brom.p_resetn (signal_resetn); |
---|
| 791 | brom.p_vci (signal_vci_tgt_d_brom); |
---|
| 792 | |
---|
| 793 | mtty.p_clk (signal_clk); |
---|
| 794 | mtty.p_resetn (signal_resetn); |
---|
| 795 | mtty.p_vci (signal_vci_tgt_d_mtty); |
---|
| 796 | for(size_t i=0 ; i<N_TTYS ; i++) |
---|
| 797 | { |
---|
| 798 | mtty.p_irq[i] (signal_irq_mtty[i]); |
---|
| 799 | } |
---|
| 800 | |
---|
| 801 | ringd[x][y]->p_to_target[BROM_TGTID] (signal_vci_tgt_d_brom); |
---|
| 802 | ringd[x][y]->p_to_target[MTTY_TGTID] (signal_vci_tgt_d_mtty); |
---|
| 803 | ringd[x][y]->p_to_target[BDEV_TGTID] (signal_vci_tgt_d_bdev); |
---|
| 804 | ringd[x][y]->p_to_target[FBUF_TGTID] (signal_vci_tgt_d_fbuf); |
---|
| 805 | ringd[x][y]->p_to_target[CDMA_TGTID] (signal_vci_tgt_d_cdma); |
---|
| 806 | |
---|
| 807 | ringd[x][y]->p_to_initiator[BDEV_SRCID] (signal_vci_ini_d_bdev); |
---|
| 808 | ringd[x][y]->p_to_initiator[CDMA_SRCID] (signal_vci_ini_d_cdma); |
---|
| 809 | |
---|
| 810 | xicu[x][y]->p_hwi[0] (signal_irq_bdev); |
---|
| 811 | xicu[x][y]->p_hwi[1] (signal_irq_cdma); |
---|
| 812 | for(size_t i=0 ; i<N_TTYS ; i++) |
---|
| 813 | { |
---|
| 814 | xicu[x][y]->p_hwi[2+i] (signal_irq_mtty[i]); |
---|
| 815 | } |
---|
| 816 | } |
---|
| 817 | } // end for y |
---|
| 818 | } // end for x |
---|
| 819 | |
---|
| 820 | // Inter Clusters horizontal connections |
---|
| 821 | for ( size_t x = 0 ; x < (xmax-1) ; x++ ) |
---|
| 822 | { |
---|
| 823 | for ( size_t y = 0 ; y < ymax ; y++ ) |
---|
| 824 | { |
---|
| 825 | for ( size_t k = 0 ; k < 2 ; k++ ) |
---|
| 826 | { |
---|
| 827 | cmdrouter[x][y]->p_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]); |
---|
| 828 | cmdrouter[x+1][y]->p_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]); |
---|
| 829 | |
---|
| 830 | cmdrouter[x][y]->p_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]); |
---|
| 831 | cmdrouter[x+1][y]->p_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]); |
---|
| 832 | |
---|
| 833 | rsprouter[x][y]->p_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]); |
---|
| 834 | rsprouter[x+1][y]->p_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]); |
---|
| 835 | |
---|
| 836 | rsprouter[x][y]->p_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]); |
---|
| 837 | rsprouter[x+1][y]->p_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]); |
---|
| 838 | } |
---|
| 839 | } |
---|
| 840 | } |
---|
| 841 | |
---|
| 842 | // Inter Clusters vertical connections |
---|
| 843 | for ( size_t y = 0 ; y < (ymax-1) ; y++ ) |
---|
| 844 | { |
---|
| 845 | for ( size_t x = 0 ; x < xmax ; x++ ) |
---|
| 846 | { |
---|
| 847 | for ( size_t k = 0 ; k < 2 ; k++ ) |
---|
| 848 | { |
---|
| 849 | cmdrouter[x][y]->p_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]); |
---|
| 850 | cmdrouter[x][y+1]->p_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]); |
---|
| 851 | |
---|
| 852 | cmdrouter[x][y]->p_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]); |
---|
| 853 | cmdrouter[x][y+1]->p_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]); |
---|
| 854 | |
---|
| 855 | rsprouter[x][y]->p_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]); |
---|
| 856 | rsprouter[x][y+1]->p_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]); |
---|
| 857 | |
---|
| 858 | rsprouter[x][y]->p_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]); |
---|
| 859 | rsprouter[x][y+1]->p_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]); |
---|
| 860 | } |
---|
| 861 | } |
---|
| 862 | } |
---|
| 863 | |
---|
| 864 | // East & West boundary cluster connections |
---|
| 865 | for ( size_t y = 0 ; y < ymax ; y++ ) |
---|
| 866 | { |
---|
| 867 | for ( size_t k = 0 ; k < 2 ; k++ ) |
---|
| 868 | { |
---|
| 869 | cmdrouter[0][y]->p_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][0]); |
---|
| 870 | cmdrouter[0][y]->p_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][0]); |
---|
| 871 | rsprouter[0][y]->p_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][0]); |
---|
| 872 | rsprouter[0][y]->p_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][0]); |
---|
| 873 | |
---|
| 874 | cmdrouter[xmax-1][y]->p_in[k][EAST] (signal_dspin_false_cmd_in[xmax-1][y][k][0]); |
---|
| 875 | cmdrouter[xmax-1][y]->p_out[k][EAST] (signal_dspin_false_cmd_out[xmax-1][y][k][0]); |
---|
| 876 | rsprouter[xmax-1][y]->p_in[k][EAST] (signal_dspin_false_rsp_in[xmax-1][y][k][0]); |
---|
| 877 | rsprouter[xmax-1][y]->p_out[k][EAST] (signal_dspin_false_rsp_out[xmax-1][y][k][0]); |
---|
| 878 | } |
---|
| 879 | } |
---|
| 880 | |
---|
| 881 | // North & South boundary clusters connections |
---|
| 882 | for ( size_t x = 0 ; x < xmax ; x++ ) |
---|
| 883 | { |
---|
| 884 | for ( size_t k = 0 ; k < 2 ; k++ ) |
---|
| 885 | { |
---|
| 886 | cmdrouter[x][0]->p_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][1]); |
---|
| 887 | cmdrouter[x][0]->p_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][1]); |
---|
| 888 | rsprouter[x][0]->p_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][1]); |
---|
| 889 | rsprouter[x][0]->p_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][1]); |
---|
| 890 | |
---|
| 891 | cmdrouter[x][ymax-1]->p_in[k][NORTH] (signal_dspin_false_cmd_in[x][ymax-1][k][1]); |
---|
| 892 | cmdrouter[x][ymax-1]->p_out[k][NORTH] (signal_dspin_false_cmd_out[x][xmax-1][k][1]); |
---|
| 893 | rsprouter[x][ymax-1]->p_in[k][NORTH] (signal_dspin_false_rsp_in[x][ymax-1][k][1]); |
---|
| 894 | rsprouter[x][ymax-1]->p_out[k][NORTH] (signal_dspin_false_rsp_out[x][ymax-1][k][1]); |
---|
| 895 | } |
---|
| 896 | } |
---|
| 897 | |
---|
| 898 | //////////////////////////////////////////////////////// |
---|
| 899 | // Simulation |
---|
| 900 | /////////////////////////////////////////////////////// |
---|
| 901 | |
---|
| 902 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
| 903 | signal_resetn = false; |
---|
| 904 | |
---|
| 905 | // network boundaries signals |
---|
| 906 | for(size_t x=0; x<xmax ; x++) |
---|
| 907 | { |
---|
| 908 | for(size_t y=0 ; y<ymax ; y++) |
---|
| 909 | { |
---|
| 910 | for (size_t k=0; k<2; k++) |
---|
| 911 | { |
---|
| 912 | for(size_t a=0; a<2; a++) |
---|
| 913 | { |
---|
| 914 | signal_dspin_false_cmd_in[x][y][k][a].write = false; |
---|
| 915 | signal_dspin_false_cmd_in[x][y][k][a].read = true; |
---|
| 916 | signal_dspin_false_cmd_out[x][y][k][a].write = false; |
---|
| 917 | signal_dspin_false_cmd_out[x][y][k][a].read = true; |
---|
| 918 | |
---|
| 919 | signal_dspin_false_rsp_in[x][y][k][a].write = false; |
---|
| 920 | signal_dspin_false_rsp_in[x][y][k][a].read = true; |
---|
| 921 | signal_dspin_false_rsp_out[x][y][k][a].write = false; |
---|
| 922 | signal_dspin_false_rsp_out[x][y][k][a].read = true; |
---|
| 923 | } |
---|
| 924 | } |
---|
| 925 | } |
---|
| 926 | } |
---|
| 927 | |
---|
| 928 | |
---|
| 929 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 930 | signal_resetn = true; |
---|
| 931 | |
---|
| 932 | for(size_t i=1 ; i<ncycles ; i++) |
---|
| 933 | { |
---|
| 934 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 935 | |
---|
| 936 | if( debug_ok && (i > from_cycle) && (i < to_cycle) ) |
---|
| 937 | { |
---|
| 938 | std::cout << std::dec << "*************** cycle " << i |
---|
| 939 | << " *******************************************************" << std::endl; |
---|
| 940 | proc[0][0][0]->print_trace(); |
---|
| 941 | proc[0][1][0]->print_trace(); |
---|
| 942 | proc[1][0][0]->print_trace(); |
---|
| 943 | proc[1][1][0]->print_trace(); |
---|
| 944 | std::cout << std::endl; |
---|
| 945 | ringd[0][0]->print_trace(); |
---|
| 946 | ringd[0][1]->print_trace(); |
---|
| 947 | ringd[1][0]->print_trace(); |
---|
| 948 | ringd[1][1]->print_trace(); |
---|
| 949 | ringc[0][0]->print_trace(); |
---|
| 950 | ringc[0][1]->print_trace(); |
---|
| 951 | ringc[1][0]->print_trace(); |
---|
| 952 | ringc[1][1]->print_trace(); |
---|
| 953 | std::cout << std::endl; |
---|
| 954 | cmdrouter[0][0]->print_trace(0); |
---|
| 955 | cmdrouter[0][1]->print_trace(0); |
---|
| 956 | cmdrouter[1][0]->print_trace(0); |
---|
| 957 | cmdrouter[1][1]->print_trace(0); |
---|
| 958 | std::cout << std::endl; |
---|
| 959 | cmdrouter[0][0]->print_trace(1); |
---|
| 960 | cmdrouter[0][1]->print_trace(1); |
---|
| 961 | cmdrouter[1][0]->print_trace(1); |
---|
| 962 | cmdrouter[1][1]->print_trace(1); |
---|
| 963 | std::cout << std::endl; |
---|
| 964 | memc[0][0]->print_trace(); |
---|
| 965 | memc[0][1]->print_trace(); |
---|
| 966 | memc[1][0]->print_trace(); |
---|
| 967 | memc[1][1]->print_trace(); |
---|
| 968 | // if ( i%5 == 0) getchar(); |
---|
| 969 | } |
---|
| 970 | } |
---|
| 971 | |
---|
| 972 | std::cout << "Hit ENTER to end simulation" << std::endl; |
---|
| 973 | char buf[1]; |
---|
| 974 | std::cin.getline(buf,1); |
---|
| 975 | |
---|
| 976 | return EXIT_SUCCESS; |
---|
| 977 | } |
---|
| 978 | |
---|
| 979 | int sc_main (int argc, char *argv[]) |
---|
| 980 | { |
---|
| 981 | try { |
---|
| 982 | return _main(argc, argv); |
---|
| 983 | } catch (std::exception &e) { |
---|
| 984 | std::cout << e.what() << std::endl; |
---|
| 985 | } catch (...) { |
---|
| 986 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 987 | throw; |
---|
| 988 | } |
---|
| 989 | return 1; |
---|
| 990 | } |
---|