[189] | 1 | ///////////////////////////////////////////////////////////////////////// |
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| 2 | // File: top.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : june 2011 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ///////////////////////////////////////////////////////////////////////// |
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| 8 | // This file define a generic TSAR architecture with virtual memory. |
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| 9 | // - It uses vci_local_crossbar as local interconnect |
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| 10 | // - It uses virtual_dspin as global interconnect |
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| 11 | // - It uses the vci_cc_vcache_wrapper_v4 |
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| 12 | // - It uses the vci_mem_cache_v4 |
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| 13 | // - It uses one vci_xicu, one vci_multi_tty, |
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| 14 | // and one vci_multi_dma controler per cluster. |
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| 15 | // |
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| 16 | // It is build with one single component implementing a cluster: |
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| 17 | // The Tsarv4ClusterMmu component is defined in files |
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| 18 | // tsarv4_cluster_mmu.* (with * = cpp, h, sd) |
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| 19 | // |
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| 20 | // The physical address space is 32 bits. |
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| 21 | // The number of clusters cannot be larger than 256. |
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| 22 | // The number of processors per cluster cannot be larger than 4. |
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| 23 | // The parameters must be power of 2. |
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| 24 | // - xmax : number of clusters in a row |
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| 25 | // - ymax : number of clusters in a column |
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| 26 | // - nprocs : number of processors per cluster |
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| 27 | // |
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| 28 | // The peripherals BDEV, FBUF, and the boot BROM |
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| 29 | // are in the cluster containing address 0xBFC00000. |
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| 30 | // - The nprocs TTY IRQs are connected to IRQ_IN[0] to IRQ_IN[3] |
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| 31 | // - The nprocs DMA IRQs are connected to IRQ_IN[4] to IRQ_IN[7] |
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| 32 | // - The IOC IRQ is connected to IRQ_IN[8] |
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| 33 | // |
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| 34 | // General policy for 32 bits physical address decoding: |
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| 35 | // All segments base addresses are multiple of 64 Kbytes |
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| 36 | // Therefore the 16 address MSB bits completely define the target: |
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| 37 | // The (x_width + y_width) MSB bits (left aligned) define |
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| 38 | // the cluster index, and the 8 LSB bits define the local index: |
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| 39 | // | X_ID | Y_ID |---| LADR | OFFSET | |
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| 40 | // |x_width|y_width|---| 8 | 16 | |
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| 41 | ///////////////////////////////////////////////////////////////////////// |
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| 42 | |
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| 43 | #include <systemc> |
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| 44 | #include <sys/time.h> |
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| 45 | #include <iostream> |
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| 46 | #include <sstream> |
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| 47 | #include <cstdlib> |
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| 48 | #include <cstdarg> |
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| 49 | #include <stdint.h> |
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| 50 | |
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| 51 | #include "gdbserver.h" |
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| 52 | #include "mapping_table.h" |
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| 53 | #include "tsarv4_cluster_mmu.h" |
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| 54 | #include "alloc_elems.h" |
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| 55 | |
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| 56 | /////////////////////////////////////////////////// |
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| 57 | // OS |
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| 58 | /////////////////////////////////////////////////// |
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| 59 | |
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[247] | 60 | #define USE_ALMOS 0 |
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[189] | 61 | #define almos_bootloader_pathname "/Users/alain/soc/tsar-svn-june-2010/softs/almos/bootloader/bin/bootloader-soclib-mipsel.bin" |
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| 62 | #define almos_kernel_pathname "/Users/alain/soc/tsar-svn-june-2010/softs/almos/kernel/bin/kernel-soclib-mipsel.bin@0xbfc10000:D" |
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| 63 | #define almos_archinfo_pathname "/Users/alain/soc/tsar-svn-june-2010/softs/almos/arch_bins/arch-info_4_4.bin@0xBFC08000:D" |
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| 64 | |
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| 65 | /////////////////////////////////////////////////// |
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| 66 | // Parallelisation |
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| 67 | /////////////////////////////////////////////////// |
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| 68 | |
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| 69 | #define USE_OPENMP 0 |
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| 70 | #define OPENMP_THREADS_NR 8 |
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| 71 | |
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| 72 | #if USE_OPENMP |
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| 73 | #include <omp.h> |
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| 74 | #endif |
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| 75 | |
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| 76 | // cluster index (computed from x,y coordinates) |
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| 77 | #define cluster(x,y) (y + ymax*x) |
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| 78 | |
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| 79 | // flit widths for the DSPIN network |
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| 80 | #define cmd_width 40 |
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| 81 | #define rsp_width 33 |
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| 82 | |
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| 83 | // VCI format |
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| 84 | #define cell_width 4 |
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| 85 | #define address_width 32 |
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| 86 | #define plen_width 8 |
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| 87 | #define error_width 2 |
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| 88 | #define clen_width 1 |
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| 89 | #define rflag_width 1 |
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| 90 | #define srcid_width 14 |
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| 91 | #define pktid_width 4 |
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| 92 | #define trdid_width 4 |
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| 93 | #define wrplen_width 1 |
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| 94 | |
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| 95 | /////////////////////////////////////////////////// |
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| 96 | // Parameters default values |
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| 97 | /////////////////////////////////////////////////// |
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| 98 | |
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| 99 | #define MESH_XMAX 2 |
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| 100 | #define MESH_YMAX 2 |
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| 101 | |
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[247] | 102 | #define NPROCS 4 |
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[189] | 103 | #define XRAM_LATENCY 0 |
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| 104 | |
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| 105 | #define MEMC_WAYS 16 |
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| 106 | #define MEMC_SETS 256 |
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| 107 | |
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| 108 | #define L1_IWAYS 4 |
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| 109 | #define L1_ISETS 64 |
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| 110 | |
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| 111 | #define L1_DWAYS 4 |
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| 112 | #define L1_DSETS 64 |
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| 113 | |
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[247] | 114 | #define FBUF_X_SIZE 512 |
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| 115 | #define FBUF_Y_SIZE 512 |
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[189] | 116 | |
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| 117 | #define BDEV_SECTOR_SIZE 128 |
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| 118 | #define BDEV_IMAGE_NAME "../../softs/soft_transpose_giet/images.raw" |
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| 119 | |
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| 120 | #define BOOT_SOFT_NAME "../../softs/soft_transpose_giet/bin.soft" |
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| 121 | |
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[247] | 122 | #define MAX_FROZEN_CYCLES 100000 |
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[189] | 123 | |
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| 124 | ///////////////////////////////////////////////////////// |
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| 125 | // Physical segments definition |
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| 126 | ///////////////////////////////////////////////////////// |
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| 127 | // There is 3 segments replicated in all clusters: |
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| 128 | // - seg_memc -> MEMC / BASE = 0x**000000 (12 M bytes) |
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| 129 | // - seg_icu -> ICU / BASE = 0x**F00000 |
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| 130 | // - seg_dma -> CDMA / BASE = 0x**F30000 |
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| 131 | // |
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| 132 | // There is 4 specific segments in the "IO" cluster |
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| 133 | // (containing address 0xBF000000) |
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| 134 | // - seg_reset -> BROM / BASE = 0xBFC00000 (1 Mbytes) |
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| 135 | // - seg_fbuf -> FBUF / BASE = 0xBFD00000 (2 M bytes) |
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| 136 | // - seg_bdev -> BDEV / BASE = 0xBFF10000 |
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| 137 | // - seg_tty -> MTTY / BASE = 0x**F20000 |
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| 138 | // |
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| 139 | // There is one special segment corresponding to |
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| 140 | // the processors in the coherence address space |
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| 141 | // - seg_proc -> PROC / BASE = 0x**B0 to 0xBF |
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| 142 | /////////////////////////////////////////////////// |
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| 143 | |
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| 144 | // specific segments in "IO" cluster |
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| 145 | |
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| 146 | #define BROM_BASE 0xBFC00000 |
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| 147 | #define BROM_SIZE 0x00100000 |
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| 148 | |
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| 149 | #define FBUF_BASE 0xBFD00000 |
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| 150 | #define FBUF_SIZE 0x00200000 |
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| 151 | |
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| 152 | #define BDEV_BASE 0xBFF10000 |
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| 153 | #define BDEV_SIZE 0x00000020 |
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| 154 | |
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| 155 | #define MTTY_BASE 0xBFF20000 |
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| 156 | #define MTTY_SIZE 0x00000040 |
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| 157 | |
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| 158 | // replicated segments |
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| 159 | |
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| 160 | #define MEMC_BASE 0x00000000 |
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| 161 | #define MEMC_SIZE 0x00C00000 |
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| 162 | |
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| 163 | #define XICU_BASE 0x00F00000 |
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| 164 | #define XICU_SIZE 0x00001000 |
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| 165 | |
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| 166 | #define CDMA_BASE 0x00F30000 |
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| 167 | #define CDMA_SIZE 0x00004000 |
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| 168 | |
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| 169 | #define PROC_BASE 0x00D00000 |
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| 170 | #define PROC_SIZE 0x00000010 |
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| 171 | |
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| 172 | //////////////////////////////////////////////////////////////////// |
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| 173 | // TGTID definition in direct space |
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| 174 | // For all components: global TGTID = global SRCID = cluster_index |
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| 175 | //////////////////////////////////////////////////////////////////// |
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| 176 | |
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| 177 | #define MEMC_TGTID 0 |
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| 178 | #define XICU_TGTID 1 |
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| 179 | #define CDMA_TGTID 2 |
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| 180 | #define MTTY_TGTID 3 |
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| 181 | #define FBUF_TGTID 4 |
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| 182 | #define BROM_TGTID 5 |
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| 183 | #define BDEV_TGTID 6 |
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| 184 | |
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| 185 | ///////////////////////////////// |
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| 186 | int _main(int argc, char *argv[]) |
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| 187 | { |
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| 188 | using namespace sc_core; |
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| 189 | using namespace soclib::caba; |
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| 190 | using namespace soclib::common; |
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| 191 | |
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| 192 | |
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| 193 | char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code |
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| 194 | size_t ncycles = 1000000000; // simulated cycles |
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| 195 | size_t xmax = MESH_XMAX; // number of clusters in a row |
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| 196 | size_t ymax = MESH_YMAX; // number of clusters in a column |
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| 197 | size_t nprocs = NPROCS; // number of processors per cluster |
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| 198 | size_t xfb = FBUF_X_SIZE; // frameBuffer column number |
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| 199 | size_t yfb = FBUF_Y_SIZE; // frameBuffer lines number |
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| 200 | size_t memc_ways = MEMC_WAYS; |
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| 201 | size_t memc_sets = MEMC_SETS; |
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| 202 | size_t l1_d_ways = L1_DWAYS; |
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| 203 | size_t l1_d_sets = L1_DSETS; |
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| 204 | size_t l1_i_ways = L1_IWAYS; |
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| 205 | size_t l1_i_sets = L1_ISETS; |
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| 206 | char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image |
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| 207 | size_t blk_size = BDEV_SECTOR_SIZE; // block size (in bytes) |
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| 208 | size_t xram_latency = XRAM_LATENCY; // external RAM latency |
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| 209 | bool trace_ok = false; // trace activated |
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| 210 | size_t trace_period = 1; // trace period |
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| 211 | uint32_t from_cycle = 0; // debug start cycle |
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| 212 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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| 213 | |
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| 214 | ////////////// command line arguments ////////////////////// |
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| 215 | if (argc > 1) |
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| 216 | { |
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| 217 | for( int n=1 ; n<argc ; n=n+2 ) |
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| 218 | { |
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| 219 | if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) ) |
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| 220 | { |
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| 221 | ncycles = atoi(argv[n+1]); |
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| 222 | } |
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| 223 | else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) ) |
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| 224 | { |
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| 225 | nprocs = atoi(argv[n+1]); |
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| 226 | assert( ((nprocs == 1) || (nprocs == 2) || (nprocs == 4)) && |
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| 227 | "NPROCS must be equal to 1, 2, or 4"); |
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| 228 | } |
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| 229 | else if( (strcmp(argv[n],"-XMAX") == 0) && (n+1<argc) ) |
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| 230 | { |
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| 231 | xmax = atoi(argv[n+1]); |
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| 232 | assert( ((xmax == 1) || (xmax == 2) || (xmax == 4) || (xmax == 8) || (xmax == 16)) |
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| 233 | && "The XMAX parameter must be 2, 4, 8, or 16" ); |
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| 234 | } |
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| 235 | |
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| 236 | else if( (strcmp(argv[n],"-YMAX") == 0) && (n+1<argc) ) |
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| 237 | { |
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| 238 | ymax = atoi(argv[n+1]); |
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| 239 | assert( ((ymax == 1) || (ymax == 2) || (ymax == 4) || (ymax == 8) || (ymax == 16)) |
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| 240 | && "The YMAX parameter must be 2, 4, 8, or 16" ); |
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| 241 | } |
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| 242 | else if( (strcmp(argv[n],"-XFB") == 0) && (n+1<argc) ) |
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| 243 | { |
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| 244 | xfb = atoi(argv[n+1]); |
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| 245 | } |
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| 246 | else if( (strcmp(argv[n],"-YFB") == 0) && (n+1<argc) ) |
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| 247 | { |
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| 248 | yfb = atoi(argv[n+1]); |
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| 249 | } |
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| 250 | else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ) |
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| 251 | { |
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| 252 | strcpy(soft_name, argv[n+1]); |
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| 253 | } |
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| 254 | else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) |
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| 255 | { |
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| 256 | strcpy(disk_name, argv[n+1]); |
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| 257 | } |
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| 258 | else if( (strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) ) |
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| 259 | { |
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| 260 | trace_ok = true; |
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| 261 | from_cycle = atoi(argv[n+1]); |
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| 262 | } |
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| 263 | else if((strcmp(argv[n], "-MCWAYS") == 0) && (n+1 < argc)) |
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| 264 | { |
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| 265 | memc_ways = atoi(argv[n+1]); |
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| 266 | } |
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| 267 | else if((strcmp(argv[n], "-MCSETS") == 0) && (n+1 < argc)) |
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| 268 | { |
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| 269 | memc_sets = atoi(argv[n+1]); |
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| 270 | } |
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| 271 | else if((strcmp(argv[n], "-XLATENCY") == 0) && (n+1 < argc)) |
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| 272 | { |
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| 273 | xram_latency = atoi(argv[n+1]); |
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| 274 | } |
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| 275 | else if((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) |
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| 276 | { |
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| 277 | frozen_cycles = atoi(argv[n+1]); |
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| 278 | } |
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| 279 | else if((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)) |
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| 280 | { |
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| 281 | trace_period = atoi(argv[n+1]); |
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| 282 | } |
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| 283 | else |
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| 284 | { |
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| 285 | std::cout << " Arguments on the command line are (key,value) couples." << std::endl; |
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| 286 | std::cout << " The order is not important." << std::endl; |
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| 287 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
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| 288 | std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; |
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| 289 | std::cout << " -DISK pathname_for_disk_image" << std::endl; |
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| 290 | std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; |
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| 291 | std::cout << " -NPROCS number_of_processors_per_cluster" << std::endl; |
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| 292 | std::cout << " -XMAX number_of_clusters_in_a_row" << std::endl; |
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| 293 | std::cout << " -YMAX number_of_clusters_in_a_column" << std::endl; |
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| 294 | std::cout << " -TRACE debug_start_cycle" << std::endl; |
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| 295 | std::cout << " -MCWAYS memory_cache_number_of_ways" << std::endl; |
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| 296 | std::cout << " -MCSETS memory_cache_number_of_sets" << std::endl; |
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| 297 | std::cout << " -XLATENCY external_ram_latency_value" << std::endl; |
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| 298 | std::cout << " -XFB fram_buffer_number_of_pixels" << std::endl; |
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| 299 | std::cout << " -YFB fram_buffer_number_of_lines" << std::endl; |
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| 300 | std::cout << " -FROZEN max_number_of_lines" << std::endl; |
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| 301 | std::cout << " -PERIOD number_of_cycles between trace" << std::endl; |
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| 302 | exit(0); |
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| 303 | } |
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| 304 | } |
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| 305 | } |
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| 306 | |
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| 307 | std::cout << std::endl; |
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| 308 | std::cout << " - NPROCS = " << nprocs << std::endl; |
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| 309 | std::cout << " - NCLUSTERS = " << xmax*ymax << std::endl; |
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| 310 | std::cout << " - MAX FROZEN = " << frozen_cycles << std::endl; |
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| 311 | std::cout << " - MEMC_WAYS = " << memc_ways << std::endl; |
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| 312 | std::cout << " - MEMC_SETS = " << memc_sets << std::endl; |
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| 313 | std::cout << " - RAM_LATENCY = " << xram_latency << std::endl; |
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| 314 | |
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| 315 | std::cout << std::endl; |
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| 316 | |
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| 317 | #if USE_OPENMP |
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| 318 | omp_set_dynamic(false); |
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| 319 | omp_set_num_threads(threads_nr); |
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| 320 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
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| 321 | #endif |
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| 322 | |
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| 323 | // Define VCI parameters |
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| 324 | typedef soclib::caba::VciParams<cell_width, |
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| 325 | plen_width, |
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| 326 | address_width, |
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| 327 | error_width, |
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| 328 | clen_width, |
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| 329 | rflag_width, |
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| 330 | srcid_width, |
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| 331 | pktid_width, |
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| 332 | trdid_width, |
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| 333 | wrplen_width> vci_param; |
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| 334 | |
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| 335 | size_t cluster_io_index; |
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| 336 | size_t x_width; |
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| 337 | size_t y_width; |
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| 338 | |
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| 339 | if (xmax == 1) x_width = 0; |
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| 340 | else if (xmax == 2) x_width = 1; |
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| 341 | else if (xmax <= 4) x_width = 2; |
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| 342 | else if (xmax <= 8) x_width = 3; |
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| 343 | else x_width = 4; |
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| 344 | |
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| 345 | if (ymax == 1) y_width = 0; |
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| 346 | else if (ymax == 2) y_width = 1; |
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| 347 | else if (ymax <= 4) y_width = 2; |
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| 348 | else if (ymax <= 8) y_width = 3; |
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| 349 | else y_width = 4; |
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| 350 | |
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| 351 | cluster_io_index = 0xBF >> (8 - x_width - y_width); |
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| 352 | |
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| 353 | ///////////////////// |
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| 354 | // Mapping Tables |
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| 355 | ///////////////////// |
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| 356 | |
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| 357 | // direct network |
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| 358 | MappingTable maptabd(address_width, |
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| 359 | IntTab(x_width + y_width, 16 - x_width - y_width), |
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| 360 | IntTab(x_width + y_width, srcid_width - x_width - y_width), |
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| 361 | 0x00FF0000); |
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| 362 | |
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| 363 | for ( size_t x = 0 ; x < xmax ; x++) |
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| 364 | { |
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| 365 | for ( size_t y = 0 ; y < ymax ; y++) |
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| 366 | { |
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| 367 | sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); |
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| 368 | |
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| 369 | std::ostringstream sh; |
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| 370 | sh << "d_seg_memc_" << x << "_" << y; |
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| 371 | maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true)); |
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| 372 | |
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| 373 | std::ostringstream si; |
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| 374 | si << "d_seg_xicu_" << x << "_" << y; |
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| 375 | maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false)); |
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| 376 | |
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| 377 | std::ostringstream sd; |
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| 378 | sd << "d_seg_mdma_" << x << "_" << y; |
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| 379 | maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false)); |
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| 380 | |
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| 381 | if ( cluster(x,y) == cluster_io_index ) |
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| 382 | { |
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| 383 | maptabd.add(Segment("d_seg_mtty ", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false)); |
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| 384 | maptabd.add(Segment("d_seg_fbuf ", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false)); |
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| 385 | maptabd.add(Segment("d_seg_bdev ", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false)); |
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| 386 | maptabd.add(Segment("d_seg_brom ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true)); |
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| 387 | } |
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| 388 | } |
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| 389 | } |
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| 390 | std::cout << maptabd << std::endl; |
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| 391 | |
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| 392 | // coherence network |
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| 393 | // - tgtid_c_proc = srcid_c_proc = local procid |
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| 394 | // - tgtid_c_memc = srcid_c_memc = nprocs |
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| 395 | MappingTable maptabc(address_width, |
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| 396 | IntTab(x_width + y_width, srcid_width - x_width - y_width), |
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[247] | 397 | IntTab(x_width + y_width, srcid_width - x_width - y_width), |
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[189] | 398 | 0x00FF0000); |
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| 399 | |
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| 400 | for ( size_t x = 0 ; x < xmax ; x++) |
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| 401 | { |
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| 402 | for ( size_t y = 0 ; y < ymax ; y++) |
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| 403 | { |
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| 404 | sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); |
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| 405 | |
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| 406 | // cleanup requests regarding the memc segment must be routed to the memory cache |
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| 407 | std::ostringstream sh; |
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| 408 | sh << "c_seg_memc_" << x << "_" << y; |
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[247] | 409 | maptabc.add( |
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| 410 | Segment( |
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| 411 | sh.str() |
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| 412 | , (nprocs << (address_width - srcid_width)) + offset |
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| 413 | , 0x10 |
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| 414 | , IntTab(cluster(x,y), nprocs) |
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| 415 | , false |
---|
| 416 | ) |
---|
| 417 | ); |
---|
[189] | 418 | |
---|
| 419 | // update & invalidate requests must be routed to the proper processor |
---|
| 420 | for ( size_t p = 0 ; p < nprocs ; p++) |
---|
| 421 | { |
---|
| 422 | std::ostringstream sp; |
---|
| 423 | sp << "c_seg_proc_" << x << "_" << y << "_" << p; |
---|
[247] | 424 | maptabc.add( |
---|
| 425 | Segment( |
---|
| 426 | sp.str() |
---|
| 427 | , (p << (address_width - srcid_width)) + offset |
---|
| 428 | , 0x10 |
---|
| 429 | , IntTab(cluster(x,y), p) |
---|
| 430 | , false |
---|
| 431 | ) |
---|
| 432 | ); |
---|
[189] | 433 | } |
---|
| 434 | } |
---|
| 435 | } |
---|
| 436 | std::cout << maptabc << std::endl; |
---|
| 437 | |
---|
| 438 | // external network |
---|
| 439 | MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000); |
---|
| 440 | |
---|
| 441 | for ( size_t x = 0 ; x < xmax ; x++) |
---|
| 442 | { |
---|
| 443 | for ( size_t y = 0 ; y < ymax ; y++) |
---|
| 444 | { |
---|
| 445 | sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); |
---|
| 446 | std::ostringstream sh; |
---|
| 447 | sh << "x_seg_memc_" << x << "_" << y; |
---|
| 448 | maptabx.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y)), false)); |
---|
| 449 | } |
---|
| 450 | } |
---|
| 451 | std::cout << maptabx << std::endl; |
---|
| 452 | |
---|
| 453 | //////////////////// |
---|
| 454 | // Signals |
---|
| 455 | /////////////////// |
---|
| 456 | |
---|
| 457 | sc_clock signal_clk("clk"); |
---|
| 458 | sc_signal<bool> signal_resetn("resetn"); |
---|
| 459 | |
---|
| 460 | // Horizontal inter-clusters DSPIN signals |
---|
| 461 | DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc = |
---|
| 462 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", xmax-1, ymax, 2); |
---|
| 463 | DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec = |
---|
| 464 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", xmax-1, ymax, 2); |
---|
| 465 | DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc = |
---|
| 466 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2); |
---|
| 467 | DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec = |
---|
| 468 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2); |
---|
| 469 | |
---|
| 470 | // Vertical inter-clusters DSPIN signals |
---|
| 471 | DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc = |
---|
| 472 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", xmax, ymax-1, 2); |
---|
| 473 | DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec = |
---|
| 474 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", xmax, ymax-1, 2); |
---|
| 475 | DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc = |
---|
| 476 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2); |
---|
| 477 | DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec = |
---|
| 478 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2); |
---|
| 479 | |
---|
| 480 | // Mesh boundaries DSPIN signals |
---|
| 481 | DspinSignals<cmd_width>**** signal_dspin_false_cmd_in = |
---|
| 482 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", xmax, ymax, 2, 4); |
---|
| 483 | DspinSignals<cmd_width>**** signal_dspin_false_cmd_out = |
---|
| 484 | alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", xmax, ymax, 2, 4); |
---|
| 485 | DspinSignals<rsp_width>**** signal_dspin_false_rsp_in = |
---|
| 486 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", xmax, ymax, 2, 4); |
---|
| 487 | DspinSignals<rsp_width>**** signal_dspin_false_rsp_out = |
---|
| 488 | alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", xmax, ymax, 2, 4); |
---|
| 489 | |
---|
| 490 | |
---|
| 491 | //////////////////////////// |
---|
| 492 | // Components |
---|
| 493 | //////////////////////////// |
---|
| 494 | |
---|
| 495 | #if USE_ALMOS |
---|
| 496 | soclib::common::Loader loader(almos_bootloader_pathname, |
---|
| 497 | almos_archinfo_pathname, |
---|
| 498 | almos_kernel_pathname); |
---|
| 499 | #else |
---|
| 500 | soclib::common::Loader loader(soft_name); |
---|
| 501 | #endif |
---|
| 502 | |
---|
| 503 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
| 504 | proc_iss::set_loader(loader); |
---|
| 505 | |
---|
| 506 | TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>* clusters[xmax][ymax]; |
---|
| 507 | |
---|
| 508 | #if USE_OPENMP |
---|
| 509 | |
---|
| 510 | #pragma omp parallel |
---|
| 511 | { |
---|
| 512 | #pragma omp for |
---|
| 513 | for( size_t i = 0 ; i < (xmax * ymax); i++) |
---|
| 514 | { |
---|
| 515 | size_t x = i / ymax; |
---|
| 516 | size_t y = i % ymax; |
---|
| 517 | |
---|
| 518 | #pragma omp critical |
---|
| 519 | std::ostringstream sc; |
---|
| 520 | sc << "cluster_" << x << "_" << y; |
---|
| 521 | clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width> |
---|
| 522 | (sc.str().c_str(), |
---|
| 523 | nprocs, |
---|
| 524 | x, |
---|
| 525 | y, |
---|
| 526 | cluster(x,y), |
---|
| 527 | maptabd, |
---|
| 528 | maptabc, |
---|
| 529 | maptabx, |
---|
| 530 | x_width, |
---|
| 531 | y_width, |
---|
| 532 | MEMC_TGTID, |
---|
| 533 | XICU_TGTID, |
---|
| 534 | FBUF_TGTID, |
---|
| 535 | MTTY_TGTID, |
---|
| 536 | BROM_TGTID, |
---|
| 537 | BDEV_TGTID, |
---|
| 538 | CDMA_TGTID, |
---|
| 539 | memc_ways, |
---|
| 540 | memc_sets, |
---|
| 541 | l1_i_ways, |
---|
| 542 | l1_i_sets, |
---|
| 543 | l1_d_ways, |
---|
| 544 | l1_d_sets, |
---|
| 545 | xram_latency, |
---|
| 546 | (cluster(x,y) == cluster_io_index), |
---|
| 547 | xfb, |
---|
| 548 | yfb, |
---|
| 549 | disk_name, |
---|
| 550 | blk_size, |
---|
| 551 | loader, |
---|
| 552 | frozen_cycles, |
---|
| 553 | from_cycle, |
---|
| 554 | trace_ok and (cluster_io_index == cluster(x,y)) ); |
---|
| 555 | } |
---|
| 556 | |
---|
| 557 | #else // NO OPENMP |
---|
| 558 | |
---|
| 559 | for( size_t x = 0 ; x < xmax ; x++) |
---|
| 560 | { |
---|
| 561 | for( size_t y = 0 ; y < ymax ; y++ ) |
---|
| 562 | { |
---|
| 563 | |
---|
| 564 | std::cout << "building cluster_" << x << "_" << y << std::endl; |
---|
| 565 | |
---|
| 566 | std::ostringstream sc; |
---|
| 567 | sc << "cluster_" << x << "_" << y; |
---|
| 568 | clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width> |
---|
| 569 | (sc.str().c_str(), |
---|
| 570 | nprocs, |
---|
| 571 | x, |
---|
| 572 | y, |
---|
| 573 | cluster(x,y), |
---|
| 574 | maptabd, |
---|
| 575 | maptabc, |
---|
| 576 | maptabx, |
---|
| 577 | x_width, |
---|
| 578 | y_width, |
---|
| 579 | MEMC_TGTID, |
---|
| 580 | XICU_TGTID, |
---|
| 581 | FBUF_TGTID, |
---|
| 582 | MTTY_TGTID, |
---|
| 583 | BROM_TGTID, |
---|
| 584 | BDEV_TGTID, |
---|
| 585 | CDMA_TGTID, |
---|
| 586 | memc_ways, |
---|
| 587 | memc_sets, |
---|
| 588 | l1_i_ways, |
---|
| 589 | l1_i_sets, |
---|
| 590 | l1_d_ways, |
---|
| 591 | l1_d_sets, |
---|
| 592 | xram_latency, |
---|
| 593 | (cluster(x,y) == cluster_io_index), |
---|
| 594 | xfb, |
---|
| 595 | yfb, |
---|
| 596 | disk_name, |
---|
| 597 | blk_size, |
---|
| 598 | loader, |
---|
| 599 | frozen_cycles, |
---|
| 600 | from_cycle, |
---|
| 601 | trace_ok and (cluster_io_index == cluster(x,y)) ); |
---|
| 602 | |
---|
| 603 | std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; |
---|
| 604 | |
---|
| 605 | } |
---|
| 606 | } |
---|
| 607 | |
---|
| 608 | #endif // USE_OPENMP |
---|
| 609 | |
---|
| 610 | /////////////////////////////////////////////////////////////// |
---|
| 611 | // Net-list |
---|
| 612 | /////////////////////////////////////////////////////////////// |
---|
| 613 | |
---|
| 614 | // Clock & RESET |
---|
| 615 | for ( size_t x = 0 ; x < (xmax) ; x++ ) |
---|
| 616 | { |
---|
| 617 | for ( size_t y = 0 ; y < ymax ; y++ ) |
---|
| 618 | { |
---|
| 619 | clusters[x][y]->p_clk (signal_clk); |
---|
| 620 | clusters[x][y]->p_resetn (signal_resetn); |
---|
| 621 | } |
---|
| 622 | } |
---|
| 623 | |
---|
| 624 | // Inter Clusters horizontal connections |
---|
| 625 | if ( xmax > 1 ) |
---|
| 626 | { |
---|
| 627 | for ( size_t x = 0 ; x < (xmax-1) ; x++ ) |
---|
| 628 | { |
---|
| 629 | for ( size_t y = 0 ; y < ymax ; y++ ) |
---|
| 630 | { |
---|
| 631 | for ( size_t k = 0 ; k < 2 ; k++ ) |
---|
| 632 | { |
---|
| 633 | clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]); |
---|
| 634 | clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]); |
---|
| 635 | clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]); |
---|
| 636 | clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]); |
---|
| 637 | clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]); |
---|
| 638 | clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]); |
---|
| 639 | clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]); |
---|
| 640 | clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]); |
---|
| 641 | } |
---|
| 642 | } |
---|
| 643 | } |
---|
| 644 | } |
---|
| 645 | std::cout << "Horizontal connections established" << std::endl; |
---|
| 646 | |
---|
| 647 | // Inter Clusters vertical connections |
---|
| 648 | if ( ymax > 1 ) |
---|
| 649 | { |
---|
| 650 | for ( size_t y = 0 ; y < (ymax-1) ; y++ ) |
---|
| 651 | { |
---|
| 652 | for ( size_t x = 0 ; x < xmax ; x++ ) |
---|
| 653 | { |
---|
| 654 | for ( size_t k = 0 ; k < 2 ; k++ ) |
---|
| 655 | { |
---|
| 656 | clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]); |
---|
| 657 | clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]); |
---|
| 658 | clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]); |
---|
| 659 | clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]); |
---|
| 660 | clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]); |
---|
| 661 | clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]); |
---|
| 662 | clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]); |
---|
| 663 | clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]); |
---|
| 664 | } |
---|
| 665 | } |
---|
| 666 | } |
---|
| 667 | } |
---|
| 668 | std::cout << "Vertical connections established" << std::endl; |
---|
| 669 | |
---|
| 670 | // East & West boundary cluster connections |
---|
| 671 | for ( size_t y = 0 ; y < ymax ; y++ ) |
---|
| 672 | { |
---|
| 673 | for ( size_t k = 0 ; k < 2 ; k++ ) |
---|
| 674 | { |
---|
| 675 | clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]); |
---|
| 676 | clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]); |
---|
| 677 | clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]); |
---|
| 678 | clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]); |
---|
| 679 | |
---|
| 680 | clusters[xmax-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[xmax-1][y][k][EAST]); |
---|
| 681 | clusters[xmax-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[xmax-1][y][k][EAST]); |
---|
| 682 | clusters[xmax-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[xmax-1][y][k][EAST]); |
---|
| 683 | clusters[xmax-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[xmax-1][y][k][EAST]); |
---|
| 684 | } |
---|
| 685 | } |
---|
| 686 | |
---|
| 687 | // North & South boundary clusters connections |
---|
| 688 | for ( size_t x = 0 ; x < xmax ; x++ ) |
---|
| 689 | { |
---|
| 690 | for ( size_t k = 0 ; k < 2 ; k++ ) |
---|
| 691 | { |
---|
| 692 | clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]); |
---|
| 693 | clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]); |
---|
| 694 | clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]); |
---|
| 695 | clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]); |
---|
| 696 | |
---|
| 697 | clusters[x][ymax-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][ymax-1][k][NORTH]); |
---|
| 698 | clusters[x][ymax-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][ymax-1][k][NORTH]); |
---|
| 699 | clusters[x][ymax-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][ymax-1][k][NORTH]); |
---|
| 700 | clusters[x][ymax-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][ymax-1][k][NORTH]); |
---|
| 701 | } |
---|
| 702 | } |
---|
| 703 | |
---|
| 704 | |
---|
| 705 | //////////////////////////////////////////////////////// |
---|
| 706 | // Simulation |
---|
| 707 | /////////////////////////////////////////////////////// |
---|
| 708 | |
---|
| 709 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
| 710 | signal_resetn = false; |
---|
| 711 | |
---|
| 712 | // network boundaries signals |
---|
| 713 | for(size_t x=0; x<xmax ; x++) |
---|
| 714 | { |
---|
| 715 | for(size_t y=0 ; y<ymax ; y++) |
---|
| 716 | { |
---|
| 717 | for (size_t k=0; k<2; k++) |
---|
| 718 | { |
---|
| 719 | for(size_t a=0; a<4; a++) |
---|
| 720 | { |
---|
| 721 | signal_dspin_false_cmd_in[x][y][k][a].write = false; |
---|
| 722 | signal_dspin_false_cmd_in[x][y][k][a].read = true; |
---|
| 723 | signal_dspin_false_cmd_out[x][y][k][a].write = false; |
---|
| 724 | signal_dspin_false_cmd_out[x][y][k][a].read = true; |
---|
| 725 | |
---|
| 726 | signal_dspin_false_rsp_in[x][y][k][a].write = false; |
---|
| 727 | signal_dspin_false_rsp_in[x][y][k][a].read = true; |
---|
| 728 | signal_dspin_false_rsp_out[x][y][k][a].write = false; |
---|
| 729 | signal_dspin_false_rsp_out[x][y][k][a].read = true; |
---|
| 730 | } |
---|
| 731 | } |
---|
| 732 | } |
---|
| 733 | } |
---|
| 734 | |
---|
| 735 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 736 | signal_resetn = true; |
---|
| 737 | |
---|
| 738 | for ( size_t n=1 ; n<ncycles ; n++) |
---|
| 739 | { |
---|
| 740 | if ( trace_ok and (n > from_cycle) and (n%trace_period == 0) ) |
---|
| 741 | { |
---|
| 742 | std::cout << "****************** cycle " << std::dec << n ; |
---|
| 743 | std::cout << " ************************************************" << std::endl; |
---|
| 744 | |
---|
| 745 | // components cluster 00 ///////////////////// |
---|
| 746 | // clusters[0][0]->proc[0]->print_trace(); |
---|
| 747 | // clusters[0][0]->memc->print_trace(); |
---|
| 748 | |
---|
| 749 | // signals cluster 00 //////////////////////// |
---|
| 750 | // clusters[0][0]->signal_vci_ini_d_proc[0].print_trace("proc_0_0_0_ini_d"); |
---|
| 751 | // clusters[0][0]->signal_vci_ini_c_proc[0].print_trace("proc_0_0_0_ini_c"); |
---|
| 752 | // clusters[0][0]->signal_vci_tgt_c_proc[0].print_trace("proc_0_0_0_tgt_c"); |
---|
| 753 | // clusters[0][0]->signal_vci_xram.print_trace("memc_0_0_xram"); |
---|
| 754 | |
---|
| 755 | // components cluster 01 ///////////////////// |
---|
| 756 | // clusters[0][1]->proc[0]->print_trace(); |
---|
| 757 | // clusters[0][1]->memc->print_trace(); |
---|
| 758 | |
---|
| 759 | // signals cluster 01 /////////////////////// |
---|
| 760 | // clusters[0][1]->signal_vci_ini_d_proc[0].print_trace("proc_0_1_0_ini_d"); |
---|
| 761 | // clusters[0][1]->signal_vci_ini_c_proc[0].print_trace("proc_0_1_0_ini_c"); |
---|
| 762 | // clusters[0][1]->signal_vci_tgt_c_proc[0].print_trace("proc_0_1_0_tgt_c"); |
---|
| 763 | // clusters[0][1]->signal_vci_xram.print_trace("memc_0_1_xram"); |
---|
| 764 | |
---|
| 765 | // components cluster 10 //////////////////// |
---|
| 766 | clusters[1][0]->proc[0]->print_trace(1); |
---|
| 767 | clusters[1][0]->memc->print_trace(); |
---|
| 768 | // clusters[1][0]->bdev->print_trace(); |
---|
| 769 | // clusters[1][0]->mdma->print_trace(); |
---|
| 770 | |
---|
| 771 | // signals cluster 10 /////////////////////// |
---|
| 772 | clusters[1][0]->signal_vci_ini_d_proc[0].print_trace("proc_1_0_0_ini_d"); |
---|
| 773 | // clusters[1][0]->signal_vci_ini_c_proc[0].print_trace("proc_1_0_0_ini_c"); |
---|
| 774 | // clusters[1][0]->signal_vci_tgt_c_proc[0].print_trace("proc_1_0_0_tgt_c"); |
---|
| 775 | clusters[1][0]->signal_vci_tgt_d_memc.print_trace("memc_1_0_tgt_d "); |
---|
| 776 | // clusters[1][0]->signal_vci_ini_c_memc.print_trace("memc_1_0_ini_c "); |
---|
| 777 | // clusters[1][0]->signal_vci_tgt_c_memc.print_trace("memc_1_0_tgt_c "); |
---|
| 778 | // clusters[1][0]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d "); |
---|
| 779 | // clusters[1][0]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d "); |
---|
| 780 | // clusters[1][0]->signal_vci_tgt_d_mdma.print_trace("mdma_1_0_tgt_d "); |
---|
| 781 | // clusters[1][0]->signal_vci_ini_d_mdma.print_trace("mdma_1_0_ini_d "); |
---|
| 782 | clusters[1][0]->signal_vci_tgt_d_mtty.print_trace("mtty_1_0_tgt_d "); |
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| 783 | clusters[1][0]->signal_vci_xram.print_trace("memc_1_0_xram"); |
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| 784 | |
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| 785 | // components cluster 11 ///////////////////// |
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| 786 | // clusters[1][1]->proc[0]->print_trace(); |
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| 787 | // clusters[1][1]->memc->print_trace(); |
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| 788 | |
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| 789 | // signals cluster 11 //////////////////////// |
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| 790 | // clusters[1][1]->signal_vci_ini_d_proc[0].print_trace("proc_1_1_0_ini_d"); |
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| 791 | // clusters[1][1]->signal_vci_ini_c_proc[0].print_trace("proc_1_1_0_ini_c"); |
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| 792 | // clusters[1][1]->signal_vci_tgt_c_proc[0].print_trace("proc_1_1_0_tgt_c"); |
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| 793 | // clusters[1][1]->signal_vci_xram.print_trace("memc_1_1_xram"); |
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| 794 | } |
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| 795 | |
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| 796 | sc_start(sc_core::sc_time(1, SC_NS)); |
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| 797 | } |
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| 798 | return EXIT_SUCCESS; |
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| 799 | } |
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| 800 | |
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| 801 | int sc_main (int argc, char *argv[]) |
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| 802 | { |
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| 803 | try { |
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| 804 | return _main(argc, argv); |
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| 805 | } catch (std::exception &e) { |
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| 806 | std::cout << e.what() << std::endl; |
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| 807 | } catch (...) { |
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| 808 | std::cout << "Unknown exception occured" << std::endl; |
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| 809 | throw; |
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| 810 | } |
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| 811 | return 1; |
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| 812 | } |
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