[189] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsarv4_cluster_mmu.h |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : march 2011 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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| 8 | // This file define a TSAR cluster architecture with virtual memory: |
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| 9 | // - It uses the virtual_dspin_router as distributed global interconnect |
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| 10 | // - It uses the vci_local_crossbar as local interconnect |
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| 11 | // - It uses the vci_cc_vcache_wrapper_v4 |
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| 12 | // - It uses the vci_mem_cache_v4 |
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| 13 | // - It contains a private RAM with a variable latency to emulate the L3 cache |
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| 14 | // - It can contains 1, 2 or 4 processors |
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| 15 | // - Each processor has a private dma channel (vci_multi_dma) |
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| 16 | // - It uses the vci_xicu interrupt controller |
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| 17 | // - The peripherals MTTY, BDEV, FBUF, and the boot BROM are in the cluster |
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| 18 | // containing address 0xBFC00000. |
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| 19 | // - The Multi-TTY component controls 4 terminals. |
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| 20 | // - The nprocs dma irqs are connected to IRQ_IN[0]...IRQ_IN[3] |
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| 21 | // - The four tty irqs are connected to IRQ_IN[4]...IRQ_IN[7] |
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| 22 | // - The bdev irq is connected to IRQ_IN[8] |
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| 23 | ////////////////////////////////////////////////////////////////////////////////// |
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| 24 | |
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| 25 | #ifndef SOCLIB_CABA_TSAR_CLUSTER_V4_MMU_H |
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| 26 | #define SOCLIB_CABA_TSAR_CLUSTER_V4_MMU_H |
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| 27 | |
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| 28 | #include <systemc> |
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| 29 | #include <sys/time.h> |
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| 30 | #include <iostream> |
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| 31 | #include <sstream> |
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| 32 | #include <cstdlib> |
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| 33 | #include <cstdarg> |
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| 34 | |
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| 35 | #include "gdbserver.h" |
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| 36 | #include "mapping_table.h" |
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| 37 | #include "mips32.h" |
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| 38 | #include "vci_simple_ram.h" |
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| 39 | #include "vci_xicu.h" |
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| 40 | #include "vci_local_crossbar.h" |
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| 41 | #include "virtual_dspin_router.h" |
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| 42 | #include "vci_vdspin_target_wrapper.h" |
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| 43 | #include "vci_vdspin_initiator_wrapper.h" |
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| 44 | #include "vci_multi_tty.h" |
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| 45 | #include "vci_block_device_tsar_v4.h" |
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| 46 | #include "vci_framebuffer.h" |
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| 47 | #include "vci_multi_dma.h" |
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| 48 | #include "vci_mem_cache_v4.h" |
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| 49 | #include "vci_cc_vcache_wrapper_v4.h" |
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| 50 | |
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| 51 | namespace soclib { |
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| 52 | namespace caba { |
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| 53 | |
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| 54 | /////////////////////////////////////////////////////////////////////////// |
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| 55 | template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> |
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| 56 | class TsarV4ClusterMmu |
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| 57 | /////////////////////////////////////////////////////////////////////////// |
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| 58 | : public soclib::caba::BaseModule |
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| 59 | { |
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| 60 | |
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| 61 | public: |
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| 62 | |
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| 63 | // Ports |
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| 64 | sc_in<bool> p_clk; |
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| 65 | sc_in<bool> p_resetn; |
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| 66 | soclib::caba::DspinOutput<cmd_width> **p_cmd_out; |
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| 67 | soclib::caba::DspinInput<cmd_width> **p_cmd_in; |
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| 68 | soclib::caba::DspinOutput<rsp_width> **p_rsp_out; |
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| 69 | soclib::caba::DspinInput<rsp_width> **p_rsp_in; |
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| 70 | |
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| 71 | // interrupt signals |
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| 72 | sc_signal<bool> signal_false; |
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| 73 | sc_signal<bool> signal_proc_it[4]; |
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| 74 | sc_signal<bool> signal_irq_mdma[4]; |
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| 75 | sc_signal<bool> signal_irq_tty0; |
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| 76 | sc_signal<bool> signal_irq_tty1; |
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| 77 | sc_signal<bool> signal_irq_tty2; |
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| 78 | sc_signal<bool> signal_irq_tty3; |
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| 79 | sc_signal<bool> signal_irq_bdev; |
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| 80 | |
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| 81 | // DSPIN signals between DSPIN routers and VCI/DSPIN wrappers |
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| 82 | DspinSignals<cmd_width> signal_dspin_cmd_l2g_d; |
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| 83 | DspinSignals<cmd_width> signal_dspin_cmd_g2l_d; |
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| 84 | DspinSignals<cmd_width> signal_dspin_cmd_l2g_c; |
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| 85 | DspinSignals<cmd_width> signal_dspin_cmd_g2l_c; |
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| 86 | DspinSignals<rsp_width> signal_dspin_rsp_l2g_d; |
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| 87 | DspinSignals<rsp_width> signal_dspin_rsp_g2l_d; |
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| 88 | DspinSignals<rsp_width> signal_dspin_rsp_l2g_c; |
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| 89 | DspinSignals<rsp_width> signal_dspin_rsp_g2l_c; |
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| 90 | |
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| 91 | // VCI signals between VCI/DSPIN wrappers and local crossbars |
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| 92 | VciSignals<vci_param> signal_vci_l2g_d; |
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| 93 | VciSignals<vci_param> signal_vci_g2l_d; |
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| 94 | VciSignals<vci_param> signal_vci_l2g_c; |
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| 95 | VciSignals<vci_param> signal_vci_g2l_c; |
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| 96 | |
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| 97 | // Direct VCI signals |
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| 98 | VciSignals<vci_param> signal_vci_ini_d_proc[4]; |
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| 99 | VciSignals<vci_param> signal_vci_ini_d_bdev; |
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| 100 | VciSignals<vci_param> signal_vci_ini_d_mdma; |
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| 101 | |
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| 102 | VciSignals<vci_param> signal_vci_tgt_d_memc; |
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| 103 | VciSignals<vci_param> signal_vci_tgt_d_mtty; |
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| 104 | VciSignals<vci_param> signal_vci_tgt_d_xicu; |
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| 105 | VciSignals<vci_param> signal_vci_tgt_d_bdev; |
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| 106 | VciSignals<vci_param> signal_vci_tgt_d_mdma; |
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| 107 | VciSignals<vci_param> signal_vci_tgt_d_brom; |
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| 108 | VciSignals<vci_param> signal_vci_tgt_d_fbuf; |
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| 109 | |
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| 110 | // Coherence VCi signals |
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| 111 | VciSignals<vci_param> signal_vci_ini_c_proc[4]; |
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| 112 | VciSignals<vci_param> signal_vci_tgt_c_proc[4]; |
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| 113 | VciSignals<vci_param> signal_vci_ini_c_memc; |
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| 114 | VciSignals<vci_param> signal_vci_tgt_c_memc; |
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| 115 | |
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| 116 | // external RAM VCI signal |
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| 117 | VciSignals<vci_param> signal_vci_xram; |
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| 118 | |
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| 119 | // Components |
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| 120 | |
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| 121 | VciCcVCacheWrapperV4<vci_param, iss_t>* proc[4]; |
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| 122 | VciMemCacheV4<vci_param>* memc; |
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| 123 | VciXicu<vci_param>* xicu; |
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| 124 | VciLocalCrossbar<vci_param>* xbard; |
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| 125 | VciLocalCrossbar<vci_param>* xbarc; |
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| 126 | VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>* tgtwrapperd; |
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| 127 | VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>* iniwrapperd; |
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| 128 | VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>* tgtwrapperc; |
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| 129 | VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>* iniwrapperc; |
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| 130 | VirtualDspinRouter<cmd_width>* cmdrouter; |
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| 131 | VirtualDspinRouter<rsp_width>* rsprouter; |
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| 132 | VciSimpleRam<vci_param>* brom; |
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| 133 | VciMultiTty<vci_param>* mtty; |
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| 134 | VciFrameBuffer<vci_param>* fbuf; |
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| 135 | VciBlockDeviceTsarV4<vci_param>* bdev; |
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| 136 | VciMultiDma<vci_param>* mdma; |
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| 137 | VciSimpleRam<vci_param>* xram; |
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| 138 | |
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| 139 | TsarV4ClusterMmu(sc_module_name insname, |
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| 140 | size_t nprocs, // number of processors |
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| 141 | size_t n_x, // x coordinate |
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| 142 | size_t n_y, // y coordinate |
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| 143 | size_t n_cluster, // y + ymax*x |
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| 144 | const soclib::common::MappingTable &mtd, // direct mapping table |
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| 145 | const soclib::common::MappingTable &mtc, // coherence mapping table |
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| 146 | const soclib::common::MappingTable &mtx, // xram mapping table |
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| 147 | size_t x_width, // x field number of bits |
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| 148 | size_t y_width, // y field number of bits |
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| 149 | size_t tgtid_memc, |
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| 150 | size_t tgtid_xicu, |
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| 151 | size_t tgtid_fbuf, |
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| 152 | size_t tgtid_mtty, |
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| 153 | size_t tgtid_brom, |
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| 154 | size_t tgtid_bdev, |
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| 155 | size_t tgtid_mdma, |
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| 156 | size_t memc_ways, // number of ways for MEMC |
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| 157 | size_t memc_sets, // number of sets for MEMC |
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| 158 | size_t l1_i_ways, // number of ways for L1 ICACHE |
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| 159 | size_t l1_i_sets, // number of sets for L1 ICACHE |
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| 160 | size_t l1_d_ways, // number of ways for L1 DCACHE |
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| 161 | size_t l1_d_sets, // number of sets for L1 DCACHE |
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| 162 | size_t xram_latency, // external ram latency |
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| 163 | bool io, // I/O cluster if true |
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| 164 | size_t xfb, // frame buffer pixels |
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| 165 | size_t yfb, // frame buffer lines |
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| 166 | char* disk_name, // virtual disk name for BDEV |
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| 167 | size_t block_size, // block size for BDEV |
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| 168 | Loader loader, // loader for BROM |
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| 169 | uint32_t frozen_cycles, // max frozen cycles |
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| 170 | uint32_t start_debug_cycle, |
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| 171 | bool debug_ok); |
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| 172 | |
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| 173 | ~TsarV4ClusterMmu(); |
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| 174 | }; |
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| 175 | }} |
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| 176 | |
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| 177 | #endif |
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