[189] | 1 | #include "../include/tsarv4_cluster_mmu.h" |
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| 2 | |
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| 3 | namespace soclib { |
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| 4 | namespace caba { |
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| 5 | |
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| 6 | ////////////////////////////////////////////////////////////////////////// |
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| 7 | // Constructor |
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| 8 | ////////////////////////////////////////////////////////////////////////// |
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| 9 | template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> |
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[249] | 10 | TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterMmu( |
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| 11 | sc_module_name insname, |
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| 12 | size_t nprocs, |
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| 13 | size_t x_id, |
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| 14 | size_t y_id, |
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| 15 | size_t cluster_id, |
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| 16 | const soclib::common::MappingTable &mtd, |
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| 17 | const soclib::common::MappingTable &mtc, |
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| 18 | const soclib::common::MappingTable &mtx, |
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| 19 | size_t x_width, |
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| 20 | size_t y_width, |
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| 21 | size_t tgtid_memc, |
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| 22 | size_t tgtid_xicu, |
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| 23 | size_t tgtid_fbuf, |
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| 24 | size_t tgtid_mtty, |
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| 25 | size_t tgtid_brom, |
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| 26 | size_t tgtid_bdev, |
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| 27 | size_t tgtid_mdma, |
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| 28 | size_t memc_ways, |
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| 29 | size_t memc_sets, |
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| 30 | size_t l1_i_ways, |
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| 31 | size_t l1_i_sets, |
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| 32 | size_t l1_d_ways, |
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| 33 | size_t l1_d_sets, |
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| 34 | size_t xram_latency, |
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| 35 | bool io, |
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| 36 | size_t xfb, |
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| 37 | size_t yfb, |
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| 38 | char* disk_name, |
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| 39 | size_t block_size, |
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| 40 | const Loader &loader, |
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| 41 | uint32_t frozen_cycles, |
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| 42 | uint32_t debug_start_cycle, |
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| 43 | bool debug_ok) |
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| 44 | : soclib::caba::BaseModule(insname), |
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| 45 | p_clk("clk"), |
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| 46 | p_resetn("resetn"), |
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[189] | 47 | |
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[249] | 48 | signal_dspin_cmd_l2g_d("signal_dspin_cmd_l2g_d"), |
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| 49 | signal_dspin_cmd_g2l_d("signal_dspin_cmd_g2l_d"), |
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| 50 | signal_dspin_cmd_l2g_c("signal_dspin_cmd_l2g_c"), |
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| 51 | signal_dspin_cmd_g2l_c("signal_dspin_cmd_g2l_c"), |
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| 52 | signal_dspin_rsp_l2g_d("signal_dspin_rsp_l2g_d"), |
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| 53 | signal_dspin_rsp_g2l_d("signal_dspin_rsp_g2l_d"), |
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| 54 | signal_dspin_rsp_l2g_c("signal_dspin_rsp_l2g_c"), |
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| 55 | signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"), |
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[189] | 56 | |
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[249] | 57 | signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"), |
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| 58 | signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"), |
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[189] | 59 | |
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[249] | 60 | signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"), |
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| 61 | signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"), |
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| 62 | signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"), |
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| 63 | signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"), |
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| 64 | signal_vci_tgt_d_mdma("signal_vci_tgt_d_mdma"), |
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| 65 | signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"), |
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| 66 | signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"), |
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[189] | 67 | |
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[249] | 68 | signal_vci_ini_c_memc("signal_vci_ini_c_memc"), |
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| 69 | signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"), |
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[189] | 70 | |
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[249] | 71 | signal_vci_xram("signal_vci_xram") |
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[189] | 72 | |
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[249] | 73 | { |
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| 74 | // Vectors of ports definition |
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[189] | 75 | |
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[249] | 76 | p_cmd_in = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4); |
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| 77 | p_cmd_out = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4); |
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| 78 | p_rsp_in = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4); |
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| 79 | p_rsp_out = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4); |
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[189] | 80 | |
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[249] | 81 | // Components definition |
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[189] | 82 | |
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[249] | 83 | // on direct network : local srcid[proc] in [0...nprocs-1] |
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| 84 | // on direct network : local srcid[mdma] = nprocs |
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| 85 | // on direct network : local srcid[bdev] = nprocs + 1 |
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[189] | 86 | |
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[249] | 87 | // on coherence network : local srcid[proc] in [0...nprocs-1] |
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| 88 | // on coherence network : local srcid[memc] = nprocs |
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[189] | 89 | |
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[249] | 90 | std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; |
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[189] | 91 | |
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[249] | 92 | for (size_t p = 0; p < nprocs; p++){ |
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| 93 | std::ostringstream sproc; |
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| 94 | sproc << "proc_" << x_id << "_" << y_id << "_" << p; |
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| 95 | proc[p] = new VciCcVCacheWrapperV4<vci_param, iss_t>( |
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| 96 | sproc.str().c_str(), |
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| 97 | cluster_id*nprocs + p, |
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| 98 | mtd, // Mapping Table Direct |
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| 99 | mtc, // Mapping Table Coherence |
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| 100 | IntTab(cluster_id,p), // SRCID_D |
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| 101 | IntTab(cluster_id,p), // SRCID_C |
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| 102 | IntTab(cluster_id,p), // TGTID_C |
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| 103 | 8, // ITLB ways |
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| 104 | 8, // ITLB sets |
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| 105 | 8, // DTLB ways |
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| 106 | 8, // DTLB sets |
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| 107 | l1_i_ways,l1_i_sets,16, // ICACHE size |
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| 108 | l1_d_ways,l1_d_sets,16, // DCACHE size |
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| 109 | 4, // WBUF width |
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| 110 | 4, // WBUF depth |
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| 111 | x_width, // X Width |
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| 112 | y_width, // Y Width |
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| 113 | nprocs, // Memory Cache Local Id (coherence) |
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| 114 | frozen_cycles, // max frozen cycles |
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| 115 | debug_start_cycle, |
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| 116 | debug_ok); |
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| 117 | } |
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[189] | 118 | |
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[249] | 119 | std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; |
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[189] | 120 | |
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[249] | 121 | std::ostringstream smemc; |
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| 122 | smemc << "memc_" << x_id << "_" << y_id; |
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| 123 | memc = new VciMemCacheV4<vci_param>( |
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| 124 | smemc.str().c_str(), |
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| 125 | mtd, mtc, mtx, |
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| 126 | IntTab(cluster_id), // SRCID_X |
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| 127 | IntTab(cluster_id, nprocs), // SRCID_C |
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| 128 | IntTab(cluster_id, tgtid_memc), // TGTID_D |
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| 129 | IntTab(cluster_id, nprocs), // TGTID_C |
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| 130 | memc_ways, memc_sets, 16, // CACHE SIZE |
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| 131 | 4096, // HEAP SIZE |
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| 132 | 8, // TRANSACTION TABLE DEPTH |
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| 133 | 8, // UPDATE TABLE DEPTH |
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| 134 | debug_start_cycle, |
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| 135 | debug_ok); |
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[189] | 136 | |
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| 137 | |
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[249] | 138 | std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; |
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[189] | 139 | |
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[249] | 140 | std::ostringstream sxram; |
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| 141 | sxram << "xram_" << x_id << "_" << y_id; |
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| 142 | xram = new VciSimpleRam<vci_param>( |
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| 143 | sxram.str().c_str(), |
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| 144 | IntTab(cluster_id), |
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| 145 | mtx, |
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| 146 | loader, |
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| 147 | xram_latency); |
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[189] | 148 | |
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[249] | 149 | std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; |
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[189] | 150 | |
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[249] | 151 | size_t nhwi = 4; // always 4 (or 9) ports, even if |
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| 152 | if (io){ |
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| 153 | nhwi = 9; // there if less than 4 processors |
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| 154 | } |
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| 155 | std::ostringstream sicu; |
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| 156 | sicu << "xicu_" << x_id << "_" << y_id; |
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| 157 | xicu = new VciXicu<vci_param>( |
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| 158 | sicu.str().c_str(), |
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| 159 | mtd, // mapping table |
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| 160 | IntTab(cluster_id, tgtid_xicu), // TGTID_D |
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| 161 | 0, // number of timer IRQs |
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| 162 | nhwi, // number of hard IRQs |
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| 163 | 0, // number of soft IRQs |
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| 164 | nprocs); // number of output IRQs |
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[189] | 165 | |
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[249] | 166 | std::cout << " - building dma_" << x_id << "_" << y_id << std::endl; |
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[189] | 167 | |
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[249] | 168 | // dma multi-canaux |
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| 169 | std::ostringstream sdma; |
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| 170 | sdma << "dma_" << x_id << "_" << y_id; |
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| 171 | mdma = new VciMultiDma<vci_param>( |
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| 172 | sdma.str().c_str(), |
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| 173 | mtd, |
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| 174 | IntTab(cluster_id, nprocs), // SRCID |
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| 175 | IntTab(cluster_id, tgtid_mdma), // TGTID |
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| 176 | 64, // burst size |
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| 177 | nprocs); // number of IRQs |
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[189] | 178 | |
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[249] | 179 | std::cout << " - building xbard_" << x_id << "_" << y_id << std::endl; |
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[189] | 180 | |
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[249] | 181 | // direct local crossbar |
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| 182 | size_t nb_direct_initiators = nprocs + 1; |
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| 183 | size_t nb_direct_targets = 3; |
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| 184 | if (io){ |
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| 185 | nb_direct_initiators = nprocs + 2; |
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| 186 | nb_direct_targets = 7; |
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| 187 | } |
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| 188 | std::ostringstream sd; |
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| 189 | sd << "xbard_" << x_id << "_" << y_id; |
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| 190 | xbard = new VciLocalCrossbar<vci_param>( |
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| 191 | sd.str().c_str(), |
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| 192 | mtd, |
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| 193 | IntTab(cluster_id), // cluster initiator index |
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| 194 | IntTab(cluster_id), // cluster target index |
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| 195 | nb_direct_initiators, // number of initiators |
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| 196 | nb_direct_targets); // number of targets |
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[189] | 197 | |
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[249] | 198 | std::cout << " - building xbarc_" << x_id << "_" << y_id << std::endl; |
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[189] | 199 | |
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[249] | 200 | // coherence local crossbar |
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| 201 | std::ostringstream sc; |
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| 202 | sc << "xbarc_" << x_id << "_" << y_id; |
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| 203 | xbarc = new VciLocalCrossbar<vci_param>( |
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| 204 | sc.str().c_str(), |
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| 205 | mtc, |
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| 206 | IntTab(cluster_id), // cluster initiator index |
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| 207 | IntTab(cluster_id), // cluster target index |
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| 208 | nprocs + 1, // number of initiators |
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| 209 | nprocs + 1); // number of targets |
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[189] | 210 | |
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[249] | 211 | std::cout << " - building wrappers in cluster_" << x_id << "_" << y_id << std::endl; |
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[189] | 212 | |
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[249] | 213 | // direct initiator wrapper |
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| 214 | std::ostringstream wid; |
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| 215 | wid << "iniwrapperd_" << x_id << "_" << y_id; |
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| 216 | iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( |
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| 217 | wid.str().c_str(), |
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| 218 | 4, // cmd fifo depth |
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| 219 | 4); // rsp fifo depth |
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[189] | 220 | |
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[249] | 221 | // direct target wrapper |
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| 222 | std::ostringstream wtd; |
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| 223 | wtd << "tgtwrapperd_" << x_id << "_" << y_id; |
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| 224 | tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( |
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| 225 | wtd.str().c_str(), |
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| 226 | 4, // cmd fifo depth |
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| 227 | 4); // rsp fifo depth |
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[189] | 228 | |
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[249] | 229 | // coherence initiator wrapper |
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| 230 | std::ostringstream wic; |
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| 231 | wic << "iniwrapperc_" << x_id << "_" << y_id; |
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| 232 | iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( |
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| 233 | wic.str().c_str(), |
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| 234 | 4, // cmd fifo depth |
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| 235 | 4); // rsp fifo depth |
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[189] | 236 | |
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[249] | 237 | // coherence target wrapper |
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| 238 | std::ostringstream wtc; |
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| 239 | wtc << "tgtwrapperc_" << x_id << "_" << y_id; |
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| 240 | tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( |
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| 241 | wtc.str().c_str(), |
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| 242 | 4, // cmd fifo depth |
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| 243 | 4); // rsp fifo depth |
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[189] | 244 | |
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[249] | 245 | std::cout << " - building cmdrouter_" << x_id << "_" << y_id << std::endl; |
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[189] | 246 | |
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[249] | 247 | // CMD router |
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| 248 | std::ostringstream scmd; |
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| 249 | scmd << "cmdrouter_" << x_id << "_" << y_id; |
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| 250 | cmdrouter = new VirtualDspinRouter<cmd_width>( |
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| 251 | scmd.str().c_str(), |
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| 252 | x_id,y_id, // coordinate in the mesh |
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| 253 | x_width, y_width, // x & y fields width |
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| 254 | 4,4); // input & output fifo depths |
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[189] | 255 | |
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[249] | 256 | std::cout << " - building rsprouter_" << x_id << "_" << y_id << std::endl; |
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[189] | 257 | |
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[249] | 258 | // RSP router |
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| 259 | std::ostringstream srsp; |
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| 260 | srsp << "rsprouter_" << x_id << "_" << y_id; |
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| 261 | rsprouter = new VirtualDspinRouter<rsp_width>( |
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| 262 | srsp.str().c_str(), |
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| 263 | x_id,y_id, // coordinates in mesh |
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| 264 | x_width, y_width, // x & y fields width |
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| 265 | 4,4); // input & output fifo depths |
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[189] | 266 | |
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[249] | 267 | // IO cluster components |
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| 268 | if (io){ |
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| 269 | brom = new VciSimpleRam<vci_param>( |
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| 270 | "brom", |
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| 271 | IntTab(cluster_id, tgtid_brom), |
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| 272 | mtd, |
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| 273 | loader); |
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[189] | 274 | |
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[249] | 275 | fbuf = new VciFrameBuffer<vci_param>( |
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| 276 | "fbuf", |
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| 277 | IntTab(cluster_id, tgtid_fbuf), |
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| 278 | mtd, |
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| 279 | xfb, yfb); |
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[189] | 280 | |
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[249] | 281 | bdev = new VciBlockDeviceTsarV4<vci_param>( |
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| 282 | "bdev", |
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| 283 | mtd, |
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| 284 | IntTab(cluster_id, nprocs+1), |
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| 285 | IntTab(cluster_id, tgtid_bdev), |
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| 286 | disk_name, |
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| 287 | block_size); |
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[189] | 288 | |
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[249] | 289 | mtty = new VciMultiTty<vci_param>( |
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| 290 | "mtty", |
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| 291 | IntTab(cluster_id, tgtid_mtty), |
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| 292 | mtd, |
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| 293 | "tty0", "tty1", "tty2", "tty3", NULL); |
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| 294 | } |
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[189] | 295 | |
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[249] | 296 | std::cout << " - all components constructed" << std::endl; |
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[189] | 297 | |
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[249] | 298 | //////////////////////////////////// |
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| 299 | // Connections are defined here |
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| 300 | //////////////////////////////////// |
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[189] | 301 | |
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[249] | 302 | // CMDROUTER and RSPROUTER |
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| 303 | cmdrouter->p_clk (this->p_clk); |
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| 304 | cmdrouter->p_resetn (this->p_resetn); |
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| 305 | rsprouter->p_clk (this->p_clk); |
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| 306 | rsprouter->p_resetn (this->p_resetn); |
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| 307 | for (int x = 0; x < 2; x++){ |
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| 308 | for(int y = 0; y < 4; y++){ |
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| 309 | cmdrouter->p_out[x][y] (this->p_cmd_out[x][y]); |
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| 310 | cmdrouter->p_in[x][y] (this->p_cmd_in[x][y]); |
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| 311 | rsprouter->p_out[x][y] (this->p_rsp_out[x][y]); |
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| 312 | rsprouter->p_in[x][y] (this->p_rsp_in[x][y]); |
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| 313 | } |
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| 314 | } |
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[189] | 315 | |
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[249] | 316 | cmdrouter->p_out[0][4] (signal_dspin_cmd_g2l_d); |
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| 317 | cmdrouter->p_out[1][4] (signal_dspin_cmd_g2l_c); |
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| 318 | cmdrouter->p_in[0][4] (signal_dspin_cmd_l2g_d); |
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| 319 | cmdrouter->p_in[1][4] (signal_dspin_cmd_l2g_c); |
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[189] | 320 | |
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[249] | 321 | rsprouter->p_out[0][4] (signal_dspin_rsp_g2l_d); |
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| 322 | rsprouter->p_out[1][4] (signal_dspin_rsp_g2l_c); |
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| 323 | rsprouter->p_in[0][4] (signal_dspin_rsp_l2g_d); |
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| 324 | rsprouter->p_in[1][4] (signal_dspin_rsp_l2g_c); |
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[189] | 325 | |
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[249] | 326 | // VCI/DSPIN WRAPPERS |
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| 327 | iniwrapperd->p_clk (this->p_clk); |
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| 328 | iniwrapperd->p_resetn (this->p_resetn); |
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| 329 | iniwrapperd->p_vci (signal_vci_l2g_d); |
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| 330 | iniwrapperd->p_dspin_out (signal_dspin_cmd_l2g_d); |
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| 331 | iniwrapperd->p_dspin_in (signal_dspin_rsp_g2l_d); |
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[189] | 332 | |
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[249] | 333 | tgtwrapperd->p_clk (this->p_clk); |
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| 334 | tgtwrapperd->p_resetn (this->p_resetn); |
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| 335 | tgtwrapperd->p_vci (signal_vci_g2l_d); |
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| 336 | tgtwrapperd->p_dspin_out (signal_dspin_rsp_l2g_d); |
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| 337 | tgtwrapperd->p_dspin_in (signal_dspin_cmd_g2l_d); |
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[189] | 338 | |
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[249] | 339 | iniwrapperc->p_clk (this->p_clk); |
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| 340 | iniwrapperc->p_resetn (this->p_resetn); |
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| 341 | iniwrapperc->p_vci (signal_vci_l2g_c); |
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| 342 | iniwrapperc->p_dspin_out (signal_dspin_cmd_l2g_c); |
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| 343 | iniwrapperc->p_dspin_in (signal_dspin_rsp_g2l_c); |
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[189] | 344 | |
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[249] | 345 | tgtwrapperc->p_clk (this->p_clk); |
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| 346 | tgtwrapperc->p_resetn (this->p_resetn); |
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| 347 | tgtwrapperc->p_vci (signal_vci_g2l_c); |
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| 348 | tgtwrapperc->p_dspin_out (signal_dspin_rsp_l2g_c); |
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| 349 | tgtwrapperc->p_dspin_in (signal_dspin_cmd_g2l_c); |
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[189] | 350 | |
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[249] | 351 | // CROSSBAR direct |
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| 352 | xbard->p_clk (this->p_clk); |
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| 353 | xbard->p_resetn (this->p_resetn); |
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| 354 | xbard->p_initiator_to_up (signal_vci_l2g_d); |
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| 355 | xbard->p_target_to_up (signal_vci_g2l_d); |
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[189] | 356 | |
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[249] | 357 | xbard->p_to_target[tgtid_memc] (signal_vci_tgt_d_memc); |
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| 358 | xbard->p_to_target[tgtid_xicu] (signal_vci_tgt_d_xicu); |
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| 359 | xbard->p_to_target[tgtid_mdma] (signal_vci_tgt_d_mdma); |
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[189] | 360 | |
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[249] | 361 | xbard->p_to_initiator[nprocs] (signal_vci_ini_d_mdma); |
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[189] | 362 | |
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[249] | 363 | for (size_t p = 0; p < nprocs; p++){ |
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| 364 | xbard->p_to_initiator[p] (signal_vci_ini_d_proc[p]); |
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| 365 | } |
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[189] | 366 | |
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[249] | 367 | if (io){ |
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| 368 | xbard->p_to_target[tgtid_mtty] (signal_vci_tgt_d_mtty); |
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| 369 | xbard->p_to_target[tgtid_brom] (signal_vci_tgt_d_brom); |
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| 370 | xbard->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev); |
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| 371 | xbard->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf); |
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[189] | 372 | |
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[249] | 373 | xbard->p_to_initiator[nprocs+1] (signal_vci_ini_d_bdev); |
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| 374 | } |
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[189] | 375 | |
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[249] | 376 | // CROSSBAR coherence |
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| 377 | xbarc->p_clk (this->p_clk); |
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| 378 | xbarc->p_resetn (this->p_resetn); |
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| 379 | xbarc->p_initiator_to_up (signal_vci_l2g_c); |
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| 380 | xbarc->p_target_to_up (signal_vci_g2l_c); |
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| 381 | xbarc->p_to_initiator[nprocs] (signal_vci_ini_c_memc); |
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| 382 | xbarc->p_to_target[nprocs] (signal_vci_tgt_c_memc); |
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| 383 | for (size_t p = 0; p < nprocs; p++) { |
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| 384 | xbarc->p_to_target[p] (signal_vci_tgt_c_proc[p]); |
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| 385 | xbarc->p_to_initiator[p] (signal_vci_ini_c_proc[p]); |
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| 386 | } |
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| 387 | |
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| 388 | // Processors |
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| 389 | for (size_t p = 0; p < nprocs; p++){ |
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| 390 | proc[p]->p_clk (this->p_clk); |
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| 391 | proc[p]->p_resetn (this->p_resetn); |
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| 392 | proc[p]->p_vci_ini_d (signal_vci_ini_d_proc[p]); |
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| 393 | proc[p]->p_vci_ini_c (signal_vci_ini_c_proc[p]); |
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| 394 | proc[p]->p_vci_tgt_c (signal_vci_tgt_c_proc[p]); |
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| 395 | proc[p]->p_irq[0] (signal_proc_it[p]); |
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| 396 | for ( size_t j = 1 ; j < 6 ; j++){ |
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| 397 | proc[p]->p_irq[j] (signal_false); |
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| 398 | } |
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| 399 | } |
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| 400 | |
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| 401 | // XICU |
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| 402 | xicu->p_clk (this->p_clk); |
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| 403 | xicu->p_resetn (this->p_resetn); |
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| 404 | xicu->p_vci (signal_vci_tgt_d_xicu); |
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| 405 | for (size_t p = 0; p < nprocs; p++){ |
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| 406 | xicu->p_irq[p] (signal_proc_it[p]); |
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| 407 | } |
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| 408 | for (size_t p = 0; p < nprocs; p++){ |
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| 409 | xicu->p_hwi[p] (signal_irq_mdma[p]); |
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| 410 | } |
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| 411 | for (size_t x = nprocs; x < 4; x++){ |
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| 412 | xicu->p_hwi[x] (signal_false); |
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| 413 | } |
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| 414 | |
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| 415 | if (io){ |
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| 416 | xicu->p_hwi[4] (signal_irq_tty0); |
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| 417 | xicu->p_hwi[5] (signal_irq_tty1); |
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| 418 | xicu->p_hwi[6] (signal_irq_tty2); |
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| 419 | xicu->p_hwi[7] (signal_irq_tty3); |
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| 420 | |
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| 421 | xicu->p_hwi[8] (signal_irq_bdev); |
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| 422 | } |
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| 423 | |
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| 424 | // MEMC |
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| 425 | memc->p_clk (this->p_clk); |
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| 426 | memc->p_resetn (this->p_resetn); |
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| 427 | memc->p_vci_ixr (signal_vci_xram); |
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| 428 | memc->p_vci_tgt (signal_vci_tgt_d_memc); |
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| 429 | memc->p_vci_ini (signal_vci_ini_c_memc); |
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| 430 | memc->p_vci_tgt_cleanup (signal_vci_tgt_c_memc); |
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| 431 | |
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| 432 | // XRAM |
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| 433 | xram->p_clk (this->p_clk); |
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| 434 | xram->p_resetn (this->p_resetn); |
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| 435 | xram->p_vci (signal_vci_xram); |
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| 436 | |
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| 437 | // CDMA |
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| 438 | mdma->p_clk (this->p_clk); |
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| 439 | mdma->p_resetn (this->p_resetn); |
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| 440 | mdma->p_vci_target (signal_vci_tgt_d_mdma); |
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| 441 | mdma->p_vci_initiator (signal_vci_ini_d_mdma); |
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| 442 | for (size_t p = 0; p < nprocs; p++){ |
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| 443 | mdma->p_irq[p] (signal_irq_mdma[p]); |
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| 444 | } |
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| 445 | |
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| 446 | // Components in IO cluster |
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| 447 | |
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| 448 | if (io){ |
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| 449 | // BDEV |
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| 450 | bdev->p_clk (this->p_clk); |
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| 451 | bdev->p_resetn (this->p_resetn); |
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| 452 | bdev->p_irq (signal_irq_bdev); |
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| 453 | bdev->p_vci_target (signal_vci_tgt_d_bdev); |
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| 454 | bdev->p_vci_initiator (signal_vci_ini_d_bdev); |
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| 455 | |
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| 456 | // FBUF |
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| 457 | fbuf->p_clk (this->p_clk); |
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| 458 | fbuf->p_resetn (this->p_resetn); |
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| 459 | fbuf->p_vci (signal_vci_tgt_d_fbuf); |
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| 460 | |
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| 461 | // BROM |
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| 462 | brom->p_clk (this->p_clk); |
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| 463 | brom->p_resetn (this->p_resetn); |
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| 464 | brom->p_vci (signal_vci_tgt_d_brom); |
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| 465 | |
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| 466 | // MTTY |
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| 467 | mtty->p_clk (this->p_clk); |
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| 468 | mtty->p_resetn (this->p_resetn); |
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| 469 | mtty->p_vci (signal_vci_tgt_d_mtty); |
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| 470 | mtty->p_irq[0] (signal_irq_tty0); |
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| 471 | mtty->p_irq[1] (signal_irq_tty1); |
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| 472 | mtty->p_irq[2] (signal_irq_tty2); |
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| 473 | mtty->p_irq[3] (signal_irq_tty3); |
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| 474 | } |
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| 475 | } // end constructor |
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| 476 | |
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[189] | 477 | /////////////////////////////////////////////////////////////////////////// |
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| 478 | // destructor |
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| 479 | /////////////////////////////////////////////////////////////////////////// |
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| 480 | template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> |
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[249] | 481 | TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::~TsarV4ClusterMmu() {} |
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[189] | 482 | |
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[249] | 483 | } |
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| 484 | } |
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| 485 | |
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| 486 | |
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| 487 | // Local Variables: |
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| 488 | // tab-width: 3 |
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| 489 | // c-basic-offset: 3 |
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| 490 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 491 | // indent-tabs-mode: nil |
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| 492 | // End: |
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| 493 | |
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| 494 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
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| 495 | |
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| 496 | |
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| 497 | |
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