| 1 | #include "../include/tsarv4_cluster_ring.h" |
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| 2 | |
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| 3 | namespace soclib { |
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| 4 | namespace caba { |
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| 5 | |
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| 6 | ////////////////////////////////////////////////////////////////////////// |
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| 7 | // Constructor |
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| 8 | ////////////////////////////////////////////////////////////////////////// |
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| 9 | template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> |
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| 10 | TsarV4ClusterRing<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterRing( |
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| 11 | sc_module_name insname, |
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| 12 | size_t nprocs, |
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| 13 | size_t x_id, |
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| 14 | size_t y_id, |
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| 15 | size_t cluster_id, |
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| 16 | const soclib::common::MappingTable &mtd, |
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| 17 | const soclib::common::MappingTable &mtc, |
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| 18 | const soclib::common::MappingTable &mtx, |
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| 19 | size_t x_width, |
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| 20 | size_t y_width, |
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| 21 | size_t tgtid_memc, |
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| 22 | size_t tgtid_xicu, |
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| 23 | size_t tgtid_fbuf, |
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| 24 | size_t tgtid_mtty, |
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| 25 | size_t tgtid_brom, |
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| 26 | size_t tgtid_bdev, |
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| 27 | size_t tgtid_mdma, |
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| 28 | size_t memc_ways, |
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| 29 | size_t memc_sets, |
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| 30 | size_t l1_i_ways, |
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| 31 | size_t l1_i_sets, |
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| 32 | size_t l1_d_ways, |
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| 33 | size_t l1_d_sets, |
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| 34 | size_t xram_latency, |
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| 35 | bool io, |
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| 36 | size_t xfb, |
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| 37 | size_t yfb, |
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| 38 | char* disk_name, |
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| 39 | size_t block_size, |
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| 40 | Loader loader) |
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| 41 | : soclib::caba::BaseModule(insname), |
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| 42 | p_clk("clk"), |
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| 43 | p_resetn("resetn"), |
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| 44 | |
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| 45 | signal_dspin_cmd_l2g_d("signal_dspin_cmd_l2g_d"), |
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| 46 | signal_dspin_cmd_g2l_d("signal_dspin_cmd_g2l_d"), |
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| 47 | signal_dspin_cmd_l2g_c("signal_dspin_cmd_l2g_c"), |
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| 48 | signal_dspin_cmd_g2l_c("signal_dspin_cmd_g2l_c"), |
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| 49 | signal_dspin_rsp_l2g_d("signal_dspin_rsp_l2g_d"), |
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| 50 | signal_dspin_rsp_g2l_d("signal_dspin_rsp_g2l_d"), |
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| 51 | signal_dspin_rsp_l2g_c("signal_dspin_rsp_l2g_c"), |
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| 52 | signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"), |
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| 53 | |
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| 54 | signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"), |
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| 55 | signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"), |
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| 56 | |
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| 57 | signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"), |
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| 58 | signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"), |
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| 59 | signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"), |
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| 60 | signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"), |
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| 61 | signal_vci_tgt_d_mdma("signal_vci_tgt_d_mdma"), |
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| 62 | signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"), |
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| 63 | signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"), |
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| 64 | |
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| 65 | signal_vci_ini_c_memc("signal_vci_ini_c_memc"), |
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| 66 | signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"), |
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| 67 | |
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| 68 | signal_vci_xram("signal_vci_xram") |
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| 69 | |
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| 70 | { |
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| 71 | // Vectors of ports definition |
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| 72 | |
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| 73 | p_cmd_in = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4); |
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| 74 | p_cmd_out = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4); |
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| 75 | p_rsp_in = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4); |
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| 76 | p_rsp_out = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4); |
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| 77 | |
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| 78 | // Components definition |
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| 79 | |
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| 80 | // on direct network : local srcid[proc] in [0...nprocs-1] |
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| 81 | // on direct network : local srcid[mdma] = nprocs |
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| 82 | // on direct network : local srcid[bdev] = nprocs + 1 |
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| 83 | |
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| 84 | // on coherence network : local srcid[proc] in [0...nprocs-1] |
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| 85 | // on coherence network : local srcid[memc] = nprocs |
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| 86 | |
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| 87 | std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; |
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| 88 | |
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| 89 | for ( size_t p=0 ; p<nprocs ; p++ ) |
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| 90 | { |
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| 91 | std::ostringstream sproc; |
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| 92 | sproc << "proc_" << x_id << "_" << y_id << "_" << p; |
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| 93 | proc[p] = new VciCcXCacheWrapperV4<vci_param, iss_t>( |
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| 94 | sproc.str().c_str(), |
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| 95 | cluster_id*nprocs + p, |
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| 96 | mtd, mtc, |
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| 97 | IntTab(cluster_id,p), // SRCID_D |
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| 98 | IntTab(cluster_id,p), // SRCID_C |
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| 99 | IntTab(cluster_id,p), // TGTID_C |
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| 100 | l1_i_ways,l1_i_sets,16, // ICACHE size |
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| 101 | l1_d_ways,l1_d_sets,16, // DCACHE size |
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| 102 | 16, // WBUF width |
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| 103 | 1, // WBUF depth |
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| 104 | 0); // WBUF timeout |
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| 105 | } |
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| 106 | |
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| 107 | std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; |
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| 108 | |
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| 109 | std::ostringstream smemc; |
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| 110 | smemc << "memc_" << x_id << "_" << y_id; |
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| 111 | memc = new VciMemCacheV4<vci_param>( |
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| 112 | smemc.str().c_str(), |
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| 113 | mtd, mtc, mtx, |
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| 114 | IntTab(cluster_id), // SRCID_X |
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| 115 | IntTab(cluster_id, nprocs), // SRCID_C |
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| 116 | IntTab(cluster_id, tgtid_memc), // TGTID_D |
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| 117 | IntTab(cluster_id, nprocs), // TGTID_C |
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| 118 | memc_ways, memc_sets, 16, // CACHE SIZE |
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| 119 | 4096, // HEAP SIZE |
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| 120 | 8, // TRANSACTION TABLE DEPTH |
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| 121 | 8); // UPDATE TABLE DEPTH |
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| 122 | |
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| 123 | |
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| 124 | std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; |
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| 125 | |
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| 126 | std::ostringstream sxram; |
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| 127 | sxram << "xram_" << x_id << "_" << y_id; |
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| 128 | xram = new VciSimpleRam<vci_param>( |
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| 129 | sxram.str().c_str(), |
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| 130 | IntTab(cluster_id), |
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| 131 | mtx, |
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| 132 | loader, |
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| 133 | xram_latency); |
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| 134 | |
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| 135 | std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; |
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| 136 | |
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| 137 | size_t nhwi = 8; // always 8 (or 9) ports, even if |
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| 138 | if( io == true ) nhwi = 9; // there if less than 4 processors |
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| 139 | std::ostringstream sicu; |
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| 140 | sicu << "xicu_" << x_id << "_" << y_id; |
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| 141 | xicu = new VciXicu<vci_param>( |
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| 142 | sicu.str().c_str(), |
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| 143 | mtd, // mapping table |
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| 144 | IntTab(cluster_id, tgtid_xicu), // TGTID_D |
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| 145 | 0, // number of timer IRQs |
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| 146 | nhwi, // number of hard IRQs |
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| 147 | 0, // number of soft IRQs |
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| 148 | nprocs); // number of output IRQs |
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| 149 | |
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| 150 | std::cout << " - building tty_" << x_id << "_" << y_id << std::endl; |
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| 151 | |
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| 152 | // tty |
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| 153 | std::ostringstream stty; |
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| 154 | stty << "tty_" << x_id << "_" << y_id; |
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| 155 | mtty = new VciMultiTty<vci_param>( |
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| 156 | stty.str().c_str(), |
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| 157 | IntTab(cluster_id, tgtid_mtty), |
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| 158 | mtd, stty.str().c_str(), NULL); |
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| 159 | |
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| 160 | std::cout << " - building dma_" << x_id << "_" << y_id << std::endl; |
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| 161 | |
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| 162 | // dma |
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| 163 | std::ostringstream sdma; |
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| 164 | sdma << "dma_" << x_id << "_" << y_id; |
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| 165 | mdma = new VciMultiDma<vci_param>( |
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| 166 | sdma.str().c_str(), |
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| 167 | mtd, |
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| 168 | IntTab(cluster_id, nprocs), // SRCID |
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| 169 | IntTab(cluster_id, tgtid_mdma), // TGTID |
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| 170 | 64, // burst size |
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| 171 | nprocs); // number of IRQs |
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| 172 | |
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| 173 | std::cout << " - building dring_" << x_id << "_" << y_id << std::endl; |
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| 174 | |
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| 175 | // direct ring |
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| 176 | size_t nb_direct_initiators = nprocs + 1; |
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| 177 | size_t nb_direct_targets = 4; |
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| 178 | if( io == true ) |
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| 179 | { |
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| 180 | nb_direct_initiators = nprocs + 2; |
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| 181 | nb_direct_targets = 7; |
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| 182 | } |
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| 183 | std::ostringstream sd; |
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| 184 | sd << "ringd_" << x_id << "_" << y_id; |
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| 185 | ringd = new VciLocalRingFast<vci_param,cmd_width,rsp_width>( |
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| 186 | sd.str().c_str(), |
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| 187 | mtd, |
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| 188 | IntTab(cluster_id), // cluster index |
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| 189 | 4, // wrapper fifo depth |
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| 190 | 4, // gateway fifo depth |
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| 191 | nb_direct_initiators, // number of initiators |
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| 192 | nb_direct_targets); // number of targets |
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| 193 | |
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| 194 | std::cout << " - building cring_" << x_id << "_" << y_id << std::endl; |
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| 195 | |
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| 196 | // coherence ring |
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| 197 | std::ostringstream sc; |
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| 198 | sc << "ringc_" << x_id << "_" << y_id; |
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| 199 | ringc = new VciLocalRingFast<vci_param,cmd_width,rsp_width>( |
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| 200 | sc.str().c_str(), |
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| 201 | mtc, |
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| 202 | IntTab(cluster_id), // cluster index |
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| 203 | 4, // wrapper fifo depth |
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| 204 | 4, // gateway fifo depth |
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| 205 | nprocs + 1, // number of initiators |
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| 206 | nprocs + 1); // number of targets |
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| 207 | |
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| 208 | std::cout << " - building cmdrouter_" << x_id << "_" << y_id << std::endl; |
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| 209 | |
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| 210 | // CMD router |
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| 211 | std::ostringstream scmd; |
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| 212 | scmd << "cmdrouter_" << x_id << "_" << y_id; |
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| 213 | cmdrouter = new VirtualDspinRouter<cmd_width>( |
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| 214 | scmd.str().c_str(), |
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| 215 | x_id,y_id, // coordinate in the mesh |
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| 216 | x_width, y_width, // x & y fields width |
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| 217 | 4,4); // input & output fifo depths |
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| 218 | |
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| 219 | std::cout << " - building rsprouter_" << x_id << "_" << y_id << std::endl; |
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| 220 | |
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| 221 | // RSP router |
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| 222 | std::ostringstream srsp; |
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| 223 | srsp << "rsprouter_" << x_id << "_" << y_id; |
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| 224 | rsprouter = new VirtualDspinRouter<rsp_width>( |
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| 225 | srsp.str().c_str(), |
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| 226 | x_id,y_id, // coordinates in mesh |
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| 227 | x_width, y_width, // x & y fields width |
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| 228 | 4,4); // input & output fifo depths |
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| 229 | |
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| 230 | // IO cluster components |
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| 231 | if ( io == true ) |
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| 232 | { |
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| 233 | brom = new VciSimpleRam<vci_param>( |
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| 234 | "brom", |
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| 235 | IntTab(cluster_id, tgtid_brom), |
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| 236 | mtd, |
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| 237 | loader); |
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| 238 | |
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| 239 | fbuf = new VciFrameBuffer<vci_param>( |
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| 240 | "fbuf", |
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| 241 | IntTab(cluster_id, tgtid_fbuf), |
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| 242 | mtd, |
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| 243 | xfb, yfb); |
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| 244 | |
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| 245 | bdev = new VciBlockDeviceTsarV4<vci_param>( |
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| 246 | "bdev", |
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| 247 | mtd, |
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| 248 | IntTab(cluster_id, nprocs+1), |
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| 249 | IntTab(cluster_id, tgtid_bdev), |
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| 250 | disk_name, |
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| 251 | block_size); |
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| 252 | } |
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| 253 | |
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| 254 | std::cout << " - all components constructed" << std::endl; |
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| 255 | |
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| 256 | //////////////////////////////////// |
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| 257 | // Connections are defined here |
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| 258 | //////////////////////////////////// |
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| 259 | |
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| 260 | // CMDROUTER and RSPROUTER |
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| 261 | cmdrouter->p_clk (this->p_clk); |
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| 262 | cmdrouter->p_resetn (this->p_resetn); |
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| 263 | rsprouter->p_clk (this->p_clk); |
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| 264 | rsprouter->p_resetn (this->p_resetn); |
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| 265 | for(int x = 0; x < 2; x++) |
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| 266 | { |
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| 267 | for(int y = 0; y < 4; y++) |
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| 268 | { |
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| 269 | cmdrouter->p_out[x][y] (this->p_cmd_out[x][y]); |
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| 270 | cmdrouter->p_in[x][y] (this->p_cmd_in[x][y]); |
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| 271 | rsprouter->p_out[x][y] (this->p_rsp_out[x][y]); |
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| 272 | rsprouter->p_in[x][y] (this->p_rsp_in[x][y]); |
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| 273 | } |
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| 274 | } |
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| 275 | |
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| 276 | cmdrouter->p_out[0][4] (signal_dspin_cmd_g2l_d); |
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| 277 | cmdrouter->p_out[1][4] (signal_dspin_cmd_g2l_c); |
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| 278 | cmdrouter->p_in[0][4] (signal_dspin_cmd_l2g_d); |
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| 279 | cmdrouter->p_in[1][4] (signal_dspin_cmd_l2g_c); |
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| 280 | |
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| 281 | rsprouter->p_out[0][4] (signal_dspin_rsp_g2l_d); |
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| 282 | rsprouter->p_out[1][4] (signal_dspin_rsp_g2l_c); |
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| 283 | rsprouter->p_in[0][4] (signal_dspin_rsp_l2g_d); |
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| 284 | rsprouter->p_in[1][4] (signal_dspin_rsp_l2g_c); |
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| 285 | |
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| 286 | // RINGD |
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| 287 | ringd->p_clk (this->p_clk); |
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| 288 | ringd->p_resetn (this->p_resetn); |
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| 289 | ringd->p_gate_cmd_out (signal_dspin_cmd_l2g_d); |
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| 290 | ringd->p_gate_cmd_in (signal_dspin_cmd_g2l_d); |
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| 291 | ringd->p_gate_rsp_out (signal_dspin_rsp_l2g_d); |
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| 292 | ringd->p_gate_rsp_in (signal_dspin_rsp_g2l_d); |
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| 293 | |
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| 294 | ringd->p_to_target[tgtid_memc] (signal_vci_tgt_d_memc); |
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| 295 | ringd->p_to_target[tgtid_xicu] (signal_vci_tgt_d_xicu); |
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| 296 | ringd->p_to_target[tgtid_mtty] (signal_vci_tgt_d_mtty); |
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| 297 | ringd->p_to_target[tgtid_mdma] (signal_vci_tgt_d_mdma); |
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| 298 | |
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| 299 | ringd->p_to_initiator[nprocs] (signal_vci_ini_d_mdma); |
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| 300 | for ( size_t p=0 ; p<nprocs ; p++) |
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| 301 | { |
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| 302 | ringd->p_to_initiator[p] (signal_vci_ini_d_proc[p]); |
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| 303 | } |
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| 304 | |
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| 305 | if ( io == true ) |
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| 306 | { |
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| 307 | ringd->p_to_target[tgtid_brom] (signal_vci_tgt_d_brom); |
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| 308 | ringd->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev); |
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| 309 | ringd->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf); |
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| 310 | |
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| 311 | ringd->p_to_initiator[nprocs+1] (signal_vci_ini_d_bdev); |
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| 312 | } |
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| 313 | |
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| 314 | // RINGC |
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| 315 | ringc->p_clk (this->p_clk); |
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| 316 | ringc->p_resetn (this->p_resetn); |
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| 317 | ringc->p_gate_cmd_out (signal_dspin_cmd_l2g_c); |
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| 318 | ringc->p_gate_cmd_in (signal_dspin_cmd_g2l_c); |
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| 319 | ringc->p_gate_rsp_out (signal_dspin_rsp_l2g_c); |
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| 320 | ringc->p_gate_rsp_in (signal_dspin_rsp_g2l_c); |
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| 321 | ringc->p_to_initiator[nprocs] (signal_vci_ini_c_memc); |
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| 322 | ringc->p_to_target[nprocs] (signal_vci_tgt_c_memc); |
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| 323 | for ( size_t p=0 ; p<nprocs ; p++) |
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| 324 | { |
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| 325 | ringc->p_to_target[p] (signal_vci_tgt_c_proc[p]); |
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| 326 | ringc->p_to_initiator[p] (signal_vci_ini_c_proc[p]); |
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| 327 | } |
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| 328 | |
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| 329 | // Processors |
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| 330 | for ( size_t p=0 ; p<nprocs ; p++) |
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| 331 | { |
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| 332 | proc[p]->p_clk (this->p_clk); |
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| 333 | proc[p]->p_resetn (this->p_resetn); |
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| 334 | proc[p]->p_vci_ini_rw (signal_vci_ini_d_proc[p]); |
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| 335 | proc[p]->p_vci_ini_c (signal_vci_ini_c_proc[p]); |
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| 336 | proc[p]->p_vci_tgt (signal_vci_tgt_c_proc[p]); |
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| 337 | proc[p]->p_irq[0] (signal_proc_it[p]); |
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| 338 | for ( size_t j = 1 ; j < 6 ; j++ ) |
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| 339 | { |
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| 340 | proc[p]->p_irq[j] (signal_false); |
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| 341 | } |
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| 342 | } |
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| 343 | |
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| 344 | // XICU |
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| 345 | xicu->p_clk (this->p_clk); |
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| 346 | xicu->p_resetn (this->p_resetn); |
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| 347 | xicu->p_vci (signal_vci_tgt_d_xicu); |
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| 348 | for ( size_t p=0 ; p<nprocs ; p++) |
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| 349 | { |
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| 350 | xicu->p_irq[p] (signal_proc_it[p]); |
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| 351 | } |
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| 352 | xicu->p_hwi[0] (signal_irq_mtty); |
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| 353 | xicu->p_hwi[1] (signal_false); |
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| 354 | xicu->p_hwi[2] (signal_false); |
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| 355 | xicu->p_hwi[3] (signal_false); |
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| 356 | for ( size_t p=0 ; p<nprocs ; p++) |
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| 357 | { |
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| 358 | xicu->p_hwi[p+4] (signal_irq_mdma[p]); |
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| 359 | } |
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| 360 | for ( size_t x=nprocs ; x<4 ; x++) |
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| 361 | { |
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| 362 | xicu->p_hwi[x+4] (signal_false); |
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| 363 | } |
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| 364 | if ( io == true ) |
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| 365 | { |
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| 366 | xicu->p_hwi[8] (signal_irq_bdev); |
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| 367 | } |
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| 368 | |
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| 369 | // MEMC |
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| 370 | memc->p_clk (this->p_clk); |
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| 371 | memc->p_resetn (this->p_resetn); |
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| 372 | memc->p_vci_ixr (signal_vci_xram); |
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| 373 | memc->p_vci_tgt (signal_vci_tgt_d_memc); |
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| 374 | memc->p_vci_ini (signal_vci_ini_c_memc); |
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| 375 | memc->p_vci_tgt_cleanup (signal_vci_tgt_c_memc); |
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| 376 | |
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| 377 | // XRAM |
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| 378 | xram->p_clk (this->p_clk); |
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| 379 | xram->p_resetn (this->p_resetn); |
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| 380 | xram->p_vci (signal_vci_xram); |
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| 381 | |
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| 382 | // MTTY |
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| 383 | mtty->p_clk (this->p_clk); |
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| 384 | mtty->p_resetn (this->p_resetn); |
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| 385 | mtty->p_vci (signal_vci_tgt_d_mtty); |
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| 386 | mtty->p_irq[0] (signal_irq_mtty); |
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| 387 | |
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| 388 | // CDMA |
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| 389 | mdma->p_clk (this->p_clk); |
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| 390 | mdma->p_resetn (this->p_resetn); |
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| 391 | mdma->p_vci_target (signal_vci_tgt_d_mdma); |
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| 392 | mdma->p_vci_initiator (signal_vci_ini_d_mdma); |
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| 393 | for (size_t p=0 ; p<nprocs ; p++) |
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| 394 | { |
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| 395 | mdma->p_irq[p] (signal_irq_mdma[p]); |
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| 396 | } |
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| 397 | |
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| 398 | // Components in IO cluster |
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| 399 | |
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| 400 | if ( io == true ) |
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| 401 | { |
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| 402 | // BDEV |
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| 403 | bdev->p_clk (this->p_clk); |
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| 404 | bdev->p_resetn (this->p_resetn); |
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| 405 | bdev->p_irq (signal_irq_bdev); |
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| 406 | bdev->p_vci_target (signal_vci_tgt_d_bdev); |
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| 407 | bdev->p_vci_initiator (signal_vci_ini_d_bdev); |
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| 408 | |
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| 409 | // FBUF |
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| 410 | fbuf->p_clk (this->p_clk); |
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| 411 | fbuf->p_resetn (this->p_resetn); |
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| 412 | fbuf->p_vci (signal_vci_tgt_d_fbuf); |
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| 413 | |
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| 414 | // BROM |
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| 415 | brom->p_clk (this->p_clk); |
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| 416 | brom->p_resetn (this->p_resetn); |
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| 417 | brom->p_vci (signal_vci_tgt_d_brom); |
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| 418 | |
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| 419 | } |
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| 420 | } // end constructor |
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| 421 | |
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| 422 | /////////////////////////////////////////////////////////////////////////// |
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| 423 | // destructor |
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| 424 | /////////////////////////////////////////////////////////////////////////// |
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| 425 | template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> |
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| 426 | TsarV4ClusterRing<vci_param, iss_t, cmd_width, rsp_width>::~TsarV4ClusterRing() {} |
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| 427 | |
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| 428 | }} |
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