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source: trunk/platforms/tsarv4_generic_xbar/top.cpp @ 162

Last change on this file since 162 was 156, checked in by alain, 14 years ago
Moving the sof_filter and soft_transpose software applications to the softs directory
File size: 37.0 KB

Line
1	/////////////////////////////////////////////////////////////////////////
2	// File: tsarv4_generic_xbar.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2011
6	// This program is released under the GNU public license
7	/////////////////////////////////////////////////////////////////////////
8	// This file define a generic TSAR architecture without virtual memory.
9	// - It uses vci_local_crossbar as local interconnect
10	// - It uses virtual_dspin as global interconnect
11	// - It uses the vci_cc_xcache_wrapper_v4
12	// - It uses the vci_mem_cache_v4
13	// - It uses the vci_xicu, with one vci_multi_tty, and one
14	// vci_multi_dma controlers per cluster.
15	// The physical address space is 32 bits.
16	// The number of clusters cannot be larger than 256.
17	// The number of processors per cluster cannot be larger than 4.
18	// The parameters must be power of 2.
19	// - xmax : number of clusters in a row
20	// - ymax : number of clusters in a column
21	// - nprocs : number of processors per cluster
22	//
23	// The peripherals BDEV, FBUF, and the boot BROM
24	// are in the cluster containing address 0xBFC00000.
25	// - The nprocs TTY IRQs are connected to IRQ_IN[0] to IRQ_IN[3]
26	// - The nprocs DMA IRQs are connected to IRQ_IN[4] to IRQ_IN[7]
27	// - The IOC IRQ is connected to IRQ_IN[8]
28	//
29	// General policy for 32 bits address decoding in direct space:
30	// All segments base addresses are multiple of 64 Kbytes
31	// Therefore the 16 address MSB bits completely define the target:
32	// The (x_width + y_width) MSB bits (left aligned) define
33	// the cluster index, and the 8 LSB bits define the local index:
34	//
35	// \| X_ID \| Y_ID \|---\| LADR \| OFFSET \|
36	// \|x_width\|y_width\|---\| 8 \| 16 \|
37	//
38	// Half of all clusters being in the protected address space domain
39	// (addresses larger than 0x8000000), software must execute in
40	// kernel mode to access memory if we want to exploit locality,
41	// because some stacks and heaps will be in the protected domain.
42	/////////////////////////////////////////////////////////////////////////
43
44	#include <systemc>
45	#include <sys/time.h>
46	#include <iostream>
47	#include <sstream>
48	#include <cstdlib>
49	#include <cstdarg>
50	#include <stdint.h>
51
52	#include "gdbserver.h"
53	#include "mapping_table.h"
54	#include "tsarv4_cluster_xbar.h"
55	#include "alloc_elems.h"
56
57	///////////////////////////////////////////////////
58	// Parallelisation
59	///////////////////////////////////////////////////
60
61	#define USE_OPENMP 0
62	#define OPENMP_THREADS_NR 8
63
64	#if USE_OPENMP
65	#include <omp.h>
66	#endif
67
68
69	// cluster index (computed from x,y coordinates)
70	#define cluster(x,y) (y + ymax*x)
71
72	// flit widths for the DSPIN network
73	#define cmd_width 40
74	#define rsp_width 33
75
76	// VCI format
77	#define cell_width 4
78	#define address_width 32
79	#define plen_width 8
80	#define error_width 2
81	#define clen_width 1
82	#define rflag_width 1
83	#define srcid_width 14
84	#define pktid_width 4
85	#define trdid_width 4
86	#define wrplen_width 1
87
88	///////////////////////////////////////////////////
89	// Parameters default values
90	///////////////////////////////////////////////////
91
92	#define MESH_XMAX 2
93	#define MESH_YMAX 2
94
95	#define NPROCS 4
96	#define XRAM_LATENCY 0
97
98	#define MEMC_WAYS 16
99	#define MEMC_SETS 256
100
101	#define L1_IWAYS 4
102	#define L1_ISETS 64
103
104	#define L1_DWAYS 4
105	#define L1_DSETS 64
106
107	#define FBUF_X_SIZE 128
108	#define FBUF_Y_SIZE 128
109
110	#define BDEV_SECTOR_SIZE 128
111	#define BDEV_IMAGE_NAME "../../softs/soft_transpose_giet/images.raw"
112
113	#define BOOT_SOFT_NAME "../../softs/soft_transpose_giet/bin.soft"
114
115	/////////////////////////////////////////////////////////
116	// Segments definition
117	/////////////////////////////////////////////////////////
118	// There is 5 segments replicated in all clusters:
119	// - seg_icu -> ICU / LADR = 0xF0
120	// - seg_tty -> MTTY / LADR = 0xF1
121	// - seg_dma -> CDMA / LADR = 0xF2
122	// - seg_stack -> RAM / LADR = 0x80 to 0x8F
123	// - seg_heap -> RAM / LADR = 0x30 to 0x7F
124	//
125	// There is 3 specific segments in the "IO" cluster
126	// (containing address 0xBF000000)
127	// - seg_reset -> BROM / LADR = 0xC0 to 0xCF
128	// - seg_fbuf -> FBUF / LADR = 0xD0 to OxEF
129	// - seg_bdev -> BDEV / LADR = 0xF3
130	//
131	// There is 3 specific segments in the "kcode" cluster
132	// (containing address 0x80000000)
133	// - seg_kcode -> RAM / LADR = 0x00 to 0x0F
134	// - seg_kdata -> RAM / LADR = 0x10 to 0x1F
135	// - seg_kunc -> RAM / LADR = 0x20 to 0x2F
136	//
137	// There is 2 specific segments in the "code" cluster
138	// (containing address 0x00000000)
139	// - seg_code -> RAM / LADR = 0x00 to Ox0F
140	// - seg_data -> RAM / LADR = 0x10 to 0x1F
141	//
142	// There is one special segment corresponding to
143	// the processors in the coherence address space
144	// - seg_proc -> PROCS / LADR = 0xB0 to 0xBF
145	///////////////////////////////////////////////////
146
147	// specific segments in "kcode" cluster
148
149	#define KCOD_BASE 0x80000000
150	#define KCOD_SIZE 0x00010000
151
152	#define KDAT_BASE 0x80100000
153	#define KDAT_SIZE 0x00010000
154
155	#define KUNC_BASE 0x80200000
156	#define KUNC_SIZE 0x00010000
157
158	// specific segments in "code" cluster
159
160	#define CODE_BASE 0x00000000
161	#define CODE_SIZE 0x00010000
162
163	#define DATA_BASE 0x00100000
164	#define DATA_SIZE 0x00010000
165
166	// specific segments in "IO" cluster
167
168	#define BROM_BASE 0xBFC00000
169	#define BROM_SIZE 0x00010000
170
171	#define FBUF_BASE 0xBFD00000
172	#define FBUF_SIZE 0x00200000
173
174	#define BDEV_BASE 0xBFF30000
175	#define BDEV_SIZE 0x00000020
176
177	// replicated segments
178
179	#define HEAP_BASE 0x00300000
180	#define HEAP_SIZE 0x00500000
181
182	#define STAK_BASE 0x00800000
183	#define STAK_SIZE 0x00100000
184
185	#define XICU_BASE 0x00F00000
186	#define XICU_SIZE 0x00001000
187
188	#define MTTY_BASE 0x00F10000
189	#define MTTY_SIZE 0x00000040
190
191	#define CDMA_BASE 0x00F20000
192	#define CDMA_SIZE 0x00000080
193
194	#define PROC_BASE 0x00B00000
195	#define PROC_SIZE 0x00000010
196
197	////////////////////////////////////////////////////////////////////
198	// TGTID definition in direct space
199	// For all components: global TGTID = global SRCID = cluster_index
200	////////////////////////////////////////////////////////////////////
201
202	#define MEMC_TGTID 0
203	#define XICU_TGTID 1
204	#define MTTY_TGTID 2
205	#define CDMA_TGTID 3
206	#define FBUF_TGTID 4
207	#define BROM_TGTID 5
208	#define BDEV_TGTID 6
209
210	///////////////////////////////////////////////////
211	// service functions for VCI & DSIN signal trace
212	//////////////////////////////////////////////////
213
214	template <typename T>
215	void print_vci_signal(std::string name, T &sig)
216	{
217	if ( sig.cmdval )
218	{
219	std::cout << name << std::hex << " CMD VCI : ";
220	if ( sig.cmd.read() == 1 ) std::cout << "RD ";
221	if ( sig.cmd.read() == 2 ) std::cout << "WR ";
222	if ( sig.cmd.read() == 3 ) std::cout << "LL ";
223	if ( sig.cmd.read() == 0 ) std::cout << "SC ";
224	std::cout << " @ = " << sig.address
225	<< " \| wdata = " << sig.wdata
226	<< " \| srcid = " << sig.srcid
227	<< " \| trdid = " << sig.trdid
228	<< " \| eop = " << sig.eop
229	<< " \| ack = " << sig.cmdack << std::endl;
230	}
231	if ( sig.rspval )
232	{
233	std::cout << name << std::hex
234	<< " RSP VCI : rerror = " << sig.rerror
235	<< " \| rdata = " << sig.rdata
236	<< " \| rsrcid = " << sig.rsrcid
237	<< " \| rtrdid = " << sig.rtrdid
238	<< " \| reop = " << sig.reop
239	<< " \| ack = " << sig.rspack << std::endl;
240	}
241	}
242
243	template <typename T>
244	void print_dspin_signal(std::string name, T &sig)
245	{
246	if ( sig.write )
247	{
248	std::cout << name << " DSPIN : data = " << std::hex << sig.data
249	<< " \| ack = " << sig.read << std::endl;
250	}
251	}
252
253	/////////////////////////////////
254	int _main(int argc, char *argv[])
255	{
256	using namespace sc_core;
257	using namespace soclib::caba;
258	using namespace soclib::common;
259
260
261	char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code
262	size_t ncycles = 1000000000; // simulated cycles
263	size_t xmax = MESH_XMAX; // number of clusters in a row
264	size_t ymax = MESH_YMAX; // number of clusters in a column
265	size_t nprocs = NPROCS; // number of processors per cluster
266	size_t xfb = FBUF_X_SIZE; // frameBuffer column number
267	size_t yfb = FBUF_Y_SIZE; // frameBuffer lines number
268	size_t memc_ways = MEMC_WAYS;
269	size_t memc_sets = MEMC_SETS;
270	size_t l1_d_ways = L1_DWAYS;
271	size_t l1_d_sets = L1_DSETS;
272	size_t l1_i_ways = L1_IWAYS;
273	size_t l1_i_sets = L1_ISETS;
274	char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image
275	size_t blk_size = BDEV_SECTOR_SIZE; // block size (in bytes)
276	size_t xram_latency = XRAM_LATENCY; // external RAM latency
277	bool trace_ok = false; // debug activated
278	size_t from_cycle = 0; // debug start cycle
279
280	////////////// command line arguments //////////////////////
281	if (argc > 1)
282	{
283	for( int n=1 ; n<argc ; n=n+2 )
284	{
285	if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
286	{
287	ncycles = atoi(argv[n+1]);
288	}
289	else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) )
290	{
291	nprocs = atoi(argv[n+1]);
292	assert( ((nprocs == 1) \|\| (nprocs == 2) \|\| (nprocs == 4)) &&
293	"NPROCS must be equal to 1, 2, or 4");
294	}
295	else if( (strcmp(argv[n],"-XMAX") == 0) && (n+1<argc) )
296	{
297	xmax = atoi(argv[n+1]);
298	assert( ((xmax == 1) \|\| (xmax == 2) \|\| (xmax == 4) \|\| (xmax == 8) \|\| (xmax == 16))
299	&& "The XMAX parameter must be 2, 4, 8, or 16" );
300	}
301
302	else if( (strcmp(argv[n],"-YMAX") == 0) && (n+1<argc) )
303	{
304	ymax = atoi(argv[n+1]);
305	assert( ((ymax == 1) \|\| (ymax == 2) \|\| (ymax == 4) \|\| (ymax == 8) \|\| (ymax == 16))
306	&& "The YMAX parameter must be 2, 4, 8, or 16" );
307	}
308	else if( (strcmp(argv[n],"-XFB") == 0) && (n+1<argc) )
309	{
310	xfb = atoi(argv[n+1]);
311	}
312	else if( (strcmp(argv[n],"-YFB") == 0) && (n+1<argc) )
313	{
314	yfb = atoi(argv[n+1]);
315	}
316	else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
317	{
318	strcpy(soft_name, argv[n+1]);
319	}
320	else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
321	{
322	strcpy(disk_name, argv[n+1]);
323	}
324	else if( (strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) )
325	{
326	trace_ok = true;
327	from_cycle = atoi(argv[n+1]);
328	}
329	else if((strcmp(argv[n], "-MCWAYS") == 0) && (n+1 < argc))
330	{
331	memc_ways = atoi(argv[n+1]);
332	}
333	else if((strcmp(argv[n], "-MCSETS") == 0) && (n+1 < argc))
334	{
335	memc_sets = atoi(argv[n+1]);
336	}
337	else if((strcmp(argv[n], "-XLATENCY") == 0) && (n+1 < argc))
338	{
339	xram_latency = atoi(argv[n+1]);
340	}
341	else
342	{
343	std::cout << " Arguments on the command line are (key,value) couples." << std::endl;
344	std::cout << " The order is not important." << std::endl;
345	std::cout << " Accepted arguments are :" << std::endl << std::endl;
346	std::cout << " -SOFT pathname_for_embedded_soft" << std::endl;
347	std::cout << " -DISK pathname_for_disk_image" << std::endl;
348	std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
349	std::cout << " -NPROCS number_of_processors_per_cluster" << std::endl;
350	std::cout << " -XMAX number_of_clusters_in_a_row" << std::endl;
351	std::cout << " -YMAX number_of_clusters_in_a_column" << std::endl;
352	std::cout << " -TRACE debug_start_cycle" << std::endl;
353	std::cout << " -MCWAYS memory_cache_number_of_ways" << std::endl;
354	std::cout << " -MCSETS memory_cache_number_of_sets" << std::endl;
355	std::cout << " -XLATENCY external_ram_latency_value" << std::endl;
356	std::cout << " -XFB fram_buffer_number_of_pixels" << std::endl;
357	std::cout << " -YFB fram_buffer_number_of_lines" << std::endl;
358	exit(0);
359	}
360	}
361	}
362
363	std::cout << std::endl;
364	std::cout << " - NPROCS = " << nprocs << std::endl;
365	std::cout << " - NCLUSTERS = " << xmax*ymax << std::endl;
366	std::cout << std::endl;
367
368	#if USE_OPENMP
369	omp_set_dynamic(false);
370	omp_set_num_threads(threads_nr);
371	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
372	#endif
373
374	// Define VCI parameters
375	typedef soclib::caba::VciParams<cell_width,
376	plen_width,
377	address_width,
378	error_width,
379	clen_width,
380	rflag_width,
381	srcid_width,
382	pktid_width,
383	trdid_width,
384	wrplen_width> vci_param;
385
386	size_t cluster_io_index;
387	size_t cluster_code_index;
388	size_t cluster_kcode_index;
389	size_t x_width;
390	size_t y_width;
391
392	if (xmax == 1) x_width = 0;
393	else if (xmax == 2) x_width = 1;
394	else if (xmax <= 4) x_width = 2;
395	else if (xmax <= 8) x_width = 3;
396	else x_width = 4;
397
398	if (ymax == 1) y_width = 0;
399	else if (ymax == 2) y_width = 1;
400	else if (ymax <= 4) y_width = 2;
401	else if (ymax <= 8) y_width = 3;
402	else y_width = 4;
403
404	cluster_io_index = 0xBF >> (8 - x_width - y_width);
405	cluster_kcode_index = 0x80 >> (8 - x_width - y_width);
406	cluster_code_index = 0;
407
408	/////////////////////
409	// Mapping Tables
410	/////////////////////
411
412	// direct network
413	MappingTable maptabd(address_width,
414	IntTab(x_width + y_width, 16 - x_width - y_width),
415	IntTab(x_width + y_width, srcid_width - x_width - y_width),
416	0x00FF0000);
417
418	for ( size_t x = 0 ; x < xmax ; x++)
419	{
420	for ( size_t y = 0 ; y < ymax ; y++)
421	{
422	sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width);
423
424	std::ostringstream sh;
425	sh << "d_seg_heap_" << x << "_" << y;
426	maptabd.add(Segment(sh.str(), HEAP_BASE+offset, HEAP_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
427
428	std::ostringstream ss;
429	ss << "d_seg_stak_" << x << "_" << y;
430	maptabd.add(Segment(ss.str(), STAK_BASE+offset, STAK_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
431
432	std::ostringstream si;
433	si << "d_seg_xicu_" << x << "_" << y;
434	maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false));
435
436	std::ostringstream st;
437	st << "d_seg_mtty_" << x << "_" << y;
438	maptabd.add(Segment(st.str(), MTTY_BASE+offset, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false));
439
440	std::ostringstream sd;
441	sd << "d_seg_cdma_" << x << "_" << y;
442	maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false));
443
444	if ( cluster(x,y) == cluster_io_index )
445	{
446	maptabd.add(Segment("d_seg_fbuf ", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false));
447	maptabd.add(Segment("d_seg_bdev ", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false));
448	maptabd.add(Segment("d_seg_brom ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true));
449	}
450	if ( cluster(x,y) == cluster_code_index )
451	{
452	maptabd.add(Segment("d_seg_code ", CODE_BASE, CODE_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
453	maptabd.add(Segment("d_seg_data ", DATA_BASE, DATA_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
454	}
455	if ( cluster(x,y) == cluster_kcode_index )
456	{
457	maptabd.add(Segment("d_seg_kcod ", KCOD_BASE, KCOD_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
458	maptabd.add(Segment("d_seg_kdat ", KDAT_BASE, KDAT_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
459	maptabd.add(Segment("d_seg_kunc ", KUNC_BASE, KUNC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
460	}
461	}
462	}
463	std::cout << maptabd << std::endl;
464
465	// coherence network
466	// - tgtid_c_proc = srcid_c_proc = local procid
467	// - tgtid_c_memc = srcid_c_memc = nprocs
468	MappingTable maptabc(address_width,
469	IntTab(x_width + y_width, 16 - x_width - y_width),
470	IntTab(x_width + y_width, srcid_width - x_width - y_width),
471	0x00FF0000);
472
473	for ( size_t x = 0 ; x < xmax ; x++)
474	{
475	for ( size_t y = 0 ; y < ymax ; y++)
476	{
477	sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width);
478
479	// cleanup requests regarding the heap segment must be routed to the memory cache
480	std::ostringstream sh;
481	sh << "c_seg_heap_" << x << "_" << y;
482	maptabc.add(Segment(sh.str(), HEAP_BASE+offset, HEAP_SIZE, IntTab(cluster(x,y), nprocs), false));
483
484	// cleanup requests regarding the stack segmentmust be routed to the memory cache
485	std::ostringstream ss;
486	ss << "c_seg_stak_" << x << "_" << y;
487	maptabc.add(Segment(ss.str(), STAK_BASE+offset, STAK_SIZE, IntTab(cluster(x,y), nprocs), false));
488
489	// cleanup requests regarding the BROM segment are also be routed to the memory cache
490	if ( cluster(x,y) == cluster_io_index )
491	{
492	maptabc.add(Segment("c_seg_brom ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y), nprocs), false));
493	}
494
495	// cleanup requests regarding the code and data segment musts be send to the memory cache
496	if ( cluster(x,y) == cluster_code_index )
497	{
498	maptabc.add(Segment("c_seg_code ", CODE_BASE, CODE_SIZE, IntTab(cluster(x,y), nprocs), false));
499	maptabc.add(Segment("c_seg_data ", DATA_BASE, DATA_SIZE, IntTab(cluster(x,y), nprocs), false));
500	}
501	// cleanup requests regarding the kcode, kunc, and kdata segments must be send to the memory cache
502	if ( cluster(x,y) == cluster_kcode_index )
503	{
504	maptabc.add(Segment("c_seg_kcod ", KCOD_BASE, KCOD_SIZE, IntTab(cluster(x,y), nprocs), false));
505	maptabc.add(Segment("c_seg_kdat ", KDAT_BASE, KDAT_SIZE, IntTab(cluster(x,y), nprocs), false));
506	maptabc.add(Segment("c_seg_kunc ", KUNC_BASE, KUNC_SIZE, IntTab(cluster(x,y), nprocs), false));
507	}
508
509	// update & invalidate requests must be routed to the proper processor
510	for ( size_t p = 0 ; p < nprocs ; p++)
511	{
512	std::ostringstream sp;
513	sp << "c_seg_proc_" << x << "_" << y << "_" << p;
514	maptabc.add(Segment(sp.str(), PROC_BASE+offset+(p*0x10000), PROC_SIZE,
515	IntTab(cluster(x,y), p), false, true, IntTab(cluster(x,y), p)));
516	}
517	}
518	}
519	std::cout << maptabc << std::endl;
520
521	// external network
522	MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000);
523
524	for ( size_t x = 0 ; x < xmax ; x++)
525	{
526	for ( size_t y = 0 ; y < ymax ; y++)
527	{
528
529	sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width);
530
531	std::ostringstream sh;
532	sh << "x_seg_heap_" << x << "_" << y;
533	maptabx.add(Segment(sh.str(), HEAP_BASE+offset, HEAP_SIZE, IntTab(cluster(x,y)), false));
534
535	std::ostringstream ss;
536	ss << "x_seg_stak_" << x << "_" << y;
537	maptabx.add(Segment(ss.str(), STAK_BASE+offset, STAK_SIZE, IntTab(cluster(x,y)), false));
538
539	if ( cluster(x,y) == cluster_code_index )
540	{
541	maptabx.add(Segment("x_seg_code ", CODE_BASE, CODE_SIZE, IntTab(cluster(x,y)), false));
542	maptabx.add(Segment("x_seg_data ", DATA_BASE, DATA_SIZE, IntTab(cluster(x,y)), false));
543	}
544	if ( cluster(x,y) == cluster_kcode_index )
545	{
546	maptabx.add(Segment("x_seg_kcod ", KCOD_BASE, KCOD_SIZE, IntTab(cluster(x,y)), false));
547	maptabx.add(Segment("x_seg_kdat ", KDAT_BASE, KDAT_SIZE, IntTab(cluster(x,y)), false));
548	maptabx.add(Segment("x_seg_kunc ", KUNC_BASE, KUNC_SIZE, IntTab(cluster(x,y)), false));
549	}
550	}
551	}
552	std::cout << maptabx << std::endl;
553
554	////////////////////
555	// Signals
556	///////////////////
557
558	sc_clock signal_clk("clk");
559	sc_signal<bool> signal_resetn("resetn");
560
561	// Horizontal inter-clusters DSPIN signals
562	DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc =
563	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", xmax-1, ymax, 2);
564	DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec =
565	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", xmax-1, ymax, 2);
566	DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc =
567	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2);
568	DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec =
569	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2);
570
571	// Vertical inter-clusters DSPIN signals
572	DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc =
573	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", xmax, ymax-1, 2);
574	DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec =
575	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", xmax, ymax-1, 2);
576	DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc =
577	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2);
578	DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec =
579	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2);
580
581	// Mesh boundaries DSPIN signals
582	DspinSignals<cmd_width>**** signal_dspin_false_cmd_in =
583	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", xmax, ymax, 2, 4);
584	DspinSignals<cmd_width>**** signal_dspin_false_cmd_out =
585	alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", xmax, ymax, 2, 4);
586	DspinSignals<rsp_width>**** signal_dspin_false_rsp_in =
587	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", xmax, ymax, 2, 4);
588	DspinSignals<rsp_width>**** signal_dspin_false_rsp_out =
589	alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", xmax, ymax, 2, 4);
590
591
592	////////////////////////////
593	// Components
594	////////////////////////////
595
596	#if USE_ALMOS
597	soclib::common::Loader loader("bootloader.bin",
598	"arch-info.bin@"TO_STR(BOOT_INFO_BLOCK)":D",
599	"kernel-soclib.bin@"TO_STR(KERNEL_BIN_IMG)":D");
600	#else
601	soclib::common::Loader loader(soft_name);
602	#endif
603
604	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
605	proc_iss::set_loader(loader);
606
607	TsarV4ClusterXbar<vci_param, proc_iss, cmd_width, rsp_width>* clusters[xmax][ymax];
608
609	#if USE_OPENMP
610
611	#pragma omp parallel
612	{
613	#pragma omp for
614	for( size_t i = 0 ; i < (xmax * ymax); i++)
615	{
616	size_t x = i / ymax;
617	size_t y = i % ymax;
618
619	#pragma omp critical
620	std::ostringstream sc;
621	sc << "cluster_" << x << "_" << y;
622	clusters[x][y] = new TsarV4ClusterXbar<vci_param, proc_iss, cmd_width, rsp_width>
623	(sc.str().c_str(),
624	nprocs,
625	x,
626	y,
627	cluster(x,y),
628	maptabd,
629	maptabc,
630	maptabx,
631	x_width,
632	y_width,
633	MEMC_TGTID,
634	XICU_TGTID,
635	FBUF_TGTID,
636	MTTY_TGTID,
637	BROM_TGTID,
638	BDEV_TGTID,
639	CDMA_TGTID,
640	memc_ways,
641	memc_sets,
642	l1_i_ways,
643	l1_i_sets,
644	l1_d_ways,
645	l1_d_sets,
646	xram_latency,
647	(cluster(x,y) == cluster_io_index),
648	xfb,
649	yfb,
650	disk_name,
651	blk_size,
652	loader);
653	}
654
655	#else // USE_OPENMP
656
657	for( size_t x = 0 ; x < xmax ; x++)
658	{
659	for( size_t y = 0 ; y < ymax ; y++ )
660	{
661
662	std::cout << "building cluster_" << x << "_" << y << std::endl;
663
664	std::ostringstream sc;
665	sc << "cluster_" << x << "_" << y;
666	clusters[x][y] = new TsarV4ClusterXbar<vci_param, proc_iss, cmd_width, rsp_width>
667	(sc.str().c_str(),
668	nprocs,
669	x,
670	y,
671	cluster(x,y),
672	maptabd,
673	maptabc,
674	maptabx,
675	x_width,
676	y_width,
677	MEMC_TGTID,
678	XICU_TGTID,
679	FBUF_TGTID,
680	MTTY_TGTID,
681	BROM_TGTID,
682	BDEV_TGTID,
683	CDMA_TGTID,
684	memc_ways,
685	memc_sets,
686	l1_i_ways,
687	l1_i_sets,
688	l1_d_ways,
689	l1_d_sets,
690	xram_latency,
691	(cluster(x,y) == cluster_io_index),
692	xfb,
693	yfb,
694	disk_name,
695	blk_size,
696	loader);
697
698	std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl;
699
700	}
701	}
702
703	#endif // USE_OPENMP
704
705	///////////////////////////////////////////////////////////////
706	// Net-list
707	///////////////////////////////////////////////////////////////
708
709	// Clock & RESET
710	for ( size_t x = 0 ; x < (xmax) ; x++ )
711	{
712	for ( size_t y = 0 ; y < ymax ; y++ )
713	{
714	clusters[x][y]->p_clk (signal_clk);
715	clusters[x][y]->p_resetn (signal_resetn);
716	}
717	}
718
719	// Inter Clusters horizontal connections
720	if ( xmax > 1 )
721	{
722	for ( size_t x = 0 ; x < (xmax-1) ; x++ )
723	{
724	for ( size_t y = 0 ; y < ymax ; y++ )
725	{
726	for ( size_t k = 0 ; k < 2 ; k++ )
727	{
728	clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]);
729	clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]);
730	clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]);
731	clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]);
732	clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]);
733	clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]);
734	clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]);
735	clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]);
736	}
737	}
738	}
739	}
740	std::cout << "Horizontal connections established" << std::endl;
741
742	// Inter Clusters vertical connections
743	if ( ymax > 1 )
744	{
745	for ( size_t y = 0 ; y < (ymax-1) ; y++ )
746	{
747	for ( size_t x = 0 ; x < xmax ; x++ )
748	{
749	for ( size_t k = 0 ; k < 2 ; k++ )
750	{
751	clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]);
752	clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]);
753	clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]);
754	clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]);
755	clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]);
756	clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]);
757	clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]);
758	clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]);
759	}
760	}
761	}
762	}
763	std::cout << "Vertical connections established" << std::endl;
764
765	// East & West boundary cluster connections
766	for ( size_t y = 0 ; y < ymax ; y++ )
767	{
768	for ( size_t k = 0 ; k < 2 ; k++ )
769	{
770	clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]);
771	clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]);
772	clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]);
773	clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]);
774
775	clusters[xmax-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[xmax-1][y][k][EAST]);
776	clusters[xmax-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[xmax-1][y][k][EAST]);
777	clusters[xmax-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[xmax-1][y][k][EAST]);
778	clusters[xmax-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[xmax-1][y][k][EAST]);
779	}
780	}
781
782	// North & South boundary clusters connections
783	for ( size_t x = 0 ; x < xmax ; x++ )
784	{
785	for ( size_t k = 0 ; k < 2 ; k++ )
786	{
787	clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]);
788	clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]);
789	clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]);
790	clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]);
791
792	clusters[x][ymax-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][ymax-1][k][NORTH]);
793	clusters[x][ymax-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][ymax-1][k][NORTH]);
794	clusters[x][ymax-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][ymax-1][k][NORTH]);
795	clusters[x][ymax-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][ymax-1][k][NORTH]);
796	}
797	}
798
799
800	////////////////////////////////////////////////////////
801	// Simulation
802	///////////////////////////////////////////////////////
803
804	sc_start(sc_core::sc_time(0, SC_NS));
805	signal_resetn = false;
806
807	// network boundaries signals
808	for(size_t x=0; x<xmax ; x++)
809	{
810	for(size_t y=0 ; y<ymax ; y++)
811	{
812	for (size_t k=0; k<2; k++)
813	{
814	for(size_t a=0; a<4; a++)
815	{
816	signal_dspin_false_cmd_in[x][y][k][a].write = false;
817	signal_dspin_false_cmd_in[x][y][k][a].read = true;
818	signal_dspin_false_cmd_out[x][y][k][a].write = false;
819	signal_dspin_false_cmd_out[x][y][k][a].read = true;
820
821	signal_dspin_false_rsp_in[x][y][k][a].write = false;
822	signal_dspin_false_rsp_in[x][y][k][a].read = true;
823	signal_dspin_false_rsp_out[x][y][k][a].write = false;
824	signal_dspin_false_rsp_out[x][y][k][a].read = true;
825	}
826	}
827	}
828	}
829
830	sc_start(sc_core::sc_time(1, SC_NS));
831	signal_resetn = true;
832
833	for ( size_t n=0 ; n<ncycles ; n++)
834	{
835	sc_start(sc_core::sc_time(1, SC_NS));
836	if ( trace_ok && (n > from_cycle) )
837	{
838	std::cout << "****************** cycle " << std::dec << n ;
839	std::cout << " ***********************************" << std::endl;
840	/*
841	clusters[0][0]->proc[0]->print_trace();
842	clusters[0][0]->proc[1]->print_trace();
843	clusters[0][0]->proc[2]->print_trace();
844	clusters[0][0]->proc[3]->print_trace();
845
846	std::cout << std::endl;
847
848	clusters[0][1]->proc[0]->print_trace();
849	clusters[0][1]->proc[1]->print_trace();
850	clusters[0][1]->proc[2]->print_trace();
851	clusters[0][1]->proc[3]->print_trace();
852
853	std::cout << std::endl;
854
855	clusters[1][0]->proc[0]->print_trace();
856	clusters[1][0]->proc[1]->print_trace();
857	*/
858	clusters[1][0]->iniwrapperd->print_trace();
859	clusters[1][0]->proc[2]->print_trace();
860	print_vci_signal("proc_1_0_2_tgt_c", clusters[1][0]->signal_vci_tgt_c_proc[2]);
861	print_vci_signal("proc_1_0_2_d", clusters[1][0]->signal_vci_ini_d_proc[2]);
862	print_vci_signal("memc_0_0_d", clusters[0][0]->signal_vci_tgt_d_memc);
863	print_vci_signal("g2l_0_0_d", clusters[0][0]->signal_vci_g2l_d);
864	print_dspin_signal("l2g_0_0_d RSP", clusters[0][0]->signal_dspin_rsp_l2g_d);
865	print_dspin_signal("c10_to_c00 RSP", signal_dspin_h_rsp_dec[0][0][0]);
866	print_dspin_signal("c00_to_c10 RSP", signal_dspin_h_rsp_inc[0][0][0]);
867	print_dspin_signal("g2l_1_0_d RSP", clusters[1][0]->signal_dspin_rsp_g2l_d);
868	print_vci_signal("l2g_1_0_d", clusters[1][0]->signal_vci_l2g_d);
869	/*
870	clusters[1][0]->proc[3]->print_trace();
871
872	std::cout << std::endl;
873
874	clusters[1][1]->proc[0]->print_trace();
875	clusters[1][1]->proc[1]->print_trace();
876	clusters[1][1]->proc[2]->print_trace();
877	clusters[1][1]->proc[3]->print_trace();
878
879	std::cout << std::endl;
880
881	clusters[0][0]->memc->print_trace();
882	clusters[0][1]->memc->print_trace();
883	clusters[1][0]->memc->print_trace();
884	clusters[1][1]->memc->print_trace();
885
886	clusters[0][0]->iniwrapperd->print_trace();
887	clusters[0][0]->tgtwrapperd->print_trace();
888	clusters[1][0]->iniwrapperd->print_trace();
889	clusters[1][0]->tgtwrapperd->print_trace();
890	clusters[0][1]->iniwrapperd->print_trace();
891	clusters[0][1]->tgtwrapperd->print_trace();
892	clusters[1][1]->iniwrapperd->print_trace();
893	clusters[1][1]->tgtwrapperd->print_trace();
894
895	std::cout << std::endl;
896
897	print_vci_signal("proc_0_0_0_d", clusters[0][0]->signal_vci_ini_d_proc[0]);
898	print_vci_signal("proc_1_0_0_d", clusters[1][0]->signal_vci_ini_d_proc[0]);
899	print_vci_signal("proc_0_1_0_d", clusters[0][1]->signal_vci_ini_d_proc[0]);
900	print_vci_signal("proc_1_1_0_d", clusters[1][1]->signal_vci_ini_d_proc[0]);
901
902	print_vci_signal("proc_0_0_0_c", clusters[0][0]->signal_vci_tgt_c_proc[0]);
903	print_vci_signal("proc_1_0_0_c", clusters[1][0]->signal_vci_tgt_c_proc[0]);
904	print_vci_signal("proc_0_1_0_c", clusters[0][1]->signal_vci_tgt_c_proc[0]);
905	print_vci_signal("proc_1_1_0_c", clusters[1][1]->signal_vci_tgt_c_proc[0]);
906
907	print_vci_signal("memc_0_0_d", clusters[0][0]->signal_vci_tgt_d_memc);
908	print_vci_signal("memc_1_0_d", clusters[1][0]->signal_vci_tgt_d_memc);
909	print_vci_signal("memc_0_1_d", clusters[0][1]->signal_vci_tgt_d_memc);
910	print_vci_signal("memc_1_1_d", clusters[1][1]->signal_vci_tgt_d_memc);
911
912	print_vci_signal("memc_1_0_ini_c", clusters[1][0]->signal_vci_ini_c_memc);
913
914	print_vci_signal("l2g_1_0_c", clusters[1][0]->signal_vci_l2g_c);
915
916	print_dspin_signal("l2g_1_0_c CMD", clusters[1][0]->signal_dspin_cmd_l2g_c);
917
918	print_vci_signal("l2g_0_0_d", clusters[0][0]->signal_vci_l2g_d);
919	print_vci_signal("g2l_0_0_d", clusters[0][0]->signal_vci_g2l_d);
920
921	print_vci_signal("l2g_1_0_d", clusters[1][0]->signal_vci_l2g_d);
922	print_vci_signal("g2l_1_0_d", clusters[1][0]->signal_vci_g2l_d);
923
924	print_dspin_signal("l2g_0_0_d CMD", clusters[0][0]->signal_dspin_cmd_l2g_d);
925	print_dspin_signal("g2l_0_0_d CMD", clusters[0][0]->signal_dspin_cmd_g2l_d);
926	print_dspin_signal("l2g_0_0_d RSP", clusters[0][0]->signal_dspin_rsp_l2g_d);
927	print_dspin_signal("g2l_0_0_d RSP", clusters[0][0]->signal_dspin_rsp_g2l_d);
928
929	print_dspin_signal("l2g_1_0_d CMD", clusters[1][0]->signal_dspin_cmd_l2g_d);
930	print_dspin_signal("g2l_1_0_d CMD", clusters[1][0]->signal_dspin_cmd_g2l_d);
931	print_dspin_signal("l2g_1_0_d RSP", clusters[1][0]->signal_dspin_rsp_l2g_d);
932	print_dspin_signal("g2l_1_0_d RSP", clusters[1][0]->signal_dspin_rsp_g2l_d);
933
934	print_vci_signal("bdev_tgt", clusters[1][0]->signal_vci_tgt_d_bdev);
935	print_vci_signal("bdev_ini", clusters[1][0]->signal_vci_ini_d_bdev);
936
937	print_vci_signal("brom_tgt", clusters[1][0]->signal_vci_tgt_d_brom);
938
939	if ( clusters[0][0]->signal_irq_bdev.read() != 0) std::cout << " IRQ_BDEV" << std::endl;
940	if ( clusters[0][0]->signal_proc_it[0].read() != 0) std::cout << " IRQ_PROC" << std::endl;
941	*/
942	}
943	}
944	return EXIT_SUCCESS;
945	}
946
947	int sc_main (int argc, char *argv[])
948	{
949	try {
950	return _main(argc, argv);
951	} catch (std::exception &e) {
952	std::cout << e.what() << std::endl;
953	} catch (...) {
954	std::cout << "Unknown exception occured" << std::endl;
955	throw;
956	}
957	return 1;
958	}

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