[154] | 1 | |
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| 2 | # -*- python -*- |
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| 3 | |
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| 4 | Module('caba:tsarv4_cluster_xbar', |
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| 5 | classname = 'soclib::caba::TsarV4ClusterXbar', |
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| 6 | tmpl_parameters = [ |
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| 7 | parameter.Module('vci_param', default = 'caba:vci_param'), |
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| 8 | parameter.Module('iss_t'), |
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| 9 | parameter.Int('cmd_width'), |
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| 10 | parameter.Int('rsp_width'), |
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| 11 | ], |
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| 12 | header_files = [ '../source/include/tsarv4_cluster_xbar.h', ], |
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| 13 | implementation_files = [ '../source/src/tsarv4_cluster_xbar.cpp', ], |
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| 14 | uses = [ |
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| 15 | Uses('caba:base_module'), |
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| 16 | Uses('common:mapping_table'), |
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| 17 | Uses('common:iss2'), |
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| 18 | Uses('caba:vci_cc_xcache_wrapper_v4', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:mips32el'), |
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| 19 | Uses('caba:vci_mem_cache_v4'), |
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| 20 | Uses('caba:vci_simple_ram'), |
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| 21 | Uses('caba:vci_xicu'), |
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| 22 | Uses('caba:vci_local_crossbar'), |
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| 23 | Uses('caba:virtual_dspin_router', flit_width = parameter.Reference('cmd_width')), |
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| 24 | Uses('caba:virtual_dspin_router', flit_width = parameter.Reference('rsp_width')), |
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| 25 | Uses('caba:vci_vdspin_target_wrapper', dspin_cmd_width = parameter.Reference('cmd_width'), |
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| 26 | dspin_rsp_width = parameter.Reference('rsp_width')), |
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| 27 | Uses('caba:vci_vdspin_initiator_wrapper', dspin_cmd_width = parameter.Reference('cmd_width'), |
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| 28 | dspin_rsp_width = parameter.Reference('rsp_width')), |
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| 29 | Uses('caba:vci_multi_tty'), |
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| 30 | Uses('caba:vci_framebuffer'), |
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| 31 | Uses('caba:vci_block_device_tsar_v4'), |
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| 32 | Uses('caba:vci_multi_dma'), |
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| 33 | Uses('common:elf_file_loader'), |
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| 34 | ], |
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| 35 | instance_parameters = [ |
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| 36 | parameter.Int('n_x'), |
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| 37 | parameter.Int('n_y'), |
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| 38 | parameter.Int('n_cluster'), |
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| 39 | parameter.Module('mtd', 'common:mapping_table'), |
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| 40 | parameter.Module('mtc', 'common:mapping_table'), |
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| 41 | parameter.Module('mtx', 'common:mapping_table'), |
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| 42 | parameter.Int('x_width'), |
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| 43 | parameter.Int('y_width'), |
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| 44 | parameter.Int('memc_tgtid'), |
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| 45 | parameter.Int('xicu_tgtid'), |
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| 46 | parameter.Int('fbuf_tgtid'), |
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| 47 | parameter.Int('mtty_tgtid'), |
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| 48 | parameter.Int('brom_tgtid'), |
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| 49 | parameter.Int('bdev_tgtid'), |
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| 50 | parameter.Int('cdma_tgtid'), |
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| 51 | parameter.Int('memc_ways'), |
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| 52 | parameter.Int('memc_sets'), |
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| 53 | parameter.Int('l1_i_ways'), |
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| 54 | parameter.Int('l1_i_sets'), |
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| 55 | parameter.Int('l1_d_ways'), |
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| 56 | parameter.Int('l1_d_sets'), |
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| 57 | parameter.Int('xram_latency'), |
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| 58 | parameter.Bool('io'), |
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| 59 | ], |
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| 60 | |
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| 61 | ports = [ |
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| 62 | Port('caba:bit_in', 'p_resetn', auto = 'resetn'), |
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| 63 | Port('caba:clock_in', 'p_clk', auto = 'clock'), |
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| 64 | Port('caba:dspin_output', 'p_cmd_out', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), |
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| 65 | Port('caba:dspin_input', 'p_cmd_in', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), |
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| 66 | Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), |
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| 67 | Port('caba:dspin_input', 'p_rsp_in', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), |
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| 68 | ], |
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| 69 | ) |
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| 70 | |
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| 71 | |
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