1 | ////////////////////////////////////////////////////////////////////////////// |
---|
2 | // File: tsarv4_cluster_xbar.h |
---|
3 | // Author: Alain Greiner |
---|
4 | // Copyright: UPMC/LIP6 |
---|
5 | // Date : march 2011 |
---|
6 | // This program is released under the GNU public license |
---|
7 | ////////////////////////////////////////////////////////////////////////////// |
---|
8 | // This file define a TSAR cluster architecture without virtual memory, |
---|
9 | // - It uses the virtual_dspin_router as distributed global interconnect |
---|
10 | // - It uses the vci_local_crossbar as local interconnect |
---|
11 | // - It uses the vci_cc_xcache_wrapper_v4 |
---|
12 | // - It uses the vci_mem_cache_v4 |
---|
13 | // - It contains a private RAM a variable latency to emulate the L3 cache |
---|
14 | // - It can contains 1, 2 or 4 processors |
---|
15 | // - Each processor has a private local TTY terminal (vci_multi_tty) |
---|
16 | // - Each processor has a private dma channel (vci_multi_dma) |
---|
17 | // - It uses the vci_xicu interrupt controller |
---|
18 | // - The nprocs tty irq are connected to IRQ_IN[0]...IRQ_IN[3] |
---|
19 | // - The nprocs dma irq are connected to IRQ_IN[4]...IRQ_IN[7] |
---|
20 | // - The peripherals BDEV, FBUF, and the boot BROM are in the cluster |
---|
21 | // containing address 0xBFC00000, and the bdev_irq is connected to IRQ_IN[8] |
---|
22 | ////////////////////////////////////////////////////////////////////////////////// |
---|
23 | |
---|
24 | #ifndef SOCLIB_CABA_TSAR_CLUSTER_V4_XBAR_H |
---|
25 | #define SOCLIB_CABA_TSAR_CLUSTER_V4_XBAR_H |
---|
26 | |
---|
27 | #include <systemc> |
---|
28 | #include <sys/time.h> |
---|
29 | #include <iostream> |
---|
30 | #include <sstream> |
---|
31 | #include <cstdlib> |
---|
32 | #include <cstdarg> |
---|
33 | |
---|
34 | #include "gdbserver.h" |
---|
35 | #include "mapping_table.h" |
---|
36 | #include "mips32.h" |
---|
37 | #include "vci_simple_ram.h" |
---|
38 | #include "vci_xicu.h" |
---|
39 | #include "vci_local_crossbar.h" |
---|
40 | #include "virtual_dspin_router.h" |
---|
41 | #include "vci_vdspin_target_wrapper.h" |
---|
42 | #include "vci_vdspin_initiator_wrapper.h" |
---|
43 | #include "vci_multi_tty.h" |
---|
44 | #include "vci_block_device_tsar_v4.h" |
---|
45 | #include "vci_framebuffer.h" |
---|
46 | #include "vci_multi_dma.h" |
---|
47 | #include "vci_mem_cache_v4.h" |
---|
48 | #include "vci_cc_xcache_wrapper_v4.h" |
---|
49 | |
---|
50 | namespace soclib { |
---|
51 | namespace caba { |
---|
52 | |
---|
53 | /////////////////////////////////////////////////////////////////////////// |
---|
54 | template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> |
---|
55 | class TsarV4ClusterXbar |
---|
56 | /////////////////////////////////////////////////////////////////////////// |
---|
57 | : public soclib::caba::BaseModule |
---|
58 | { |
---|
59 | |
---|
60 | public: |
---|
61 | |
---|
62 | // Ports |
---|
63 | sc_in<bool> p_clk; |
---|
64 | sc_in<bool> p_resetn; |
---|
65 | soclib::caba::DspinOutput<cmd_width> **p_cmd_out; |
---|
66 | soclib::caba::DspinInput<cmd_width> **p_cmd_in; |
---|
67 | soclib::caba::DspinOutput<rsp_width> **p_rsp_out; |
---|
68 | soclib::caba::DspinInput<rsp_width> **p_rsp_in; |
---|
69 | |
---|
70 | // interrupt signals |
---|
71 | sc_signal<bool> signal_false; |
---|
72 | sc_signal<bool> signal_proc_it[4]; |
---|
73 | sc_signal<bool> signal_irq_mdma[4]; |
---|
74 | sc_signal<bool> signal_irq_mtty; |
---|
75 | sc_signal<bool> signal_irq_bdev; |
---|
76 | |
---|
77 | // DSPIN signals between DSPIN routers and VCI/DSPIN wrappers |
---|
78 | DspinSignals<cmd_width> signal_dspin_cmd_l2g_d; |
---|
79 | DspinSignals<cmd_width> signal_dspin_cmd_g2l_d; |
---|
80 | DspinSignals<cmd_width> signal_dspin_cmd_l2g_c; |
---|
81 | DspinSignals<cmd_width> signal_dspin_cmd_g2l_c; |
---|
82 | DspinSignals<rsp_width> signal_dspin_rsp_l2g_d; |
---|
83 | DspinSignals<rsp_width> signal_dspin_rsp_g2l_d; |
---|
84 | DspinSignals<rsp_width> signal_dspin_rsp_l2g_c; |
---|
85 | DspinSignals<rsp_width> signal_dspin_rsp_g2l_c; |
---|
86 | |
---|
87 | // VCI signals between VCI/DSPIN wrappers and local crossbars |
---|
88 | VciSignals<vci_param> signal_vci_l2g_d; |
---|
89 | VciSignals<vci_param> signal_vci_g2l_d; |
---|
90 | VciSignals<vci_param> signal_vci_l2g_c; |
---|
91 | VciSignals<vci_param> signal_vci_g2l_c; |
---|
92 | |
---|
93 | // Direct VCI signals |
---|
94 | VciSignals<vci_param> signal_vci_ini_d_proc[4]; |
---|
95 | VciSignals<vci_param> signal_vci_ini_d_bdev; |
---|
96 | VciSignals<vci_param> signal_vci_ini_d_mdma; |
---|
97 | |
---|
98 | VciSignals<vci_param> signal_vci_tgt_d_memc; |
---|
99 | VciSignals<vci_param> signal_vci_tgt_d_mtty; |
---|
100 | VciSignals<vci_param> signal_vci_tgt_d_xicu; |
---|
101 | VciSignals<vci_param> signal_vci_tgt_d_bdev; |
---|
102 | VciSignals<vci_param> signal_vci_tgt_d_mdma; |
---|
103 | VciSignals<vci_param> signal_vci_tgt_d_brom; |
---|
104 | VciSignals<vci_param> signal_vci_tgt_d_fbuf; |
---|
105 | |
---|
106 | // Coherence VCi signals |
---|
107 | VciSignals<vci_param> signal_vci_ini_c_proc[4]; |
---|
108 | VciSignals<vci_param> signal_vci_tgt_c_proc[4]; |
---|
109 | VciSignals<vci_param> signal_vci_ini_c_memc; |
---|
110 | VciSignals<vci_param> signal_vci_tgt_c_memc; |
---|
111 | |
---|
112 | // external RAM VCI signal |
---|
113 | VciSignals<vci_param> signal_vci_xram; |
---|
114 | |
---|
115 | // Components |
---|
116 | |
---|
117 | VciCcXCacheWrapperV4<vci_param, iss_t>* proc[4]; |
---|
118 | VciMemCacheV4<vci_param>* memc; |
---|
119 | VciXicu<vci_param>* xicu; |
---|
120 | VciLocalCrossbar<vci_param>* xbard; |
---|
121 | VciLocalCrossbar<vci_param>* xbarc; |
---|
122 | VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>* tgtwrapperd; |
---|
123 | VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>* iniwrapperd; |
---|
124 | VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>* tgtwrapperc; |
---|
125 | VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>* iniwrapperc; |
---|
126 | VirtualDspinRouter<cmd_width>* cmdrouter; |
---|
127 | VirtualDspinRouter<rsp_width>* rsprouter; |
---|
128 | VciSimpleRam<vci_param>* brom; |
---|
129 | VciMultiTty<vci_param>* mtty; |
---|
130 | VciFrameBuffer<vci_param>* fbuf; |
---|
131 | VciBlockDeviceTsarV4<vci_param>* bdev; |
---|
132 | VciMultiDma<vci_param>* mdma; |
---|
133 | VciSimpleRam<vci_param>* xram; |
---|
134 | |
---|
135 | TsarV4ClusterXbar( sc_module_name insname, |
---|
136 | size_t nprocs, // number of processors |
---|
137 | size_t n_x, // x coordinate |
---|
138 | size_t n_y, // y coordinate |
---|
139 | size_t n_cluster, // y + ymax*x |
---|
140 | const soclib::common::MappingTable &mtd, // direct mapping table |
---|
141 | const soclib::common::MappingTable &mtc, // coherence mapping table |
---|
142 | const soclib::common::MappingTable &mtx, // xram mapping table |
---|
143 | size_t x_width, // x field number of bits |
---|
144 | size_t y_width, // y field number of bits |
---|
145 | size_t tgtid_memc, |
---|
146 | size_t tgtid_xicu, |
---|
147 | size_t tgtid_fbuf, |
---|
148 | size_t tgtid_mtty, |
---|
149 | size_t tgtid_brom, |
---|
150 | size_t tgtid_bdev, |
---|
151 | size_t tgtid_mdma, |
---|
152 | size_t memc_ways, // number of ways for MEMC |
---|
153 | size_t memc_sets, // number of sets for MEMC |
---|
154 | size_t l1_i_ways, // number of ways for L1 ICACHE |
---|
155 | size_t l1_i_sets, // number of sets for L1 ICACHE |
---|
156 | size_t l1_d_ways, // number of ways for L1 DCACHE |
---|
157 | size_t l1_d_sets, // number of sets for L1 DCACHE |
---|
158 | size_t xram_latency, // external ram latency |
---|
159 | bool io, // I/O cluster if true |
---|
160 | size_t xfb, // frame buffer pixels |
---|
161 | size_t yfb, // frame buffer lines |
---|
162 | char* disk_name, // virtual disk name for BDEV |
---|
163 | size_t block_size, // block size for BDEV |
---|
164 | Loader loader); // loader for BROM |
---|
165 | |
---|
166 | ~TsarV4ClusterXbar(); |
---|
167 | }; |
---|
168 | }} |
---|
169 | |
---|
170 | #endif |
---|