[243] | 1 | ///////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsarv4_vgmn_generic_32_top.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : november 5 2010 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ///////////////////////////////////////////////////////////////////////// |
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| 8 | // This file define a generic TSAR architecture without virtual memory. |
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| 9 | // - It uses the vci_vgmn as global interconnect |
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| 10 | // - It uses the vci_local_crossbar as local interconnect |
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| 11 | // - It uses the vci_cc_xcache (No MMU) |
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| 12 | // The physical address space is 32 bits. |
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| 13 | // The number of clusters cannot be larger than 256. |
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| 14 | // The three parameters are |
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| 15 | // - xmax : number of clusters in a row |
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| 16 | // - ymax : number of clusters in a column |
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| 17 | // - nprocs : number of processor per cluster |
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| 18 | // |
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| 19 | // Each cluster contains nprocs processors, one Memory Cache, |
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| 20 | // and one XICU component. |
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| 21 | // The peripherals BDEV, CDMA, FBUF, MTTY and the boot BROM |
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| 22 | // are in the cluster containing address 0xBFC00000. |
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| 23 | // - The bdev_irq is connected to IRQ_IN[0] |
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| 24 | // - The cdma_irq is connected to IRQ_IN[1] |
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| 25 | // - The tty_irq[i] is connected to IRQ_IN[i+2] |
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| 26 | // For all clusters, the XICU component contains nprocs timers. |
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| 27 | // |
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| 28 | // As we target up to 256 clusters, each cluster can contain |
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| 29 | // at most 16 Mbytes (in a 4Gbytes address space). |
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| 30 | // - Each memory cache contains 9 Mbytes. |
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| 31 | // - The Frame buffer contains 2 Mbytes. |
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| 32 | // - The Boot ROM contains 1 Mbytes. |
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| 33 | // |
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| 34 | // General policy for 32 bits address decoding: |
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| 35 | // To simplifly, all segments base addresses are aligned |
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| 36 | // on 1 Mbyte addresses. Therefore the 12 address MSB bits |
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| 37 | // define the target in the direct address space. |
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| 38 | // In these 12 bits, the (x_width + y_width) MSB bits define |
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| 39 | // the cluster index, and the 4 LSB bits define the local index: |
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| 40 | // |
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| 41 | // | X_ID | Y_ID |---| L_ID | OFFSET | |
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| 42 | // |x_width|y_width|---| 4 | 20 | |
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| 43 | ///////////////////////////////////////////////////////////////////////// |
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| 44 | |
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| 45 | #include <systemc> |
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| 46 | #include <sys/time.h> |
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| 47 | #include <iostream> |
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| 48 | #include <sstream> |
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| 49 | #include <cstdlib> |
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| 50 | #include <cstdarg> |
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| 51 | #include <stdint.h> |
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| 52 | |
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| 53 | #include "mapping_table.h" |
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| 54 | #include "mips32.h" |
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| 55 | #include "vci_simple_ram.h" |
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| 56 | #include "vci_multi_tty.h" |
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| 57 | #include "vci_mem_cache_v4.h" |
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| 58 | #include "vci_cc_vcache_wrapper_v4.h" |
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| 59 | //#include "vci_xicu.h" |
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| 60 | #include "vci_multi_icu.h" |
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| 61 | #include "vci_vgmn.h" |
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| 62 | #include "vci_framebuffer.h" |
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| 63 | #include "vci_dma_tsar_v2.h" |
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| 64 | #include "vci_block_device_tsar_v4.h" |
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| 65 | //#include "vci_block_device.h" |
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| 66 | #include "vci_io_bridge.h" |
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| 67 | #include "gdbserver.h" |
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| 68 | |
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| 69 | //#define SECTOR_SIZE 2048 |
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| 70 | #define SECTOR_SIZE 512 |
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| 71 | |
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| 72 | #define FBUF_XSIZE 128 |
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| 73 | #define FBUF_YSIZE 128 |
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| 74 | |
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| 75 | #define NB_TTYS 9 |
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| 76 | |
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| 77 | ////////////////////////////////////////////// |
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| 78 | // segments definition in direct space. |
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| 79 | // There is 16 Mbytes address space per cluster. |
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| 80 | // The 8 MSB bits define the cluster index (x,y), |
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| 81 | // even if the number of clusters is less than 256. |
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| 82 | // Each memory cache contains up to 9 Mbytes. |
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| 83 | // There is one MEMC segment and one XICU segment per cluster |
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| 84 | // The peripherals BDEV, FBUF, MTTY, CDMA and the boot BROM |
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| 85 | // are mapped in cluster containing address 0xBFC00000 |
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| 86 | |
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| 87 | //#define MEMC_BASE 0x00000000 |
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| 88 | //#define MEMC_SIZE 0x00900000 |
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| 89 | |
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| 90 | #define BROM_BASE 0xBFC00000 |
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| 91 | #define BROM_SIZE 0x00010000 |
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| 92 | |
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| 93 | #define USER_BASE 0x00000000 |
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| 94 | #define USER_SIZE 0x01000000 |
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| 95 | |
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| 96 | #define KERNEL_BASE 0x80000000 |
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| 97 | #define KERNEL_SIZE 0x00100000 |
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| 98 | |
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| 99 | //#define XICU_BASE 0x00900000 |
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| 100 | //#define XICU_SIZE 0x00001000 |
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| 101 | |
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| 102 | #define MTTY_BASE 0x90000000 |
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| 103 | #define MTTY_SIZE 0x00000200 |
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| 104 | |
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| 105 | #define TIM_BASE 0x91000000 |
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| 106 | #define TIM_SIZE 0x00000080 |
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| 107 | |
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| 108 | #define BDEV_BASE 0x92000000 |
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| 109 | #define BDEV_SIZE 0x00000020 |
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| 110 | |
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| 111 | #define CDMA_BASE 0x93000000 |
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| 112 | #define CDMA_SIZE 0x00000100 |
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| 113 | |
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| 114 | #define FBUF_BASE 0x96000000 |
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| 115 | #define FBUF_SIZE 0x00004000 |
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| 116 | |
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| 117 | #define IOB_BASE 0x9E000000 |
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| 118 | #define IOB_SIZE 0x00000100 |
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| 119 | |
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| 120 | #define ICU_BASE 0x9F000000 |
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| 121 | #define ICU_SIZE 0x00000100 |
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| 122 | |
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| 123 | /* Pour ALMOS |
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| 124 | |
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| 125 | #define BOOT_INFO_BLOCK 0xbfc08000 |
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| 126 | #define KERNEL_BIN_IMG 0xbfc10000 |
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| 127 | |
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| 128 | */ |
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| 129 | |
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| 130 | //////////////////////////////////////////////////////////////////// |
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| 131 | // TGTID & SRCID definition in direct space |
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| 132 | // For all components: global TGTID = global SRCID = cluster_index |
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| 133 | // For processors, the local SRCID is between 0 & nprocs-1 |
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| 134 | |
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| 135 | #define PROC_SRCID 0 |
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| 136 | |
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| 137 | #define MEMC_TGTID 4 |
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| 138 | #define BROM_TGTID 1 |
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| 139 | //#define XICU_TGTID 2 |
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| 140 | #define ICU_TGTID 2 |
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| 141 | #define MTTY_TGTID 3 |
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| 142 | #define IOB_TGTID 0 |
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| 143 | //#define BDEV_TGTID 1 |
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| 144 | //#define CDMA_TGTID 2 |
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| 145 | //#define FBUF_TGTID 3 |
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| 146 | |
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| 147 | //////////////////////////////////////////////////////////////////// |
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| 148 | // TGTID & SRCID definition in IO space |
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| 149 | |
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| 150 | #define IOB_TGTID_IO 0 |
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| 151 | #define BDEV_TGTID_IO 1 |
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| 152 | #define CDMA_TGTID_IO 2 |
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| 153 | #define FBUF_TGTID_IO 3 |
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| 154 | |
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| 155 | #define IOB_SRCID_IO 0 |
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| 156 | #define BDEV_SRCID_IO 1 |
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| 157 | #define CDMA_SRCID_IO 2 |
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| 158 | |
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| 159 | //////////////////////////////////////////////////////// |
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| 160 | // TGTID & SRCID definition in coherence space |
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| 161 | // For all components: global TGTID = global SRCID = cluster_index |
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| 162 | // For MEMC : local SRCID = local TGTID = nprocs |
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| 163 | // For processors : local SRCID = local TGTID = PROC_ID |
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| 164 | |
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| 165 | /////////////// |
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| 166 | // VCI format |
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| 167 | #define cell_width 4 |
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| 168 | #define address_width 32 // 40 Ã terme |
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| 169 | #define address_width_io 32 |
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| 170 | #define plen_width 8 |
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| 171 | #define error_width 1 |
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| 172 | #define clen_width 1 |
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| 173 | #define rflag_width 1 |
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| 174 | #define srcid_width 14 |
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| 175 | #define pktid_width 4 |
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| 176 | #define trdid_width 4 |
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| 177 | #define wrplen_width 1 |
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| 178 | |
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| 179 | // cluster index (computed from x,y coordinates) |
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| 180 | #define cluster(x,y) (y + ymax*x) |
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| 181 | |
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| 182 | ///////////////////////////////// |
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| 183 | int _main(int argc, char *argv[]) |
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| 184 | { |
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| 185 | using namespace sc_core; |
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| 186 | using namespace soclib::caba; |
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| 187 | using namespace soclib::common; |
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| 188 | |
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| 189 | char soft_name[128] = "giet_vm171/soft.elf"; // pathname to binary code |
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| 190 | char disk_name[128] = "giet_vm171/apps/display/images.raw"; // pathname to the disk image |
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| 191 | size_t ncycles = 1000000000; // simulated cycles |
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| 192 | size_t nprocs = 1; // number of processors per cluster |
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| 193 | bool debug_ok = false; // debug activated |
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| 194 | size_t from_cycle = 0; // debug start cycle |
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| 195 | size_t to_cycle = 1000000000; // debug end cycle |
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| 196 | |
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| 197 | ////////////// command line arguments ////////////////////// |
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| 198 | if (argc > 1) |
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| 199 | { |
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| 200 | for( int n=1 ; n<argc ; n=n+2 ) |
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| 201 | { |
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| 202 | if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) ) |
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| 203 | { |
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| 204 | ncycles = atoi(argv[n+1]); |
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| 205 | } |
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| 206 | else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) ) |
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| 207 | { |
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| 208 | nprocs = atoi(argv[n+1]); |
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| 209 | assert( (nprocs <= 8) && "The number of processors per cluster cannot be larger than 8"); |
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| 210 | } |
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| 211 | else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ) |
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| 212 | { |
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| 213 | strcpy(soft_name, argv[n+1]); |
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| 214 | } |
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| 215 | else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) |
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| 216 | { |
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| 217 | strcpy(disk_name, argv[n+1]); |
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| 218 | } |
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| 219 | else if( (strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) |
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| 220 | { |
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| 221 | debug_ok = true; |
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| 222 | from_cycle = atoi(argv[n+1]); |
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| 223 | } |
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| 224 | else if( (strcmp(argv[n],"-TOCYCLE") == 0) && (n+1<argc) ) |
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| 225 | { |
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| 226 | to_cycle = atoi(argv[n+1]); |
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| 227 | } |
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| 228 | else |
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| 229 | { |
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| 230 | std::cout << " Arguments on the command line are (key,value) couples." << std::endl; |
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| 231 | std::cout << " The order is not important." << std::endl; |
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| 232 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
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| 233 | std::cout << " -SOFT elf_file_name" << std::endl; |
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| 234 | std::cout << " -DISK disk_image_file_name" << std::endl; |
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| 235 | std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; |
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| 236 | std::cout << " -NPROCS number_of_processors_per_cluster" << std::endl; |
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| 237 | std::cout << " -DEBUG debug_start_cycle" << std::endl; |
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| 238 | std::cout << " -TOCYCLE debug_end_cycle" << std::endl; |
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| 239 | exit(0); |
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| 240 | } |
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| 241 | } |
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| 242 | } |
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| 243 | |
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| 244 | std::cout << std::endl << "*********** TSAR ARCHITECTURE **************" << std::endl |
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| 245 | << " - Interconnect = VGMN & CROSSBAR" << std::endl |
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| 246 | << " - Number of clusters 1" << std::endl |
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| 247 | << " - Number of processors per cluster = " << nprocs << std::endl |
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| 248 | << "**********************************************" << std::endl |
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| 249 | << std::endl; |
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| 250 | |
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| 251 | |
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| 252 | // Define VCI parameters |
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| 253 | typedef soclib::caba::VciParams<cell_width, |
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| 254 | plen_width, |
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| 255 | address_width, |
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| 256 | error_width, |
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| 257 | clen_width, |
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| 258 | rflag_width, |
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| 259 | srcid_width, |
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| 260 | pktid_width, |
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| 261 | trdid_width, |
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| 262 | wrplen_width> vci_param; |
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| 263 | |
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| 264 | typedef soclib::caba::VciParams<cell_width, |
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| 265 | plen_width, |
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| 266 | address_width_io, |
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| 267 | error_width, |
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| 268 | clen_width, |
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| 269 | rflag_width, |
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| 270 | srcid_width, |
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| 271 | pktid_width, |
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| 272 | trdid_width, |
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| 273 | wrplen_width> vci_param_io; |
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| 274 | ///////////////////// |
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| 275 | // Mapping Tables |
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| 276 | ///////////////////// |
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| 277 | |
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| 278 | // direct network |
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| 279 | MappingTable maptabd(address_width, |
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| 280 | IntTab(12), |
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| 281 | IntTab(srcid_width), |
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| 282 | 0xFFF00000); |
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| 283 | |
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| 284 | Segment seg_config_iob("d_seg_iob" , IOB_BASE , IOB_SIZE , IntTab(IOB_TGTID ), false); |
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| 285 | // maptabd.add(Segment("d_seg_memc", MEMC_BASE, MEMC_SIZE, IntTab(MEMC_TGTID), true)); |
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| 286 | maptabd.add(Segment("d_seg_memc_user", USER_BASE, USER_SIZE, IntTab(MEMC_TGTID), true)); |
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| 287 | maptabd.add(Segment("d_seg_memc_kernel", KERNEL_BASE, KERNEL_SIZE, IntTab(MEMC_TGTID), true)); |
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| 288 | maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(BROM_TGTID), true)); |
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| 289 | // maptabd.add(Segment("d_seg_xicu", XICU_BASE, XICU_SIZE, IntTab(XICU_TGTID), false)); |
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| 290 | maptabd.add(Segment("d_seg_icu", ICU_BASE, ICU_SIZE, IntTab(ICU_TGTID), false)); |
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| 291 | maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(MTTY_TGTID), false)); |
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| 292 | |
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| 293 | //maptabd.add(Segment("d_seg_tim" , TIM_BASE , TIM_SIZE , IntTab(MEMC_TGTID ), false)); |
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| 294 | maptabd.add(seg_config_iob); |
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| 295 | maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(IOB_TGTID ), false)); |
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| 296 | maptabd.add(Segment("d_seg_cdma", CDMA_BASE, CDMA_SIZE, IntTab(IOB_TGTID ), false)); |
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| 297 | maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(IOB_TGTID ), false)); |
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| 298 | |
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| 299 | std::cout << maptabd << std::endl; |
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| 300 | |
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| 301 | // coherence network |
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| 302 | MappingTable maptabc(address_width, |
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| 303 | IntTab(12), |
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| 304 | IntTab(srcid_width), |
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| 305 | 0xF0000000); |
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| 306 | |
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| 307 | std::ostringstream sm; |
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| 308 | sm << "c_seg_memc_0"; |
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| 309 | // maptabc.add(Segment(sm.str(), MEMC_BASE, MEMC_SIZE, IntTab(nprocs), false)); |
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| 310 | maptabc.add(Segment(sm.str(), USER_BASE, USER_SIZE, IntTab(nprocs), false)); |
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| 311 | maptabc.add(Segment("c_seb_memc_kernel", KERNEL_BASE, KERNEL_SIZE, IntTab(nprocs), false)); |
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| 312 | // the segment base and size will be modified |
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| 313 | // when the segmentation of the coherence space will be simplified |
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| 314 | |
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| 315 | std::ostringstream sr; |
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| 316 | sr << "c_seg_brom_0"; |
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| 317 | maptabc.add(Segment(sr.str(), BROM_BASE, BROM_SIZE, IntTab(nprocs), false)); |
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| 318 | |
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| 319 | sc_uint<address_width> avoid_collision = 0; |
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| 320 | for ( size_t p = 0 ; p < nprocs ; p++) |
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| 321 | { |
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| 322 | sc_uint<address_width> base = USER_SIZE + KERNEL_SIZE + (p*0x100000); |
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| 323 | // the following test is to avoid a collision between the c_seg_brom segment |
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| 324 | // and a c_seg_proc segment (all segments base addresses being multiple of 1Mbytes) |
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| 325 | if ( base == BROM_BASE ) avoid_collision = 0x100000; |
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| 326 | std::ostringstream sp; |
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| 327 | sp << "c_seg_proc_" << p; |
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| 328 | maptabc.add(Segment(sp.str(), base + avoid_collision, 0x20, IntTab(p), false, true, IntTab(p))); |
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| 329 | // the two last arguments will be removed |
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| 330 | // when the segmentation of the coherence space will be simplified |
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| 331 | } |
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| 332 | |
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| 333 | std::cout << maptabc << std::endl; |
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| 334 | |
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| 335 | // external network |
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| 336 | MappingTable maptabx(address_width, IntTab(1), IntTab(srcid_width), 0xF0000000); |
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| 337 | |
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| 338 | // maptabx.add(Segment("seg_memc_x", MEMC_BASE, MEMC_SIZE, IntTab(0), false)); |
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| 339 | maptabx.add(Segment("seg_memc_x_user", USER_BASE, USER_SIZE, IntTab(0), false)); |
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| 340 | maptabx.add(Segment("seg_memc_x_kernel", KERNEL_BASE, KERNEL_SIZE, IntTab(0), false)); |
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| 341 | |
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| 342 | std::cout << maptabx << std::endl; |
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| 343 | |
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| 344 | // io network |
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| 345 | MappingTable maptabio(address_width, |
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| 346 | IntTab(12), |
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| 347 | IntTab(srcid_width), |
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| 348 | 0x00F00000); |
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| 349 | |
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| 350 | maptabio.add(Segment("io_seg_iob" , IOB_BASE , IOB_SIZE , IntTab(IOB_TGTID_IO) , false)); |
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| 351 | maptabio.add(Segment("io_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(BDEV_TGTID_IO), false)); |
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| 352 | maptabio.add(Segment("io_seg_cdma", CDMA_BASE, CDMA_SIZE, IntTab(CDMA_TGTID_IO), false)); |
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| 353 | maptabio.add(Segment("io_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(FBUF_TGTID_IO), false)); |
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| 354 | |
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| 355 | std::cout << maptabio << std::endl; |
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| 356 | //////////////////// |
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| 357 | // Signals |
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| 358 | /////////////////// |
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| 359 | |
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| 360 | sc_clock signal_clk("clk"); |
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| 361 | sc_signal<bool> signal_resetn("resetn"); |
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| 362 | sc_signal<bool> signal_false; |
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| 363 | |
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| 364 | // IRQ signals (one signal per proc) |
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| 365 | sc_signal<bool>* signal_proc_it = |
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| 366 | alloc_elems<sc_signal<bool> >("signal_proc_it", nprocs); |
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| 367 | |
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| 368 | sc_signal<bool>* signal_irq_mtty = |
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| 369 | alloc_elems<sc_signal<bool> >("signal_irq_mtty", NB_TTYS); |
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| 370 | |
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| 371 | sc_signal<bool> signal_irq_bdev; |
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| 372 | sc_signal<bool> signal_irq_cdma; |
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| 373 | |
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| 374 | sc_signal<bool> empty; |
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| 375 | |
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| 376 | // Direct VCI signals |
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| 377 | VciSignals<vci_param>* signal_vci_ini_d_proc = |
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| 378 | alloc_elems<VciSignals<vci_param> >("signal_vci_ini_d_proc", nprocs); |
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| 379 | VciSignals<vci_param> signal_vci_ini_d_iob("signal_vci_ini_d_iob"); |
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| 380 | |
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| 381 | VciSignals<vci_param> signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"); |
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| 382 | VciSignals<vci_param> signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"); |
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| 383 | // VciSignals<vci_param> signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"); |
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| 384 | VciSignals<vci_param> signal_vci_tgt_d_icu("signal_vci_tgt_d_icu"); |
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| 385 | VciSignals<vci_param> signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"); |
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| 386 | VciSignals<vci_param> signal_vci_tgt_d_iob("signal_vci_tgt_d_iob"); |
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| 387 | |
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| 388 | // IO network VCI signals |
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| 389 | VciSignals<vci_param_io> signal_vci_tgt_io_iob ("signal_vci_tgt_io_iob"); |
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| 390 | VciSignals<vci_param_io> signal_vci_tgt_io_bdev("signal_vci_tgt_io_bdev"); |
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| 391 | VciSignals<vci_param_io> signal_vci_tgt_io_cdma("signal_vci_tgt_io_cdma"); |
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| 392 | VciSignals<vci_param_io> signal_vci_tgt_io_fbuf("signal_vci_tgt_io_fbuf"); |
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| 393 | |
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| 394 | VciSignals<vci_param_io> signal_vci_ini_io_bdev("signal_vci_ini_io_bdev"); |
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| 395 | VciSignals<vci_param_io> signal_vci_ini_io_cdma("signal_vci_ini_io_cdma"); |
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| 396 | VciSignals<vci_param_io> signal_vci_ini_io_iob ("signal_vci_ini_io_iob"); |
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| 397 | |
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| 398 | // Coherence VCI signals |
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| 399 | |
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| 400 | VciSignals<vci_param>* signal_vci_ini_c_proc = |
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| 401 | alloc_elems<VciSignals<vci_param> >("signal_vci_ini_c_proc", nprocs); |
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| 402 | |
---|
| 403 | VciSignals<vci_param>* signal_vci_tgt_c_proc = |
---|
| 404 | alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_c_proc", nprocs); |
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| 405 | |
---|
| 406 | VciSignals<vci_param> signal_vci_ini_c_memc("signal_vci_ini_c_memc"); |
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| 407 | VciSignals<vci_param> signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"); |
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| 408 | |
---|
| 409 | // Xternal network VCI signals |
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| 410 | |
---|
| 411 | VciSignals<vci_param> signal_vci_tgt_x_xram("signal_vci_tgt_x_xram"); |
---|
| 412 | VciSignals<vci_param> signal_vci_ini_x_memc("signal_vci_ini_x_memc"); |
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| 413 | VciSignals<vci_param> signal_vci_ini_x_iob("signal_vci_ini_x_iob"); |
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| 414 | |
---|
| 415 | //////////////////////////// |
---|
| 416 | // Components |
---|
| 417 | //////////////////////////// |
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| 418 | |
---|
| 419 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
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| 420 | |
---|
| 421 | |
---|
| 422 | soclib::common::Loader loader(soft_name); |
---|
| 423 | proc_iss::set_loader(loader); |
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| 424 | |
---|
| 425 | |
---|
| 426 | // External RAM |
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| 427 | VciSimpleRam<vci_param> xram( |
---|
| 428 | "xram", |
---|
| 429 | IntTab(0), |
---|
| 430 | maptabx, |
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| 431 | loader); |
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| 432 | |
---|
| 433 | // External network |
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| 434 | VciVgmn<vci_param> xnoc( |
---|
| 435 | "xnoc", |
---|
| 436 | maptabx, |
---|
| 437 | 2, |
---|
| 438 | 1, |
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| 439 | 2, |
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| 440 | 2); |
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| 441 | |
---|
| 442 | // Direct network |
---|
| 443 | VciVgmn<vci_param> dnoc( |
---|
| 444 | "dnoc", |
---|
| 445 | maptabd, |
---|
| 446 | nprocs+1, |
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| 447 | 5, |
---|
| 448 | 2, 2); |
---|
| 449 | |
---|
| 450 | // Coherence network |
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| 451 | VciVgmn<vci_param> cnoc( |
---|
| 452 | "cnoc", |
---|
| 453 | maptabc, |
---|
| 454 | nprocs+1, |
---|
| 455 | nprocs+1, |
---|
| 456 | 2, 2); |
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| 457 | |
---|
| 458 | // IO network |
---|
| 459 | VciVgmn<vci_param_io> ionoc( |
---|
| 460 | "ionoc", |
---|
| 461 | maptabio, |
---|
| 462 | 3, |
---|
| 463 | 4, |
---|
| 464 | 2, 2); |
---|
| 465 | |
---|
| 466 | |
---|
| 467 | // Peripherals : TTY, Frame Buffer, Block Device, Boot ROM, & DMA |
---|
| 468 | VciSimpleRam<vci_param> brom( |
---|
| 469 | "brom", |
---|
| 470 | IntTab(BROM_TGTID), |
---|
| 471 | maptabd, |
---|
| 472 | loader); |
---|
| 473 | |
---|
| 474 | |
---|
| 475 | VciIoBridge<vci_param, vci_param, vci_param_io> iob( |
---|
| 476 | "vci_iob", |
---|
| 477 | 3, // number of peripherals |
---|
| 478 | maptabx, |
---|
| 479 | maptabd, |
---|
| 480 | maptabio, |
---|
| 481 | /**/ seg_config_iob, |
---|
| 482 | IntTab(), |
---|
| 483 | // IntTab(IOB_TGTID), |
---|
| 484 | IntTab(nprocs), |
---|
| 485 | IntTab(IOB_TGTID_IO), |
---|
| 486 | IntTab(IOB_SRCID_IO), |
---|
| 487 | IntTab(1), |
---|
| 488 | 16, |
---|
| 489 | 4, |
---|
| 490 | 4, |
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| 491 | from_cycle, |
---|
| 492 | debug_ok |
---|
| 493 | ); |
---|
| 494 | |
---|
| 495 | |
---|
| 496 | VciMultiTty<vci_param> mtty( |
---|
| 497 | "mtty", |
---|
| 498 | IntTab(MTTY_TGTID), |
---|
| 499 | maptabd, |
---|
| 500 | "tty0","tty1","tty2","tty3", |
---|
| 501 | "tty4","tty5","tty6","tty7", |
---|
| 502 | "tty8", NULL); |
---|
| 503 | |
---|
| 504 | VciFrameBuffer<vci_param_io> fbuf( |
---|
| 505 | "fbuf", |
---|
| 506 | IntTab(FBUF_TGTID_IO), |
---|
| 507 | maptabio, |
---|
| 508 | FBUF_XSIZE, |
---|
| 509 | FBUF_YSIZE); |
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| 510 | |
---|
| 511 | VciBlockDeviceTsarV4<vci_param_io> bdev( |
---|
| 512 | // VciBlockDevice<vci_param_io> bdev( |
---|
| 513 | "bdev", |
---|
| 514 | maptabio, |
---|
| 515 | IntTab(BDEV_SRCID_IO), // SRCID_D |
---|
| 516 | IntTab(BDEV_TGTID_IO), // TGTID_D |
---|
| 517 | disk_name, |
---|
| 518 | SECTOR_SIZE); |
---|
| 519 | |
---|
| 520 | VciDmaTsarV2<vci_param_io> cdma( |
---|
| 521 | "cdma", |
---|
| 522 | maptabio, |
---|
| 523 | IntTab(CDMA_SRCID_IO), // SRCID_D |
---|
| 524 | IntTab(CDMA_TGTID_IO), // TGTID_D |
---|
| 525 | 64); |
---|
| 526 | |
---|
| 527 | // processors (nprocs per cluster) |
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| 528 | |
---|
| 529 | VciCcVCacheWrapperV4<vci_param, proc_iss> *proc[nprocs]; |
---|
| 530 | |
---|
| 531 | for ( size_t p = 0 ; p < nprocs ; p++ ) |
---|
| 532 | { |
---|
| 533 | |
---|
| 534 | std::ostringstream sp; |
---|
| 535 | sp << "proc_" << "_" << p; |
---|
| 536 | |
---|
| 537 | proc[p] = new VciCcVCacheWrapperV4<vci_param, proc_iss>( |
---|
| 538 | sp.str().c_str(), |
---|
| 539 | p, |
---|
| 540 | maptabd, maptabc, |
---|
| 541 | IntTab(PROC_SRCID+p), // SRCID_D |
---|
| 542 | IntTab(PROC_SRCID+p), // SRCID_C |
---|
| 543 | IntTab(PROC_SRCID+p), // TGTID_C |
---|
| 544 | 4,4, // itlb ways, sets |
---|
| 545 | 4,4, // dtlb ways, sets |
---|
| 546 | 4,64,16,4,64,16, // Icache and Dcache sizes (way, set, words) |
---|
| 547 | 4,8, |
---|
| 548 | 20000000, |
---|
| 549 | from_cycle, |
---|
| 550 | debug_ok |
---|
| 551 | ); |
---|
| 552 | } |
---|
| 553 | |
---|
| 554 | // memory caches (one per cluster) |
---|
| 555 | VciMemCacheV4<vci_param> memc( |
---|
| 556 | sm.str().c_str(), |
---|
| 557 | maptabd, maptabc, maptabx, |
---|
| 558 | IntTab(0), // SRCID_X |
---|
| 559 | IntTab(nprocs), // SRCID_C |
---|
| 560 | IntTab(MEMC_TGTID), // TGTID_D |
---|
| 561 | IntTab(nprocs), // TGTID_C |
---|
| 562 | 16,256,16, // CACHE SIZE |
---|
| 563 | 4096, // HEAP SIZE |
---|
| 564 | 4,4, // TRANSACTION and UPDATE TAB lines |
---|
| 565 | from_cycle, |
---|
| 566 | debug_ok |
---|
| 567 | ); |
---|
| 568 | /* |
---|
| 569 | // XICU (one per cluster) |
---|
| 570 | VciXicu<vci_param> xicu( |
---|
| 571 | "vci_xicu", |
---|
| 572 | maptabd, |
---|
| 573 | IntTab(XICU_TGTID), // TGTID_D |
---|
| 574 | nprocs, // number of TIMERS |
---|
| 575 | NB_TTYS, // number of hard IRQs |
---|
| 576 | nprocs+1, // number of soft IRQs |
---|
| 577 | nprocs); // number of output IRQ lines |
---|
| 578 | */ |
---|
| 579 | // ICU |
---|
| 580 | /* |
---|
| 581 | VciIcu<vci_param> icu( |
---|
| 582 | "vci_icu", |
---|
| 583 | IntTab(ICU_TGTID), // TGTID_D |
---|
| 584 | maptabd, |
---|
| 585 | NB_TTYS + 2 // number of hard IRQs |
---|
| 586 | ); |
---|
| 587 | */ |
---|
| 588 | VciMultiIcu<vci_param> *icu; |
---|
| 589 | icu = new VciMultiIcu<vci_param>("icu", |
---|
| 590 | IntTab(ICU_TGTID), |
---|
| 591 | maptabd, |
---|
| 592 | 32, // number of irq in |
---|
| 593 | 1); //NB_PROCS number of irq out |
---|
| 594 | |
---|
| 595 | |
---|
| 596 | std::cout << "all components created" << std::endl; |
---|
| 597 | |
---|
| 598 | /////////////////////////////////////////////////////////////// |
---|
| 599 | // Net-list |
---|
| 600 | /////////////////////////////////////////////////////////////// |
---|
| 601 | |
---|
| 602 | // External Ram (one instance) |
---|
| 603 | xram.p_clk (signal_clk); |
---|
| 604 | xram.p_resetn (signal_resetn); |
---|
| 605 | xram.p_vci (signal_vci_tgt_x_xram); |
---|
| 606 | |
---|
| 607 | // External Network (one instance) |
---|
| 608 | xnoc.p_clk (signal_clk); |
---|
| 609 | xnoc.p_resetn (signal_resetn); |
---|
| 610 | xnoc.p_to_target[0] (signal_vci_tgt_x_xram); |
---|
| 611 | xnoc.p_to_initiator[0] (signal_vci_ini_x_memc); |
---|
| 612 | xnoc.p_to_initiator[1] (signal_vci_ini_x_iob); |
---|
| 613 | |
---|
| 614 | // Direct Network (one instance) |
---|
| 615 | dnoc.p_clk (signal_clk); |
---|
| 616 | dnoc.p_resetn (signal_resetn); |
---|
| 617 | dnoc.p_to_target[MEMC_TGTID] (signal_vci_tgt_d_memc); |
---|
| 618 | dnoc.p_to_target[BROM_TGTID] (signal_vci_tgt_d_brom); |
---|
| 619 | // dnoc.p_to_target[XICU_TGTID] (signal_vci_tgt_d_xicu); |
---|
| 620 | dnoc.p_to_target[ICU_TGTID] (signal_vci_tgt_d_icu); |
---|
| 621 | dnoc.p_to_target[MTTY_TGTID] (signal_vci_tgt_d_mtty); |
---|
| 622 | dnoc.p_to_target[IOB_TGTID] (signal_vci_tgt_d_iob); |
---|
| 623 | // dnoc.p_to_target[BDEV_TGTID] (signal_vci_tgt_d_iob); |
---|
| 624 | // dnoc.p_to_target[CDMA_TGTID] (signal_vci_tgt_d_iob); |
---|
| 625 | // dnoc.p_to_target[FBUF_TGTID] (signal_vci_tgt_d_iob); |
---|
| 626 | |
---|
| 627 | dnoc.p_to_initiator[nprocs] (signal_vci_ini_d_iob); |
---|
| 628 | |
---|
| 629 | |
---|
| 630 | // Coherence Network (one instance) |
---|
| 631 | cnoc.p_clk (signal_clk); |
---|
| 632 | cnoc.p_resetn (signal_resetn); |
---|
| 633 | cnoc.p_to_initiator[nprocs] (signal_vci_ini_c_memc); |
---|
| 634 | cnoc.p_to_target[nprocs] (signal_vci_tgt_c_memc); |
---|
| 635 | |
---|
| 636 | // Processors |
---|
| 637 | for ( size_t p = 0 ; p < nprocs ; p++ ) |
---|
| 638 | { |
---|
| 639 | dnoc.p_to_initiator[p] (signal_vci_ini_d_proc[p]); |
---|
| 640 | cnoc.p_to_initiator[p] (signal_vci_ini_c_proc[p]); |
---|
| 641 | cnoc.p_to_target[p] (signal_vci_tgt_c_proc[p]); |
---|
| 642 | |
---|
| 643 | proc[p]->p_clk (signal_clk); |
---|
| 644 | proc[p]->p_resetn (signal_resetn); |
---|
| 645 | proc[p]->p_vci_ini_d (signal_vci_ini_d_proc[p]); |
---|
| 646 | proc[p]->p_vci_ini_c (signal_vci_ini_c_proc[p]); |
---|
| 647 | proc[p]->p_vci_tgt_c (signal_vci_tgt_c_proc[p]); |
---|
| 648 | proc[p]->p_irq[0] (signal_proc_it[p]); |
---|
| 649 | for ( size_t j = 1 ; j < 6 ; j++ ) |
---|
| 650 | { |
---|
| 651 | proc[p]->p_irq[j] (signal_false); |
---|
| 652 | } |
---|
| 653 | } |
---|
| 654 | |
---|
| 655 | std::cout << "ionoc: begin" << std::endl; |
---|
| 656 | |
---|
| 657 | ionoc.p_clk (signal_clk); |
---|
| 658 | ionoc.p_resetn (signal_resetn); |
---|
| 659 | ionoc.p_to_initiator[IOB_SRCID_IO] (signal_vci_ini_io_iob); |
---|
| 660 | ionoc.p_to_initiator[BDEV_SRCID_IO] (signal_vci_ini_io_bdev); |
---|
| 661 | ionoc.p_to_initiator[CDMA_SRCID_IO] (signal_vci_ini_io_cdma); |
---|
| 662 | ionoc.p_to_target[IOB_TGTID_IO] (signal_vci_tgt_io_iob); |
---|
| 663 | ionoc.p_to_target[BDEV_TGTID_IO] (signal_vci_tgt_io_bdev); |
---|
| 664 | ionoc.p_to_target[CDMA_TGTID_IO] (signal_vci_tgt_io_cdma); |
---|
| 665 | ionoc.p_to_target[FBUF_TGTID_IO] (signal_vci_tgt_io_fbuf); |
---|
| 666 | |
---|
| 667 | std::cout << "ionoc: end" << std::endl; |
---|
| 668 | /* |
---|
| 669 | // XICU |
---|
| 670 | xicu.p_clk (signal_clk); |
---|
| 671 | xicu.p_resetn (signal_resetn); |
---|
| 672 | xicu.p_vci (signal_vci_tgt_d_xicu); |
---|
| 673 | for ( size_t p = 0 ; p < nprocs ; p++ ) |
---|
| 674 | { |
---|
| 675 | xicu.p_irq[p] (signal_proc_it[p]); |
---|
| 676 | } |
---|
| 677 | |
---|
| 678 | for(size_t i=0 ; i<NB_TTYS ; i++) |
---|
| 679 | { |
---|
| 680 | xicu.p_hwi[i] (signal_irq_mtty[i]); |
---|
| 681 | } |
---|
| 682 | */ |
---|
| 683 | // ICU |
---|
| 684 | icu->p_clk (signal_clk); |
---|
| 685 | icu->p_resetn (signal_resetn); |
---|
| 686 | icu->p_vci (signal_vci_tgt_d_icu); |
---|
| 687 | icu->p_irq_out[0] (signal_proc_it[0]); |
---|
| 688 | |
---|
| 689 | for (size_t i = 0 ; i < 32 ; i++ ) |
---|
| 690 | { |
---|
| 691 | // if ( i < NB_TIMERS ) icu->p_irq_in[i] (signal_irq_tim[i]); |
---|
| 692 | if ( i < 8 ) icu->p_irq_in[i] (signal_false); |
---|
| 693 | else if ( i == 8) icu->p_irq_in[i] (signal_irq_cdma); |
---|
| 694 | else if ( i < 16 ) icu->p_irq_in[i] (signal_false); |
---|
| 695 | else if ( i < (16 + NB_TTYS) ) icu->p_irq_in[i] (signal_irq_mtty[i-16]); |
---|
| 696 | else if ( i < 31 ) icu->p_irq_in[i] (signal_false); |
---|
| 697 | else icu->p_irq_in[i] (signal_irq_bdev); |
---|
| 698 | } |
---|
| 699 | |
---|
| 700 | // MEMC |
---|
| 701 | memc.p_clk (signal_clk); |
---|
| 702 | memc.p_resetn (signal_resetn); |
---|
| 703 | memc.p_vci_tgt (signal_vci_tgt_d_memc); |
---|
| 704 | memc.p_vci_ini (signal_vci_ini_c_memc); |
---|
| 705 | memc.p_vci_tgt_cleanup (signal_vci_tgt_c_memc); |
---|
| 706 | memc.p_vci_ixr (signal_vci_ini_x_memc); |
---|
| 707 | |
---|
| 708 | brom.p_clk (signal_clk); |
---|
| 709 | brom.p_resetn (signal_resetn); |
---|
| 710 | brom.p_vci (signal_vci_tgt_d_brom); |
---|
| 711 | |
---|
| 712 | mtty.p_clk (signal_clk); |
---|
| 713 | mtty.p_resetn (signal_resetn); |
---|
| 714 | mtty.p_vci (signal_vci_tgt_d_mtty); |
---|
| 715 | |
---|
| 716 | for(size_t i=0 ; i<NB_TTYS ; i++) |
---|
| 717 | { |
---|
| 718 | mtty.p_irq[i] (signal_irq_mtty[i]); |
---|
| 719 | } |
---|
| 720 | |
---|
| 721 | std::cout << "iob: begin" << std::endl; |
---|
| 722 | |
---|
| 723 | iob.p_clk (signal_clk); |
---|
| 724 | iob.p_resetn (signal_resetn); |
---|
| 725 | // iob.p_irq_in[0] (signal_irq_cdma); |
---|
| 726 | // iob.p_irq_in[1] (signal_irq_bdev); |
---|
| 727 | iob.p_irq_in[0] (empty); |
---|
| 728 | iob.p_irq_in[1] (empty); |
---|
| 729 | iob.p_irq_in[2] (empty); |
---|
| 730 | iob.p_vci_ini_dma (signal_vci_ini_x_iob); |
---|
| 731 | iob.p_vci_tgt_dma (signal_vci_tgt_io_iob); |
---|
| 732 | iob.p_vci_ini_config (signal_vci_ini_io_iob); |
---|
| 733 | iob.p_vci_ini_miss (signal_vci_ini_d_iob); |
---|
| 734 | iob.p_vci_tgt_config (signal_vci_tgt_d_iob); |
---|
| 735 | |
---|
| 736 | std::cout << "iob: end" << std::endl; |
---|
| 737 | |
---|
| 738 | bdev.p_clk (signal_clk); |
---|
| 739 | bdev.p_resetn (signal_resetn); |
---|
| 740 | bdev.p_irq (signal_irq_bdev); |
---|
| 741 | bdev.p_vci_target (signal_vci_tgt_io_bdev); |
---|
| 742 | bdev.p_vci_initiator (signal_vci_ini_io_bdev); |
---|
| 743 | |
---|
| 744 | cdma.p_clk (signal_clk); |
---|
| 745 | cdma.p_resetn (signal_resetn); |
---|
| 746 | cdma.p_irq (signal_irq_cdma); |
---|
| 747 | cdma.p_vci_target (signal_vci_tgt_io_cdma); |
---|
| 748 | cdma.p_vci_initiator (signal_vci_ini_io_cdma); |
---|
| 749 | |
---|
| 750 | fbuf.p_clk (signal_clk); |
---|
| 751 | fbuf.p_resetn (signal_resetn); |
---|
| 752 | fbuf.p_vci (signal_vci_tgt_io_fbuf); |
---|
| 753 | |
---|
| 754 | |
---|
| 755 | std::cout << "all components connected" << std::endl; |
---|
| 756 | |
---|
| 757 | //////////////////////////////////////////////////////// |
---|
| 758 | // Simulation |
---|
| 759 | /////////////////////////////////////////////////////// |
---|
| 760 | |
---|
| 761 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
| 762 | signal_resetn = false; |
---|
| 763 | |
---|
| 764 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 765 | signal_resetn = true; |
---|
| 766 | char buf[1]; |
---|
| 767 | |
---|
| 768 | for(size_t i=1 ; i<ncycles ; i++) |
---|
| 769 | { |
---|
| 770 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 771 | |
---|
| 772 | if( debug_ok && (i > from_cycle) && (i < to_cycle) ) |
---|
| 773 | { |
---|
| 774 | std::cout << std::dec << "*************** cycle " << i << " ***********************" << std::endl; |
---|
| 775 | proc[0]->print_trace(); |
---|
| 776 | std::cout << std::endl; |
---|
| 777 | |
---|
| 778 | memc.print_trace(); |
---|
| 779 | std::cout << std::endl; |
---|
| 780 | |
---|
| 781 | iob.print_trace(); |
---|
| 782 | std::cout << std::endl; |
---|
| 783 | |
---|
| 784 | icu->print_trace(); |
---|
| 785 | std::cout << std::endl; |
---|
| 786 | |
---|
| 787 | bdev.print_trace(); |
---|
| 788 | std::cout << std::endl; |
---|
| 789 | |
---|
| 790 | xram.print_trace(); |
---|
| 791 | std::cout << std::endl; |
---|
| 792 | } |
---|
| 793 | } |
---|
| 794 | |
---|
| 795 | std::cout << "Hit ENTER to end simulation" << std::endl; |
---|
| 796 | std::cin.getline(buf,1); |
---|
| 797 | |
---|
| 798 | // for ( size_t p = 0 ; p < nprocs ; p++ ) |
---|
| 799 | // proc[p]->print_stats(); |
---|
| 800 | |
---|
| 801 | return EXIT_SUCCESS; |
---|
| 802 | } |
---|
| 803 | |
---|
| 804 | int sc_main (int argc, char *argv[]) |
---|
| 805 | { |
---|
| 806 | try { |
---|
| 807 | return _main(argc, argv); |
---|
| 808 | } catch (std::exception &e) { |
---|
| 809 | std::cout << e.what() << std::endl; |
---|
| 810 | } catch (...) { |
---|
| 811 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 812 | throw; |
---|
| 813 | } |
---|
| 814 | return 1; |
---|
| 815 | } |
---|