[243] | 1 | ///////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsarv4_vgmn_generic_32_top.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : november 5 2010 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ///////////////////////////////////////////////////////////////////////// |
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| 8 | // This file define a generic TSAR architecture without virtual memory. |
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| 9 | // - It uses the vci_vgmn as global interconnect |
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| 10 | // - It uses the vci_local_crossbar as local interconnect |
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| 11 | // - It uses the vci_cc_xcache (No MMU) |
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| 12 | // The physical address space is 32 bits. |
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| 13 | // The number of clusters cannot be larger than 256. |
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| 14 | // The three parameters are |
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| 15 | // - xmax : number of clusters in a row |
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| 16 | // - ymax : number of clusters in a column |
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| 17 | // - nprocs : number of processor per cluster |
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| 18 | // |
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| 19 | // Each cluster contains nprocs processors, one Memory Cache, |
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| 20 | // and one XICU component. |
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| 21 | // The peripherals BDEV, CDMA, FBUF, MTTY and the boot BROM |
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| 22 | // are in the cluster containing address 0xBFC00000. |
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| 23 | // - The bdev_irq is connected to IRQ_IN[0] |
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| 24 | // - The cdma_irq is connected to IRQ_IN[1] |
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| 25 | // - The tty_irq[i] is connected to IRQ_IN[i+2] |
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| 26 | // For all clusters, the XICU component contains nprocs timers. |
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| 27 | // |
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| 28 | // As we target up to 256 clusters, each cluster can contain |
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| 29 | // at most 16 Mbytes (in a 4Gbytes address space). |
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| 30 | // - Each memory cache contains 9 Mbytes. |
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| 31 | // - The Frame buffer contains 2 Mbytes. |
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| 32 | // - The Boot ROM contains 1 Mbytes. |
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| 33 | // |
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| 34 | // General policy for 32 bits address decoding: |
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| 35 | // To simplifly, all segments base addresses are aligned |
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| 36 | // on 1 Mbyte addresses. Therefore the 12 address MSB bits |
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| 37 | // define the target in the direct address space. |
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| 38 | // In these 12 bits, the (x_width + y_width) MSB bits define |
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| 39 | // the cluster index, and the 4 LSB bits define the local index: |
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| 40 | // |
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| 41 | // | X_ID | Y_ID |---| L_ID | OFFSET | |
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| 42 | // |x_width|y_width|---| 4 | 20 | |
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| 43 | ///////////////////////////////////////////////////////////////////////// |
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| 44 | |
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| 45 | #include <systemc> |
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| 46 | #include <sys/time.h> |
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| 47 | #include <iostream> |
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| 48 | #include <sstream> |
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| 49 | #include <cstdlib> |
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| 50 | #include <cstdarg> |
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| 51 | #include <stdint.h> |
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| 52 | |
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| 53 | #include "mapping_table.h" |
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| 54 | #include "mips32.h" |
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| 55 | #include "vci_simple_ram.h" |
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| 56 | #include "vci_multi_tty.h" |
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| 57 | #include "vci_mem_cache_v4.h" |
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| 58 | #include "vci_cc_vcache_wrapper_v4.h" |
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| 59 | //#include "vci_xicu.h" |
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| 60 | #include "vci_multi_icu.h" |
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| 61 | #include "vci_vgmn.h" |
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| 62 | #include "vci_framebuffer.h" |
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| 63 | #include "vci_dma_tsar_v2.h" |
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| 64 | #include "vci_block_device_tsar_v4.h" |
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| 65 | //#include "vci_block_device.h" |
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| 66 | //#include "vci_io_bridge.h" |
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| 67 | #include "gdbserver.h" |
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| 68 | |
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| 69 | //#define SECTOR_SIZE 2048 |
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| 70 | #define SECTOR_SIZE 512 |
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| 71 | |
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| 72 | #define FBUF_XSIZE 128 |
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| 73 | #define FBUF_YSIZE 128 |
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| 74 | |
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| 75 | #define NB_TTYS 9 |
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| 76 | |
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| 77 | ////////////////////////////////////////////// |
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| 78 | // segments definition in direct space. |
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| 79 | // There is 16 Mbytes address space per cluster. |
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| 80 | // The 8 MSB bits define the cluster index (x,y), |
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| 81 | // even if the number of clusters is less than 256. |
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| 82 | // Each memory cache contains up to 9 Mbytes. |
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| 83 | // There is one MEMC segment and one XICU segment per cluster |
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| 84 | // The peripherals BDEV, FBUF, MTTY, CDMA and the boot BROM |
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| 85 | // are mapped in cluster containing address 0xBFC00000 |
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| 86 | |
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| 87 | //#define MEMC_BASE 0x00000000 |
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| 88 | //#define MEMC_SIZE 0x00900000 |
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| 89 | |
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| 90 | #define BROM_BASE 0xBFC00000 |
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| 91 | #define BROM_SIZE 0x00010000 |
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| 92 | |
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| 93 | #define USER_BASE 0x00000000 |
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| 94 | #define USER_SIZE 0x01000000 |
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| 95 | |
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| 96 | #define KERNEL_BASE 0x80000000 |
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| 97 | #define KERNEL_SIZE 0x00100000 |
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| 98 | |
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| 99 | //#define XICU_BASE 0x00900000 |
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| 100 | //#define XICU_SIZE 0x00001000 |
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| 101 | |
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| 102 | #define MTTY_BASE 0x90000000 |
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| 103 | #define MTTY_SIZE 0x00000200 |
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| 104 | |
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| 105 | #define TIM_BASE 0x91000000 |
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| 106 | #define TIM_SIZE 0x00000080 |
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| 107 | |
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| 108 | #define BDEV_BASE 0x92000000 |
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| 109 | #define BDEV_SIZE 0x00000020 |
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| 110 | |
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| 111 | #define CDMA_BASE 0x93000000 |
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| 112 | #define CDMA_SIZE 0x00000100 |
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| 113 | |
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| 114 | #define FBUF_BASE 0x96000000 |
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| 115 | #define FBUF_SIZE 0x00004000 |
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| 116 | |
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| 117 | //#define IOB_BASE 0x9E000000 |
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| 118 | //#define IOB_SIZE 0x00000100 |
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| 119 | |
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| 120 | #define ICU_BASE 0x9F000000 |
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| 121 | #define ICU_SIZE 0x00000100 |
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| 122 | |
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| 123 | /* Pour ALMOS |
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| 124 | |
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| 125 | #define BOOT_INFO_BLOCK 0xbfc08000 |
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| 126 | #define KERNEL_BIN_IMG 0xbfc10000 |
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| 127 | |
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| 128 | */ |
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| 129 | |
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| 130 | //////////////////////////////////////////////////////////////////// |
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| 131 | // TGTID & SRCID definition in direct space |
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| 132 | // For all components: global TGTID = global SRCID = cluster_index |
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| 133 | // For processors, the local SRCID is between 0 & nprocs-1 |
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| 134 | |
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| 135 | #define PROC_SRCID 0 |
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| 136 | #define BDEV_SRCID 1 |
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| 137 | #define CDMA_SRCID 2 |
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| 138 | |
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| 139 | #define MEMC_TGTID 4 |
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| 140 | #define BROM_TGTID 1 |
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| 141 | //#define XICU_TGTID 2 |
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| 142 | #define ICU_TGTID 2 |
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| 143 | #define MTTY_TGTID 3 |
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| 144 | //#define IOB_TGTID 0 |
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| 145 | #define BDEV_TGTID 0 |
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| 146 | #define CDMA_TGTID 5 |
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| 147 | #define FBUF_TGTID 6 |
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| 148 | |
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| 149 | //////////////////////////////////////////////////////////////////// |
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| 150 | // TGTID & SRCID definition in IO space |
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| 151 | |
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| 152 | //#define IOB_TGTID_IO 0 |
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| 153 | //#define BDEV_TGTID_IO 1 |
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| 154 | //#define CDMA_TGTID_IO 2 |
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| 155 | //#define FBUF_TGTID_IO 3 |
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| 156 | |
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| 157 | //#define IOB_SRCID_IO 0 |
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| 158 | //#define BDEV_SRCID_IO 1 |
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| 159 | //#define CDMA_SRCID_IO 2 |
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| 160 | |
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| 161 | //////////////////////////////////////////////////////// |
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| 162 | // TGTID & SRCID definition in coherence space |
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| 163 | // For all components: global TGTID = global SRCID = cluster_index |
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| 164 | // For MEMC : local SRCID = local TGTID = nprocs |
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| 165 | // For processors : local SRCID = local TGTID = PROC_ID |
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| 166 | |
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| 167 | /////////////// |
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| 168 | // VCI format |
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| 169 | #define cell_width 4 |
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| 170 | #define address_width 32 // 40 Ã terme |
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| 171 | #define address_width_io 32 |
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| 172 | #define plen_width 8 |
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| 173 | #define error_width 1 |
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| 174 | #define clen_width 1 |
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| 175 | #define rflag_width 1 |
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| 176 | #define srcid_width 14 |
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| 177 | #define pktid_width 4 |
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| 178 | #define trdid_width 4 |
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| 179 | #define wrplen_width 1 |
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| 180 | |
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| 181 | // cluster index (computed from x,y coordinates) |
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| 182 | #define cluster(x,y) (y + ymax*x) |
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| 183 | |
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| 184 | ///////////////////////////////// |
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| 185 | int _main(int argc, char *argv[]) |
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| 186 | { |
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| 187 | using namespace sc_core; |
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| 188 | using namespace soclib::caba; |
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| 189 | using namespace soclib::common; |
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| 190 | |
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| 191 | char soft_name[128] = "giet_vm171/soft.elf"; // pathname to binary code |
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| 192 | char disk_name[128] = "giet_vm171/apps/display/images.raw"; // pathname to the disk image |
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| 193 | size_t ncycles = 1000000000; // simulated cycles |
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| 194 | size_t nprocs = 1; // number of processors per cluster |
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| 195 | bool debug_ok = false; // debug activated |
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| 196 | size_t from_cycle = 0; // debug start cycle |
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| 197 | size_t to_cycle = 1000000000; // debug end cycle |
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| 198 | |
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| 199 | ////////////// command line arguments ////////////////////// |
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| 200 | if (argc > 1) |
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| 201 | { |
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| 202 | for( int n=1 ; n<argc ; n=n+2 ) |
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| 203 | { |
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| 204 | if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) ) |
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| 205 | { |
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| 206 | ncycles = atoi(argv[n+1]); |
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| 207 | } |
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| 208 | else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) ) |
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| 209 | { |
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| 210 | nprocs = atoi(argv[n+1]); |
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| 211 | assert( (nprocs <= 8) && "The number of processors per cluster cannot be larger than 8"); |
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| 212 | } |
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| 213 | else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ) |
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| 214 | { |
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| 215 | strcpy(soft_name, argv[n+1]); |
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| 216 | } |
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| 217 | else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) |
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| 218 | { |
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| 219 | strcpy(disk_name, argv[n+1]); |
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| 220 | } |
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| 221 | else if( (strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) |
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| 222 | { |
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| 223 | debug_ok = true; |
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| 224 | from_cycle = atoi(argv[n+1]); |
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| 225 | } |
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| 226 | else if( (strcmp(argv[n],"-TOCYCLE") == 0) && (n+1<argc) ) |
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| 227 | { |
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| 228 | to_cycle = atoi(argv[n+1]); |
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| 229 | } |
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| 230 | else |
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| 231 | { |
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| 232 | std::cout << " Arguments on the command line are (key,value) couples." << std::endl; |
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| 233 | std::cout << " The order is not important." << std::endl; |
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| 234 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
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| 235 | std::cout << " -SOFT elf_file_name" << std::endl; |
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| 236 | std::cout << " -DISK disk_image_file_name" << std::endl; |
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| 237 | std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; |
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| 238 | std::cout << " -NPROCS number_of_processors_per_cluster" << std::endl; |
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| 239 | std::cout << " -DEBUG debug_start_cycle" << std::endl; |
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| 240 | std::cout << " -TOCYCLE debug_end_cycle" << std::endl; |
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| 241 | exit(0); |
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| 242 | } |
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| 243 | } |
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| 244 | } |
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| 245 | |
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| 246 | std::cout << std::endl << "*********** TSAR ARCHITECTURE **************" << std::endl |
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| 247 | << " - Interconnect = VGMN & CROSSBAR" << std::endl |
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| 248 | << " - Number of clusters 1" << std::endl |
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| 249 | << " - Number of processors per cluster = " << nprocs << std::endl |
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| 250 | << "**********************************************" << std::endl |
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| 251 | << std::endl; |
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| 252 | |
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| 253 | |
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| 254 | // Define VCI parameters |
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| 255 | typedef soclib::caba::VciParams<cell_width, |
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| 256 | plen_width, |
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| 257 | address_width, |
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| 258 | error_width, |
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| 259 | clen_width, |
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| 260 | rflag_width, |
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| 261 | srcid_width, |
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| 262 | pktid_width, |
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| 263 | trdid_width, |
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| 264 | wrplen_width> vci_param; |
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| 265 | |
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| 266 | typedef soclib::caba::VciParams<cell_width, |
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| 267 | plen_width, |
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| 268 | address_width_io, |
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| 269 | error_width, |
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| 270 | clen_width, |
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| 271 | rflag_width, |
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| 272 | srcid_width, |
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| 273 | pktid_width, |
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| 274 | trdid_width, |
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| 275 | wrplen_width> vci_param_io; |
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| 276 | ///////////////////// |
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| 277 | // Mapping Tables |
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| 278 | ///////////////////// |
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| 279 | |
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| 280 | // direct network |
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| 281 | MappingTable maptabd(address_width, |
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| 282 | IntTab(12), |
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| 283 | IntTab(srcid_width), |
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| 284 | 0xFFF00000); |
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| 285 | |
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| 286 | // maptabd.add(Segment("d_seg_memc", MEMC_BASE, MEMC_SIZE, IntTab(MEMC_TGTID), true)); |
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| 287 | maptabd.add(Segment("d_seg_memc_user", USER_BASE, USER_SIZE, IntTab(MEMC_TGTID), true)); |
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| 288 | maptabd.add(Segment("d_seg_memc_kernel", KERNEL_BASE, KERNEL_SIZE, IntTab(MEMC_TGTID), true)); |
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| 289 | maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(BROM_TGTID), true)); |
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| 290 | // maptabd.add(Segment("d_seg_xicu", XICU_BASE, XICU_SIZE, IntTab(XICU_TGTID), false)); |
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| 291 | maptabd.add(Segment("d_seg_icu", ICU_BASE, ICU_SIZE, IntTab(ICU_TGTID), false)); |
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| 292 | maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(MTTY_TGTID), false)); |
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| 293 | |
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| 294 | //maptabd.add(Segment("d_seg_tim" , TIM_BASE , TIM_SIZE , IntTab(MEMC_TGTID ), false)); |
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| 295 | maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(BDEV_TGTID ), false)); |
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| 296 | maptabd.add(Segment("d_seg_cdma", CDMA_BASE, CDMA_SIZE, IntTab(CDMA_TGTID ), false)); |
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| 297 | maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(FBUF_TGTID ), false)); |
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| 298 | |
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| 299 | std::cout << maptabd << std::endl; |
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| 300 | |
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| 301 | // coherence network |
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| 302 | MappingTable maptabc(address_width, |
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| 303 | IntTab(12), |
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| 304 | IntTab(srcid_width), |
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| 305 | 0xF0000000); |
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| 306 | |
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| 307 | std::ostringstream sm; |
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| 308 | sm << "c_seg_memc_0"; |
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| 309 | // maptabc.add(Segment(sm.str(), MEMC_BASE, MEMC_SIZE, IntTab(nprocs), false)); |
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| 310 | maptabc.add(Segment(sm.str(), USER_BASE, USER_SIZE, IntTab(nprocs), false)); |
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| 311 | maptabc.add(Segment("c_seb_memc_kernel", KERNEL_BASE, KERNEL_SIZE, IntTab(nprocs), false)); |
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| 312 | // the segment base and size will be modified |
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| 313 | // when the segmentation of the coherence space will be simplified |
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| 314 | |
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| 315 | std::ostringstream sr; |
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| 316 | sr << "c_seg_brom_0"; |
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| 317 | maptabc.add(Segment(sr.str(), BROM_BASE, BROM_SIZE, IntTab(nprocs), false)); |
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| 318 | |
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| 319 | sc_uint<address_width> avoid_collision = 0; |
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| 320 | for ( size_t p = 0 ; p < nprocs ; p++) |
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| 321 | { |
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| 322 | sc_uint<address_width> base = USER_SIZE + KERNEL_SIZE + (p*0x100000); |
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| 323 | // the following test is to avoid a collision between the c_seg_brom segment |
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| 324 | // and a c_seg_proc segment (all segments base addresses being multiple of 1Mbytes) |
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| 325 | if ( base == BROM_BASE ) avoid_collision = 0x100000; |
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| 326 | std::ostringstream sp; |
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| 327 | sp << "c_seg_proc_" << p; |
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| 328 | maptabc.add(Segment(sp.str(), base + avoid_collision, 0x20, IntTab(p), false, true, IntTab(p))); |
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| 329 | // the two last arguments will be removed |
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| 330 | // when the segmentation of the coherence space will be simplified |
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| 331 | } |
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| 332 | |
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| 333 | std::cout << maptabc << std::endl; |
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| 334 | |
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| 335 | // external network |
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| 336 | MappingTable maptabx(address_width, IntTab(1), IntTab(srcid_width), 0xF0000000); |
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| 337 | |
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| 338 | // maptabx.add(Segment("seg_memc_x", MEMC_BASE, MEMC_SIZE, IntTab(0), false)); |
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| 339 | maptabx.add(Segment("seg_memc_x_user", USER_BASE, USER_SIZE, IntTab(0), false)); |
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| 340 | maptabx.add(Segment("seg_memc_x_kernel", KERNEL_BASE, KERNEL_SIZE, IntTab(0), false)); |
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| 341 | |
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| 342 | std::cout << maptabx << std::endl; |
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| 343 | |
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| 344 | //////////////////// |
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| 345 | // Signals |
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| 346 | /////////////////// |
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| 347 | |
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| 348 | sc_clock signal_clk("clk"); |
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| 349 | sc_signal<bool> signal_resetn("resetn"); |
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| 350 | sc_signal<bool> signal_false; |
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| 351 | |
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| 352 | // IRQ signals (one signal per proc) |
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| 353 | sc_signal<bool>* signal_proc_it = |
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| 354 | alloc_elems<sc_signal<bool> >("signal_proc_it", nprocs); |
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| 355 | |
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| 356 | sc_signal<bool>* signal_irq_mtty = |
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| 357 | alloc_elems<sc_signal<bool> >("signal_irq_mtty", NB_TTYS); |
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| 358 | |
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| 359 | sc_signal<bool> signal_irq_bdev; |
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| 360 | sc_signal<bool> signal_irq_cdma; |
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| 361 | |
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| 362 | sc_signal<bool> empty; |
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| 363 | |
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| 364 | // Direct VCI signals |
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| 365 | |
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| 366 | VciSignals<vci_param>* signal_vci_ini_d_proc = |
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| 367 | alloc_elems<VciSignals<vci_param> >("signal_vci_ini_d_proc", nprocs); |
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| 368 | VciSignals<vci_param_io> signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"); |
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| 369 | VciSignals<vci_param_io> signal_vci_ini_d_cdma("signal_vci_ini_d_cdma"); |
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| 370 | |
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| 371 | VciSignals<vci_param> signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"); |
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| 372 | VciSignals<vci_param> signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"); |
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| 373 | // VciSignals<vci_param> signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"); |
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| 374 | VciSignals<vci_param> signal_vci_tgt_d_icu("signal_vci_tgt_d_icu"); |
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| 375 | VciSignals<vci_param> signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"); |
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| 376 | VciSignals<vci_param_io> signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"); |
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| 377 | VciSignals<vci_param_io> signal_vci_tgt_d_cmda("signal_vci_tgt_d_cmda"); |
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| 378 | VciSignals<vci_param_io> signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"); |
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| 379 | |
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| 380 | // Coherence VCI signals |
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| 381 | |
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| 382 | VciSignals<vci_param>* signal_vci_ini_c_proc = |
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| 383 | alloc_elems<VciSignals<vci_param> >("signal_vci_ini_c_proc", nprocs); |
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| 384 | |
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| 385 | VciSignals<vci_param>* signal_vci_tgt_c_proc = |
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| 386 | alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_c_proc", nprocs); |
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| 387 | |
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| 388 | VciSignals<vci_param> signal_vci_ini_c_memc("signal_vci_ini_c_memc"); |
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| 389 | VciSignals<vci_param> signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"); |
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| 390 | |
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| 391 | // Xternal network VCI signals |
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| 392 | |
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| 393 | VciSignals<vci_param> signal_vci_tgt_x_xram("signal_vci_tgt_x_xram"); |
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| 394 | VciSignals<vci_param> signal_vci_ini_x_memc("signal_vci_ini_x_memc"); |
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| 395 | |
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| 396 | //////////////////////////// |
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| 397 | // Components |
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| 398 | //////////////////////////// |
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| 399 | |
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| 400 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
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| 401 | |
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| 402 | |
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| 403 | soclib::common::Loader loader(soft_name); |
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| 404 | proc_iss::set_loader(loader); |
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| 405 | |
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| 406 | |
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| 407 | // External RAM |
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| 408 | VciSimpleRam<vci_param> xram( |
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| 409 | "xram", |
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| 410 | IntTab(0), |
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| 411 | maptabx, |
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| 412 | loader); |
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| 413 | |
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| 414 | // External network |
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| 415 | VciVgmn<vci_param> xnoc( |
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| 416 | "xnoc", |
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| 417 | maptabx, |
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| 418 | 1, // initiators |
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| 419 | 1, // targets |
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| 420 | 2, |
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| 421 | 2); |
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| 422 | |
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| 423 | // Direct network |
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| 424 | VciVgmn<vci_param> dnoc( |
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| 425 | "dnoc", |
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| 426 | maptabd, |
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| 427 | nprocs+2, // nb of initiators |
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| 428 | 7, // nb of targets |
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| 429 | 2, 2); //latence, FIFO depth |
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| 430 | |
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| 431 | // Coherence network |
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| 432 | VciVgmn<vci_param> cnoc( |
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| 433 | "cnoc", |
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| 434 | maptabc, |
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| 435 | nprocs+1, |
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| 436 | nprocs+1, |
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| 437 | 2, 2); |
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| 438 | |
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| 439 | // Peripherals : TTY, Frame Buffer, Block Device, Boot ROM, & DMA |
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| 440 | VciSimpleRam<vci_param> brom( |
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| 441 | "brom", |
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| 442 | IntTab(BROM_TGTID), |
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| 443 | maptabd, |
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| 444 | loader); |
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| 445 | |
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| 446 | VciMultiTty<vci_param> mtty( |
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| 447 | "mtty", |
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| 448 | IntTab(MTTY_TGTID), |
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| 449 | maptabd, |
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| 450 | "tty0","tty1","tty2","tty3", |
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| 451 | "tty4","tty5","tty6","tty7", |
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| 452 | "tty8", NULL); |
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| 453 | |
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| 454 | VciFrameBuffer<vci_param_io> fbuf( |
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| 455 | "fbuf", |
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| 456 | IntTab(FBUF_TGTID), |
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| 457 | maptabd, |
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| 458 | FBUF_XSIZE, |
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| 459 | FBUF_YSIZE); |
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| 460 | |
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| 461 | VciBlockDeviceTsarV4<vci_param_io> bdev( |
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| 462 | // VciBlockDevice<vci_param_io> bdev( |
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| 463 | "bdev", |
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| 464 | maptabd, |
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| 465 | IntTab(BDEV_SRCID), // SRCID_D |
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| 466 | IntTab(BDEV_TGTID), // TGTID_D |
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| 467 | disk_name, |
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| 468 | SECTOR_SIZE, |
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| 469 | 32); // burst size |
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| 470 | |
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| 471 | VciDmaTsarV2<vci_param_io> cdma( |
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| 472 | "cdma", |
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| 473 | maptabd, |
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| 474 | IntTab(CDMA_SRCID), // SRCID_D |
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| 475 | IntTab(CDMA_TGTID), // TGTID_D |
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| 476 | 64); |
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| 477 | |
---|
| 478 | // processors (nprocs per cluster) |
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| 479 | |
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| 480 | VciCcVCacheWrapperV4<vci_param, proc_iss> *proc[nprocs]; |
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| 481 | |
---|
| 482 | for ( size_t p = 0 ; p < nprocs ; p++ ) |
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| 483 | { |
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| 484 | |
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| 485 | std::ostringstream sp; |
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| 486 | sp << "proc_" << "_" << p; |
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| 487 | |
---|
| 488 | proc[p] = new VciCcVCacheWrapperV4<vci_param, proc_iss>( |
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| 489 | sp.str().c_str(), |
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| 490 | p, |
---|
| 491 | maptabd, maptabc, |
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| 492 | IntTab(PROC_SRCID+p), // SRCID_D |
---|
| 493 | IntTab(PROC_SRCID+p), // SRCID_C |
---|
| 494 | IntTab(PROC_SRCID+p), // TGTID_C |
---|
| 495 | 4,4, // itlb ways, sets |
---|
| 496 | 4,4, // dtlb ways, sets |
---|
| 497 | 4,64,16,4,64,16, // Icache and Dcache sizes (way, set, words) |
---|
| 498 | 4,8, |
---|
| 499 | 20000000, |
---|
| 500 | from_cycle, |
---|
| 501 | false |
---|
| 502 | ); |
---|
| 503 | } |
---|
| 504 | |
---|
| 505 | // memory caches (one per cluster) |
---|
| 506 | VciMemCacheV4<vci_param> memc( |
---|
| 507 | sm.str().c_str(), |
---|
| 508 | maptabd, maptabc, maptabx, |
---|
| 509 | IntTab(0), // SRCID_X |
---|
| 510 | IntTab(nprocs), // SRCID_C |
---|
| 511 | IntTab(MEMC_TGTID), // TGTID_D |
---|
| 512 | IntTab(nprocs), // TGTID_C |
---|
| 513 | 16,256,16, // CACHE SIZE |
---|
| 514 | 4096, // HEAP SIZE |
---|
| 515 | 4,4, // TRANSACTION and UPDATE TAB lines |
---|
| 516 | from_cycle, |
---|
| 517 | debug_ok |
---|
| 518 | ); |
---|
| 519 | /* |
---|
| 520 | // XICU (one per cluster) |
---|
| 521 | VciXicu<vci_param> xicu( |
---|
| 522 | "vci_xicu", |
---|
| 523 | maptabd, |
---|
| 524 | IntTab(XICU_TGTID), // TGTID_D |
---|
| 525 | nprocs, // number of TIMERS |
---|
| 526 | NB_TTYS, // number of hard IRQs |
---|
| 527 | nprocs+1, // number of soft IRQs |
---|
| 528 | nprocs); // number of output IRQ lines |
---|
| 529 | */ |
---|
| 530 | // ICU |
---|
| 531 | /* |
---|
| 532 | VciIcu<vci_param> icu( |
---|
| 533 | "vci_icu", |
---|
| 534 | IntTab(ICU_TGTID), // TGTID_D |
---|
| 535 | maptabd, |
---|
| 536 | NB_TTYS + 2 // number of hard IRQs |
---|
| 537 | ); |
---|
| 538 | */ |
---|
| 539 | VciMultiIcu<vci_param> *icu; |
---|
| 540 | icu = new VciMultiIcu<vci_param>("icu", |
---|
| 541 | IntTab(ICU_TGTID), |
---|
| 542 | maptabd, |
---|
| 543 | 32, // number of irq in |
---|
| 544 | 1); //NB_PROCS number of irq out |
---|
| 545 | |
---|
| 546 | |
---|
| 547 | std::cout << "all components created" << std::endl; |
---|
| 548 | |
---|
| 549 | /////////////////////////////////////////////////////////////// |
---|
| 550 | // Net-list |
---|
| 551 | /////////////////////////////////////////////////////////////// |
---|
| 552 | |
---|
| 553 | // External Ram (one instance) |
---|
| 554 | xram.p_clk (signal_clk); |
---|
| 555 | xram.p_resetn (signal_resetn); |
---|
| 556 | xram.p_vci (signal_vci_tgt_x_xram); |
---|
| 557 | |
---|
| 558 | // External Network (one instance) |
---|
| 559 | xnoc.p_clk (signal_clk); |
---|
| 560 | xnoc.p_resetn (signal_resetn); |
---|
| 561 | xnoc.p_to_target[0] (signal_vci_tgt_x_xram); |
---|
| 562 | xnoc.p_to_initiator[0] (signal_vci_ini_x_memc); |
---|
| 563 | |
---|
| 564 | // Direct Network (one instance) |
---|
| 565 | dnoc.p_clk (signal_clk); |
---|
| 566 | dnoc.p_resetn (signal_resetn); |
---|
| 567 | dnoc.p_to_target[MEMC_TGTID] (signal_vci_tgt_d_memc); |
---|
| 568 | dnoc.p_to_target[BROM_TGTID] (signal_vci_tgt_d_brom); |
---|
| 569 | // dnoc.p_to_target[XICU_TGTID] (signal_vci_tgt_d_xicu); |
---|
| 570 | dnoc.p_to_target[ICU_TGTID] (signal_vci_tgt_d_icu); |
---|
| 571 | dnoc.p_to_target[MTTY_TGTID] (signal_vci_tgt_d_mtty); |
---|
| 572 | dnoc.p_to_target[BDEV_TGTID] (signal_vci_tgt_d_bdev); |
---|
| 573 | dnoc.p_to_target[CDMA_TGTID] (signal_vci_tgt_d_cmda); |
---|
| 574 | dnoc.p_to_target[FBUF_TGTID] (signal_vci_tgt_d_fbuf); |
---|
| 575 | |
---|
| 576 | dnoc.p_to_initiator[BDEV_SRCID] (signal_vci_ini_d_bdev); |
---|
| 577 | dnoc.p_to_initiator[CDMA_SRCID] (signal_vci_ini_d_cdma); |
---|
| 578 | |
---|
| 579 | // Coherence Network (one instance) |
---|
| 580 | cnoc.p_clk (signal_clk); |
---|
| 581 | cnoc.p_resetn (signal_resetn); |
---|
| 582 | cnoc.p_to_initiator[nprocs] (signal_vci_ini_c_memc); |
---|
| 583 | cnoc.p_to_target[nprocs] (signal_vci_tgt_c_memc); |
---|
| 584 | |
---|
| 585 | // Processors |
---|
| 586 | for ( size_t p = 0 ; p < nprocs ; p++ ) |
---|
| 587 | { |
---|
| 588 | dnoc.p_to_initiator[p] (signal_vci_ini_d_proc[p]); |
---|
| 589 | cnoc.p_to_initiator[p] (signal_vci_ini_c_proc[p]); |
---|
| 590 | cnoc.p_to_target[p] (signal_vci_tgt_c_proc[p]); |
---|
| 591 | |
---|
| 592 | proc[p]->p_clk (signal_clk); |
---|
| 593 | proc[p]->p_resetn (signal_resetn); |
---|
| 594 | proc[p]->p_vci_ini_d (signal_vci_ini_d_proc[p]); |
---|
| 595 | proc[p]->p_vci_ini_c (signal_vci_ini_c_proc[p]); |
---|
| 596 | proc[p]->p_vci_tgt_c (signal_vci_tgt_c_proc[p]); |
---|
| 597 | proc[p]->p_irq[0] (signal_proc_it[p]); |
---|
| 598 | for ( size_t j = 1 ; j < 6 ; j++ ) |
---|
| 599 | { |
---|
| 600 | proc[p]->p_irq[j] (signal_false); |
---|
| 601 | } |
---|
| 602 | } |
---|
| 603 | |
---|
| 604 | |
---|
| 605 | /* |
---|
| 606 | // XICU |
---|
| 607 | xicu.p_clk (signal_clk); |
---|
| 608 | xicu.p_resetn (signal_resetn); |
---|
| 609 | xicu.p_vci (signal_vci_tgt_d_xicu); |
---|
| 610 | for ( size_t p = 0 ; p < nprocs ; p++ ) |
---|
| 611 | { |
---|
| 612 | xicu.p_irq[p] (signal_proc_it[p]); |
---|
| 613 | } |
---|
| 614 | |
---|
| 615 | for(size_t i=0 ; i<NB_TTYS ; i++) |
---|
| 616 | { |
---|
| 617 | xicu.p_hwi[i] (signal_irq_mtty[i]); |
---|
| 618 | } |
---|
| 619 | */ |
---|
| 620 | // ICU |
---|
| 621 | icu->p_clk (signal_clk); |
---|
| 622 | icu->p_resetn (signal_resetn); |
---|
| 623 | icu->p_vci (signal_vci_tgt_d_icu); |
---|
| 624 | icu->p_irq_out[0] (signal_proc_it[0]); |
---|
| 625 | |
---|
| 626 | for (size_t i = 0 ; i < 32 ; i++ ) |
---|
| 627 | { |
---|
| 628 | // if ( i < NB_TIMERS ) icu->p_irq_in[i] (signal_irq_tim[i]); |
---|
| 629 | if ( i < 8 ) icu->p_irq_in[i] (signal_false); |
---|
| 630 | else if ( i == 8) icu->p_irq_in[i] (signal_irq_cdma); |
---|
| 631 | else if ( i < 16 ) icu->p_irq_in[i] (signal_false); |
---|
| 632 | else if ( i < (16 + NB_TTYS) ) icu->p_irq_in[i] (signal_irq_mtty[i-16]); |
---|
| 633 | else if ( i < 31 ) icu->p_irq_in[i] (signal_false); |
---|
| 634 | else icu->p_irq_in[i] (signal_irq_bdev); |
---|
| 635 | } |
---|
| 636 | |
---|
| 637 | // MEMC |
---|
| 638 | memc.p_clk (signal_clk); |
---|
| 639 | memc.p_resetn (signal_resetn); |
---|
| 640 | memc.p_vci_tgt (signal_vci_tgt_d_memc); |
---|
| 641 | memc.p_vci_ini (signal_vci_ini_c_memc); |
---|
| 642 | memc.p_vci_tgt_cleanup (signal_vci_tgt_c_memc); |
---|
| 643 | memc.p_vci_ixr (signal_vci_ini_x_memc); |
---|
| 644 | |
---|
| 645 | brom.p_clk (signal_clk); |
---|
| 646 | brom.p_resetn (signal_resetn); |
---|
| 647 | brom.p_vci (signal_vci_tgt_d_brom); |
---|
| 648 | |
---|
| 649 | mtty.p_clk (signal_clk); |
---|
| 650 | mtty.p_resetn (signal_resetn); |
---|
| 651 | mtty.p_vci (signal_vci_tgt_d_mtty); |
---|
| 652 | |
---|
| 653 | for(size_t i=0 ; i<NB_TTYS ; i++) |
---|
| 654 | { |
---|
| 655 | mtty.p_irq[i] (signal_irq_mtty[i]); |
---|
| 656 | } |
---|
| 657 | |
---|
| 658 | bdev.p_clk (signal_clk); |
---|
| 659 | bdev.p_resetn (signal_resetn); |
---|
| 660 | bdev.p_irq (signal_irq_bdev); |
---|
| 661 | bdev.p_vci_target (signal_vci_tgt_d_bdev); |
---|
| 662 | bdev.p_vci_initiator (signal_vci_ini_d_bdev); |
---|
| 663 | |
---|
| 664 | cdma.p_clk (signal_clk); |
---|
| 665 | cdma.p_resetn (signal_resetn); |
---|
| 666 | cdma.p_irq (signal_irq_cdma); |
---|
| 667 | cdma.p_vci_target (signal_vci_tgt_d_cmda); |
---|
| 668 | cdma.p_vci_initiator (signal_vci_ini_d_cdma); |
---|
| 669 | |
---|
| 670 | fbuf.p_clk (signal_clk); |
---|
| 671 | fbuf.p_resetn (signal_resetn); |
---|
| 672 | fbuf.p_vci (signal_vci_tgt_d_fbuf); |
---|
| 673 | |
---|
| 674 | |
---|
| 675 | std::cout << "all components connected" << std::endl; |
---|
| 676 | |
---|
| 677 | //////////////////////////////////////////////////////// |
---|
| 678 | // Simulation |
---|
| 679 | /////////////////////////////////////////////////////// |
---|
| 680 | |
---|
| 681 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
| 682 | signal_resetn = false; |
---|
| 683 | |
---|
| 684 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 685 | signal_resetn = true; |
---|
| 686 | char buf[1]; |
---|
| 687 | |
---|
| 688 | for(size_t i=1 ; i<ncycles ; i++) |
---|
| 689 | { |
---|
| 690 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 691 | |
---|
| 692 | if( debug_ok && (i > from_cycle) && (i < to_cycle) ) |
---|
| 693 | { |
---|
| 694 | std::cout << std::dec << "*************** cycle " << i << " ***********************" << std::endl; |
---|
| 695 | proc[0]->print_trace(); |
---|
| 696 | std::cout << std::endl; |
---|
| 697 | |
---|
| 698 | memc.print_trace(); |
---|
| 699 | std::cout << std::endl; |
---|
| 700 | |
---|
| 701 | icu->print_trace(); |
---|
| 702 | std::cout << std::endl; |
---|
| 703 | |
---|
| 704 | // bdev.print_trace(); |
---|
| 705 | // std::cout << std::endl; |
---|
| 706 | |
---|
| 707 | xram.print_trace(); |
---|
| 708 | std::cout << std::endl; |
---|
| 709 | } |
---|
| 710 | } |
---|
| 711 | |
---|
| 712 | std::cout << "Hit ENTER to end simulation" << std::endl; |
---|
| 713 | std::cin.getline(buf,1); |
---|
| 714 | |
---|
| 715 | // for ( size_t p = 0 ; p < nprocs ; p++ ) |
---|
| 716 | // proc[p]->print_stats(); |
---|
| 717 | |
---|
| 718 | return EXIT_SUCCESS; |
---|
| 719 | } |
---|
| 720 | |
---|
| 721 | int sc_main (int argc, char *argv[]) |
---|
| 722 | { |
---|
| 723 | try { |
---|
| 724 | return _main(argc, argv); |
---|
| 725 | } catch (std::exception &e) { |
---|
| 726 | std::cout << e.what() << std::endl; |
---|
| 727 | } catch (...) { |
---|
| 728 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 729 | throw; |
---|
| 730 | } |
---|
| 731 | return 1; |
---|
| 732 | } |
---|