| 1 | /********************************************************************************
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| 2 | * File : giet.S
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| 3 | * Author : Alain Greiner
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| 4 | * Date : 15/01/2014
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| 5 | *********************************************************************************
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| 6 | * This is a very simple Interrupts/Exception/Traps handler for a generic
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| 7 | * multi-clusters / multi-processors TSAR architecture (up to 256 clusters,
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| 8 | * up to 4 processors per cluster).
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| 9 | * The physical address is 40 bits, and the 8 MSB bits A[39:32] define the
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| 10 | * cluster index.
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| 11 | ********************************************************************************/
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| 12 |
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| 13 | #include "hard_config.h"
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| 14 |
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| 15 | .section .giet,"ax",@progbits
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| 16 | .align 2
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| 17 | .global _interrupt_vector
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| 18 |
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| 19 | .extern seg_xcu_base
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| 20 | .extern seg_tty_base
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| 21 |
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| 22 | .extern _procid
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| 23 | .extern _proctime
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| 24 | .extern _tty_write
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| 25 | .extern _tty_read
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| 26 | .extern _tty_read_irq
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| 27 | .extern _locks_read
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| 28 | .extern _locks_write
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| 29 | .extern _exit
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| 30 | .extern _fb_sync_write
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| 31 | .extern _fb_sync_read
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| 32 | .extern _ioc_write
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| 33 | .extern _ioc_read
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| 34 | .extern _ioc_completed
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| 35 | .extern _itoa_hex
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| 36 | .extern _barrier_init
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| 37 | .extern _barrier_wait
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| 38 |
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| 39 | .ent _giet
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| 40 |
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| 41 | /****************************************************************
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| 42 | * Cause Table (indexed by the Cause register)
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| 43 | ****************************************************************/
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| 44 | tab_causes:
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| 45 | .word _int_handler /* 0000 : external interrupt */
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| 46 | .word _cause_ukn /* 0001 : undefined exception */
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| 47 | .word _cause_ukn /* 0010 : undefined exception */
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| 48 | .word _cause_ukn /* 0011 : undefined exception */
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| 49 | .word _cause_adel /* 0100 : illegal address read exception */
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| 50 | .word _cause_ades /* 0101 : illegal address write exception */
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| 51 | .word _cause_ibe /* 0110 : instruction bus error exception */
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| 52 | .word _cause_dbe /* 0111 : data bus error exception */
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| 53 | .word _sys_handler /* 1000 : system call */
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| 54 | .word _cause_bp /* 1001 : breakpoint exception */
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| 55 | .word _cause_ri /* 1010 : illegal codop exception */
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| 56 | .word _cause_cpu /* 1011 : illegal coprocessor access */
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| 57 | .word _cause_ovf /* 1100 : arithmetic overflow exception */
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| 58 | .word _cause_ukn /* 1101 : undefined exception */
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| 59 | .word _cause_ukn /* 1110 : undefined exception */
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| 60 | .word _cause_ukn /* 1111 : undefined exception */
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| 61 |
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| 62 | .space 320
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| 63 |
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| 64 | /****************************************************************
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| 65 | * Entry point (base + 0x180)
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| 66 | ****************************************************************/
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| 67 | _giet:
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| 68 | mfc0 $27, $13 /* Cause Register analysis */
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| 69 | la $26, seg_kcode_base /* $26 <= tab_causes */
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| 70 | andi $27, $27, 0x3c
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| 71 | addu $26, $26, $27 /* $26 <= &tab_causes[XCODE] */
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| 72 | lw $26, ($26)
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| 73 | jr $26 /* Jump to tab_causes[XCODE] */
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| 74 |
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| 75 | .end _giet
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| 76 |
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| 77 | /****************************************************************
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| 78 | * System Call Handler
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| 79 | *
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| 80 | * As the GIET_TSAR does not support system calls,
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| 81 | * an error message is displayed on TTY0, the program is killed.
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| 82 | ****************************************************************/
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| 83 | .ent _sys_handler
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| 84 |
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| 85 | _sys_handler:
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| 86 | la $4, _msg_uknsyscall /* $4 <= message address */
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| 87 | li $5, 36 /* $5 <= message length */
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| 88 | li $6, 0 /* $6 <= TTY0 */
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| 89 | jal _tty_write /* print unknown message */
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| 90 | nop
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| 91 |
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| 92 | la $4, _msg_epc /* $4 <= message address */
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| 93 | li $5, 8 /* $5 <= message length */
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| 94 | li $6, 0 /* $6 <= TTY0 */
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| 95 | jal _tty_write /* print EPC message */
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| 96 | nop
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| 97 |
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| 98 | mfc0 $4, $14 /* $4 <= EPC */
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| 99 | la $5, _itoa_buffer /* $5 <= buffer address */
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| 100 | addiu $5, $5, 2 /* skip the 0x prefix */
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| 101 | jal _itoa_hex /* fill the buffer */
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| 102 | nop
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| 103 |
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| 104 | la $4, _itoa_buffer /* $4 <= buffer address */
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| 105 | li $5, 10 /* $5 <= buffer length */
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| 106 | li $6, 0 /* $6 <= TTY0 */
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| 107 | jal _tty_write /* print EPC value */
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| 108 | nop
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| 109 |
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| 110 | j _exit /* end of program */
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| 111 |
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| 112 | _itoa_buffer: .ascii "0x00000000"
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| 113 |
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| 114 | .align 2
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| 115 |
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| 116 | .end _sys_handler
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| 117 |
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| 118 | /****************************************************************
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| 119 | * Interrupt Handler
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| 120 | * This simple interrupt handler cannot be interrupted.
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| 121 | * It uses the SoCLib VCI_XICU component.
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| 122 | * It makes the assumption that there is only one interrupt per
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| 123 | * entry in the interrupt vector (it can be PTI, HWI, or WTI).
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| 124 | * In case of a multi-clusters architecture, it exist one XCU
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| 125 | * per cluster, and the base address of the ICU segment depends
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| 126 | * on both the cluster_xy and the proc_id:
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| 127 | * - base_address = seg_xcu_base + (32*local_id) + (4G*cluster_xy)
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| 128 | * - cluster_xy = proc_id / NB_PROCS_MAX
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| 129 | * - local_id = proc_id % NB_PROCS_MAX
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| 130 | * If no active interrupt is found in the PRIO register,
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| 131 | * nothing is done.
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| 132 | * The interrupt vector (32 ISR addresses array stored at
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| 133 | * _interrupt_vector address) is initialised with the default
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| 134 | * ISR address. The actual ISR addresses are supposed to be written
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| 135 | * in the interrupt vector array by the boot code.
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| 136 | * All non persistant registers, such as $1 to $15, and $24 to $25,
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| 137 | * as well as register $31 and EPC, are saved in the interrupted
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| 138 | * program stack, before calling the Interrupt Service Routine.
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| 139 | * These registers can be used by the ISR code.
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| 140 | ***************************************************************/
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| 141 | .ent _int_handler
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| 142 |
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| 143 | _int_handler:
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| 144 | addiu $29, $29, -23*4 /* stack space reservation */
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| 145 | .set noat
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| 146 | sw $1, 4*4($29) /* save $1 */
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| 147 | .set at
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| 148 | sw $2, 4*5($29) /* save $2 */
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| 149 | sw $3, 4*6($29) /* save $3 */
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| 150 | sw $4, 4*7($29) /* save $4 */
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| 151 | sw $5, 4*8($29) /* save $5 */
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| 152 | sw $6, 4*9($29) /* save $6 */
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| 153 | sw $7, 4*10($29) /* save $7 */
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| 154 | sw $8, 4*11($29) /* save $8 */
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| 155 | sw $9, 4*12($29) /* save $9 */
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| 156 | sw $10, 4*13($29) /* save $10 */
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| 157 | sw $11, 4*14($29) /* save $11 */
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| 158 | sw $12, 4*15($29) /* save $12 */
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| 159 | sw $13, 4*16($29) /* save $13 */
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| 160 | sw $14, 4*17($29) /* save $14 */
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| 161 | sw $15, 4*18($29) /* save $15 */
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| 162 | sw $24, 4*19($29) /* save $24 */
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| 163 | sw $25, 4*20($29) /* save $25 */
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| 164 | sw $31, 4*21($29) /* save $31 */
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| 165 | mfc0 $27, $14
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| 166 | sw $27, 4*22($29) /* save EPC */
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| 167 |
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| 168 | /* XICU PRIO register address computation */
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| 169 | /* It depends on both the cluster_xy & local_id, */
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| 170 | /* and we must use the physical address extension */
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| 171 | mfc0 $10, $15, 1 /* $10 <= proc_id */
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| 172 | andi $10, $10, 0x3FF /* at most 1024 processors */
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| 173 | li $11, NB_PROCS_MAX
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| 174 | divu $10, $11
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| 175 | mflo $12 /* $12 <= cluster_xy */
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| 176 | mfhi $13 /* $13 <= local_id */
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| 177 | la $14, seg_xcu_base /* $14 <= seg_xcu_base */
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| 178 |
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| 179 | li $7, 0b011110000000 /* $7 <= PRIO offset */
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| 180 | sll $8, $13, 2 /* $8 <= local_id*4 */
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| 181 | addu $9, $7, $8 /* $9 <= PRIO offset + local_id*4 */
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| 182 | addu $26, $9, $14 /* $26 <= seg_icu_base + PRIO offset + local_id*4 */
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| 183 |
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| 184 | /* XCU[cluster_xy] access to get PRIO register value */
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| 185 | mtc2 $12, $24 /* set PADDR extension */
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| 186 | lw $15, 0($26) /* $15 <= PRIO register value */
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| 187 | mtc2 $0, $24 /* reset PADDR extension */
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| 188 |
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| 189 | /* test PTI, then HWI, then WTI */
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| 190 | andi $27, $15, 0x1 /* test bit T in PRIO register */
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| 191 | bne $27, $0, _int_PTI /* branch to PTI handler */
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| 192 | andi $27, $15, 0x2 /* test bit W in PRIO register */
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| 193 | bne $27, $0, _int_HWI /* branch to HWI handler */
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| 194 | andi $27, $15, 0x4 /* test bit W in PRIO register */
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| 195 | bne $27, $0, _int_WTI /* branch to WTI handler */
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| 196 |
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| 197 | /* exit interrupt handler: restore registers */
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| 198 | _int_restore:
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| 199 | .set noat
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| 200 | lw $1, 4*4($29)
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| 201 | .set at
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| 202 | lw $2, 4*5($29)
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| 203 | lw $3, 4*6($29)
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| 204 | lw $4, 4*7($29)
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| 205 | lw $5, 4*8($29)
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| 206 | lw $6, 4*9($29)
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| 207 | lw $7, 4*10($29)
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| 208 | lw $8, 4*11($29)
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| 209 | lw $9, 4*12($29)
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| 210 | lw $10, 4*13($29)
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| 211 | lw $11, 4*14($29)
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| 212 | lw $12, 4*15($29)
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| 213 | lw $13, 4*16($29)
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| 214 | lw $14, 4*17($29)
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| 215 | lw $15, 4*18($29)
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| 216 | lw $24, 4*19($29)
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| 217 | lw $25, 4*20($29)
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| 218 | lw $31, 4*21($29)
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| 219 | lw $27, 4*22($29) /* get EPC */
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| 220 | addiu $29, $29, 23*4 /* restore SP */
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| 221 | mtc0 $27, $14 /* restore EPC */
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| 222 | eret /* exit GIET */
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| 223 |
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| 224 | /* The PTI handler get PTI index, */
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| 225 | /* acknowledge the PTI register */
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| 226 | /* and call the corresponding ISR */
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| 227 | _int_PTI:
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| 228 | srl $26, $15, 6 /* $26 <= PRIO >> 6 */
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| 229 | andi $26, $26, 0x7C /* $26 <= PTI_INDEX * 4 */
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| 230 | addi $27, $14, 0x180 /* $27 <= &PTI_ACK[0] */
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| 231 | add $27, $27, $26 /* $27 <= &PTI_ACK[PTI_INDEX] */
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| 232 | lw $0, ($27) /* acknowledge XICU PTI */
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| 233 | la $27, _interrupt_vector
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| 234 | addu $26, $26, $27
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| 235 | lw $26, ($26) /* read ISR address */
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| 236 | jalr $26 /* call ISR */
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| 237 | nop
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| 238 | j _int_restore /* return from INT handler */
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| 239 | nop
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| 240 |
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| 241 | /* The HWI handler get HWI index */
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| 242 | /* and call the corresponding ISR */
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| 243 | _int_HWI:
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| 244 | srl $26, $15, 14 /* $26 <= PRIO >> 14 */
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| 245 | andi $26, $26, 0x7C /* $26 <= HWI_INDEX * 4 */
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| 246 | la $27, _interrupt_vector
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| 247 | addu $26, $26, $27 /* $26 <= &ISR[HWI_INDEX */
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| 248 | lw $26, ($26) /* read ISR address */
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| 249 | jalr $26 /* call ISR */
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| 250 | nop
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| 251 | j _int_restore /* return from INT handler */
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| 252 | nop
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| 253 |
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| 254 | /* The WTI handler get WTI index, */
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| 255 | /* acknowledge the WTI register */
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| 256 | /* and call the corresponding ISR */
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| 257 | _int_WTI:
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| 258 | srl $26, $15, 22 /* $26 <= PRIO >> 22 */
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| 259 | andi $26, $26, 0x7C /* $26 <= WTI_INDEX * 4 */
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| 260 | add $27, $14, $26 /* $27 <= &WTI_REG[WTI_INDEX] */
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| 261 | lw $0, ($27) /* acknowledge XICU WTI */
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| 262 | la $27, _interrupt_vector
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| 263 | addu $26, $26, $27 /* $26 <= &ISR[WTI_INDEX] */
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| 264 | lw $26, ($26) /* read ISR address */
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| 265 | jalr $26 /* call ISR */
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| 266 | nop
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| 267 | j _int_restore /* return from INT handler */
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| 268 | nop
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| 269 |
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| 270 | /* The default ISR is called when no specific ISR has been installed */
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| 271 | /* in the interrupt vector. It simply displays a message on TTY0 */
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| 272 |
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| 273 | isr_default:
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| 274 | addiu $29, $29, -20 /* get space in stack */
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| 275 | sw $31, 16($29) /* to save the return address */
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| 276 | la $4, _msg_default /* $4 <= string address */
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| 277 | addi $5, $0, 36 /* $5 <= string length */
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| 278 | li $6, 0 /* $6 <= TTY0 */
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| 279 | jal _tty_write
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| 280 | lw $31, 16($29) /* restore return address */
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| 281 | addiu $29, $29, 20 /* free space */
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| 282 | jr $31 /* returns to interrupt handler */
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| 283 |
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| 284 | /****************************************************************
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| 285 | * Interrupt Vector Table (indexed by interrupt index)
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| 286 | * 32 words corresponding to 32 ISR addresses
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| 287 | ****************************************************************/
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| 288 | _interrupt_vector:
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| 289 | .word isr_default /* ISR 0 */
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| 290 | .word isr_default /* ISR 1 */
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| 291 | .word isr_default /* ISR 2 */
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| 292 | .word isr_default /* ISR 3 */
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| 293 | .word isr_default /* ISR 4 */
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| 294 | .word isr_default /* ISR 5 */
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| 295 | .word isr_default /* ISR 6 */
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| 296 | .word isr_default /* ISR 7 */
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| 297 | .word isr_default /* ISR 8 */
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| 298 | .word isr_default /* ISR 9 */
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| 299 | .word isr_default /* ISR 10 */
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| 300 | .word isr_default /* ISR 11 */
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| 301 | .word isr_default /* ISR 12 */
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| 302 | .word isr_default /* ISR 13 */
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| 303 | .word isr_default /* ISR 14 */
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| 304 | .word isr_default /* ISR 15 */
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| 305 | .word isr_default /* ISR 16 */
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| 306 | .word isr_default /* ISR 17 */
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| 307 | .word isr_default /* ISR 18 */
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| 308 | .word isr_default /* ISR 19 */
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| 309 | .word isr_default /* ISR 20 */
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| 310 | .word isr_default /* ISR 21 */
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| 311 | .word isr_default /* ISR 22 */
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| 312 | .word isr_default /* ISR 23 */
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| 313 | .word isr_default /* ISR 24 */
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| 314 | .word isr_default /* ISR 25 */
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| 315 | .word isr_default /* ISR 26 */
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| 316 | .word isr_default /* ISR 27 */
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| 317 | .word isr_default /* ISR 28 */
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| 318 | .word isr_default /* ISR 29 */
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| 319 | .word isr_default /* ISR 30 */
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| 320 | .word isr_default /* ISR 31 */
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| 321 |
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| 322 | .end _int_handler
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| 323 |
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| 324 | /****************************************************************
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| 325 | * Exception Handler
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| 326 | * Same code for all fatal exceptions :
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| 327 | * Print the exception type and the values of EPC & BAR
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| 328 | * on the TTY correspondintg to the processor PROCID,
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| 329 | * and the user program is killed.
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| 330 | ****************************************************************/
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| 331 | .ent _exc_handler
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| 332 |
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| 333 | _exc_handler:
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| 334 | _cause_bp:
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| 335 | _cause_ukn:
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| 336 | _cause_ri:
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| 337 | _cause_ovf:
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| 338 | _cause_adel:
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| 339 | _cause_ades:
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| 340 | _cause_ibe:
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| 341 | _cause_dbe:
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| 342 | _cause_cpu:
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| 343 | mfc0 $26, $13 /* $26 <= CR */
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| 344 | andi $26, $26, 0x3C /* $26 <= _cause_index * 4 */
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| 345 | la $27, _mess_causes /* mess_cause table base address */
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| 346 | addu $27, $26, $27 /* $26 <= message base address */
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| 347 |
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| 348 | /* take the lock on TTY0 */
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| 349 | li $4, 0
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| 350 | jal _tty_get_lock
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| 351 | nop
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| 352 |
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| 353 | /* display exception type */
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| 354 | lw $4, ($27) /* $4 <= message address */
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| 355 | li $5, 36 /* $5 <= message length */
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| 356 | li $6, 0 /* $6 <= TTY0 */
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| 357 | jal _tty_write
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| 358 | nop
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| 359 |
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| 360 | /* display EPC value */
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| 361 | la $4, _msg_epc /* $4 <= message address */
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| 362 | li $5, 8 /* $5 <= message length */
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| 363 | li $6, 0 /* $6 <= TTY0 */
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| 364 | jal _tty_write
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| 365 | nop
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| 366 |
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| 367 | mfc0 $4, $14 /* $4 <= EPC value */
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| 368 | la $5, _itoa_buffer /* $5 <= buffer address */
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| 369 | addiu $5, $5, 2 /* skip 0x prefix */
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| 370 | jal _itoa_hex /* fill buffer */
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| 371 | nop
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| 372 |
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| 373 | la $4, _itoa_buffer /* $4 <= buffer address */
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| 374 | li $5, 10 /* $5 <= buffer length */
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| 375 | li $6, 0 /* $6 <= TTY0 */
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| 376 | jal _tty_write
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| 377 | nop
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| 378 |
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| 379 | /* display BAR value */
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| 380 | la $4, _msg_bar /* $4 <= message address */
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| 381 | li $5, 8 /* $5 <= message length */
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| 382 | li $6, 0 /* $6 <= TTY0 */
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| 383 | jal _tty_write
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| 384 | nop
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| 385 |
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| 386 | mfc0 $4, $8 /* $4 <= BAR value */
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| 387 | la $5, _itoa_buffer /* $5 <= buffer address */
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| 388 | addiu $5, $5, 2 /* skip 0x prefix */
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| 389 | jal _itoa_hex /* fill buffer */
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| 390 | nop
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| 391 |
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| 392 | la $4, _itoa_buffer /* $4 <= message address */
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| 393 | li $5, 10 /* $5 <= message length */
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| 394 | li $6, 0 /* $6 <= TTY0 */
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| 395 | jal _tty_write
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| 396 | nop
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| 397 |
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| 398 |
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| 399 | /* release the lock on TTY0 */
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| 400 | li $4, 0
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|---|
| 401 | jal _tty_get_lock
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| 402 | nop
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|---|
| 403 |
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| 404 | j _exit /* kill user program */
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| 405 |
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| 406 | /* Exceptions Messages table (indexed by XCODE) */
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| 407 | _mess_causes:
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| 408 | .word _msg_ukncause
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| 409 | .word _msg_ukncause
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|---|
| 410 | .word _msg_ukncause
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|---|
| 411 | .word _msg_ukncause
|
|---|
| 412 | .word _msg_adel
|
|---|
| 413 | .word _msg_ades
|
|---|
| 414 | .word _msg_ibe
|
|---|
| 415 | .word _msg_dbe
|
|---|
| 416 | .word _msg_ukncause
|
|---|
| 417 | .word _msg_bp
|
|---|
| 418 | .word _msg_ri
|
|---|
| 419 | .word _msg_cpu
|
|---|
| 420 | .word _msg_ovf
|
|---|
| 421 | .word _msg_ukncause
|
|---|
| 422 | .word _msg_ukncause
|
|---|
| 423 | .word _msg_ukncause
|
|---|
| 424 |
|
|---|
| 425 | /********************************************************************
|
|---|
| 426 | * All messages
|
|---|
| 427 | * Messages length are fixed : 8 or 36 characters...
|
|---|
| 428 | ********************************************************************/
|
|---|
| 429 | _msg_bar: .asciiz "\nBAR = "
|
|---|
| 430 | _msg_epc: .asciiz "\nEPC = "
|
|---|
| 431 | _msg_default: .asciiz "\n\n !!! Default ISR !!! \n"
|
|---|
| 432 | _msg_uknsyscall: .asciiz "\n\n !!! Undefined System Call !!! \n"
|
|---|
| 433 | _msg_ukncause: .asciiz "\n\nException : strange unknown cause\n"
|
|---|
| 434 | _msg_adel: .asciiz "\n\nException : illegal read address \n"
|
|---|
| 435 | _msg_ades: .asciiz "\n\nException : illegal write address\n"
|
|---|
| 436 | _msg_ibe: .asciiz "\n\nException : inst bus error \n"
|
|---|
| 437 | _msg_dbe: .asciiz "\n\nException : data bus error \n"
|
|---|
| 438 | _msg_bp: .asciiz "\n\nException : breakpoint \n"
|
|---|
| 439 | _msg_ri: .asciiz "\n\nException : reserved instruction \n"
|
|---|
| 440 | _msg_ovf: .asciiz "\n\nException : arithmetic overflow \n"
|
|---|
| 441 | _msg_cpu: .asciiz "\n\nException : illegal coproc access\n"
|
|---|
| 442 |
|
|---|
| 443 | .end _exc_handler
|
|---|
| 444 |
|
|---|
| 445 |
|
|---|
