| 1 | /******************************************************************************** |
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| 2 | * File : reset.S |
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| 3 | * Author : Alain Greiner |
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| 4 | * Date : 15/01/2014 |
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| 5 | ********************************************************************************* |
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| 6 | * This is a boot code for a generic multi-clusters / multi-processors |
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| 7 | * TSAR architecture (up to 256 clusters / up to 4 processors per cluster). |
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| 8 | * The physical address is 40 bits, and the 8 MSB bits A[39:32] define the |
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| 9 | * cluster index. |
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| 10 | * |
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| 11 | * As we don't want to use the virtual memory, the physical address is |
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| 12 | * equal to the virtual address (identity mapping) and all processors use |
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| 13 | * the physical memory bank in cluster 0. Both the reset base address and |
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| 14 | * the kernel base address can be redefined to use a physical memory bank |
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| 15 | * smaller than 4 Gbytes. |
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| 16 | * |
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| 17 | * There is one XCU iand one MMC per cluster. |
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| 18 | * All other peripherals (including the boot ROM) are located in cluster 0. |
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| 19 | * Only two HWI interrupts are supported: |
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| 20 | * - IRQ_IN[0] IOC |
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| 21 | * - IRQ_IN[12] MMC |
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| 22 | * |
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| 23 | * The boot sequence is the following: |
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| 24 | * - Each processor initializes the stack pointer ($29) depending on proc_id. |
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| 25 | * - Each processor initializes the CP0 EBASE register |
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| 26 | * - Only processor 0 initializes the Interrupt vector. |
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| 27 | * - Each processor initializes its private XCU mask. |
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| 28 | * - Each processor initializes the Status Register (SR) |
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| 29 | * - Each processor jumps to the same main address in kernel mode... |
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| 30 | ********************************************************************************/ |
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| 31 | |
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| 32 | #include "hard_config.h" |
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| 33 | #include "mips32_registers.h" |
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| 34 | |
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| 35 | .section .reset,"ax",@progbits |
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| 36 | |
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| 37 | .extern seg_stack_base |
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| 38 | .extern seg_xcu_base |
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| 39 | .extern seg_kcode_base |
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| 40 | .extern _interrupt_vector |
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| 41 | .extern _ioc_isr |
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| 42 | .extern _mmc_isr |
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| 43 | .extern main |
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| 44 | |
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| 45 | .globl reset |
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| 46 | .ent reset |
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| 47 | .align 2 |
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| 48 | |
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| 49 | reset: |
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| 50 | .set noreorder |
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| 51 | |
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| 52 | /* each proc computes proc_id, lpid, cluster_xy */ |
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| 53 | mfc0 $26, CP0_PROCID |
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| 54 | andi $26, $26, 0x3FF /* at most 1024 processors */ |
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| 55 | move $10, $26 /* $10 <= proc_id */ |
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| 56 | li $27, NB_PROCS_MAX |
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| 57 | divu $26, $27 |
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| 58 | mfhi $11 /* $11 <= lpid */ |
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| 59 | mflo $12 /* $12 <= cluster_xy */ |
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| 60 | |
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| 61 | /* each proc initializes stack pointer (64K per processor) */ |
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| 62 | la $27, seg_stack_base |
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| 63 | addi $26, $10, 1 /* $26 <= (proc_id + 1) */ |
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| 64 | sll $26, $26, 16 /* $26 <= (proc_id + 1) * 64K */ |
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| 65 | addu $29, $27, $26 /* $29 <= seg_stack_base(proc_id) */ |
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| 66 | |
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| 67 | /* each proc initializes CP0 EBASE register */ |
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| 68 | la $26, seg_kcode_base |
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| 69 | mtc0 $26, CP0_EBASE /* CP0_EBASE <= seg_kcode_base */ |
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| 70 | |
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| 71 | /* only proc (0,0,0) initializes interrupt vector */ |
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| 72 | bne $10, $0, reset_xcu |
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| 73 | nop |
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| 74 | |
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| 75 | la $26, _interrupt_vector /* interrupt vector address */ |
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| 76 | la $27, _ioc_isr |
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| 77 | sw $27, 0($26) /* interrupt_vector[0] <= _isr_ioc */ |
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| 78 | la $27, _mmc_isr |
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| 79 | sw $27, 48($26) /* interrupt_vector[12] <= _isr_mmc */ |
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| 80 | |
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| 81 | reset_xcu: |
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| 82 | |
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| 83 | /* only proc (x,y,0) receive IRQs and initialise its private XCU mask */ |
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| 84 | bne $11, $0, reset_end |
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| 85 | nop |
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| 86 | la $26, seg_xcu_base |
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| 87 | li $27, 0b010010000000 /* offset for MSK_HWI_ENABLE & lpid == 0 */ |
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| 88 | addu $24, $26, $27 /* $24 <= &MASK */ |
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| 89 | li $25, 0x00001001 /* IOC: IRQ[0] / MEMC: IRQ[12] */ |
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| 90 | sw $25, 0($24) /* set MASK */ |
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| 91 | |
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| 92 | reset_end: |
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| 93 | |
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| 94 | /* initializes SR register */ |
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| 95 | li $26, 0x0000FF01 |
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| 96 | mtc0 $26, $12 /* SR <= kernel mode / IRQ enable */ |
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| 97 | |
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| 98 | /* jumps to main in kernel mode */ |
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| 99 | la $26, main |
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| 100 | jr $26 |
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| 101 | nop |
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| 102 | |
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| 103 | .end reset |
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| 104 | |
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| 105 | .set reorder |
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