[536] | 1 | #!/usr/bin/env python |
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| 2 | |
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| 3 | from dsx.hard.hard import * |
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| 4 | |
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| 5 | |
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| 6 | def TSArch(cluster_x, cluster_y, nb_proc = 1, nb_tty = 8, wcoproc = False): |
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| 7 | |
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| 8 | nb_cluster = cluster_x * cluster_y |
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| 9 | |
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| 10 | hd = Hardware(cluster_x, cluster_y , addr_size = 40, nb_proc = nb_proc, ccoherence = True) #nb_proc : proc by cluster |
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| 11 | |
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| 12 | |
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| 13 | ######### peripherals ########## |
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| 14 | hd.add(Tty('PSEG_TTY', pbase = 0xB4000000, channel_size = 16, nb_channel = nb_tty)) |
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| 15 | hd.add(Fbf('PSEG_FBF', pbase = 0xB2000000, channel_size = 352 * 288 * 2, nb_channel = 1)) |
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| 16 | hd.add(Ioc('PSEG_IOC', pbase = 0xB3000000, channel_size = 32, nb_channel = 1)) |
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| 17 | |
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| 18 | hd.add(Xicu('PSEG_XICU', pbase = 0xB0000000, channel_size = 32, nb_channel = nb_proc, replicated = True)) # name suffixed with "_<num_cluster>" |
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| 19 | hd.add(Dma('PSEG_DMA', pbase = 0xB1000000, channel_size = 32, nb_channel = nb_proc, replicated = True)) |
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| 20 | |
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| 21 | ############## MEMORY ########### |
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| 22 | for cl in range(nb_cluster): |
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| 23 | hd.add(RAM('PSEG_RAM_%d'%cl, pbase = 0x00000000 + (cl * hd.cluster_span), size = 0x00C00000)) |
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| 24 | |
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| 25 | ############## IRQ ############ |
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| 26 | hd.add(Irq(cluster_id = 0, proc_id = 0, icu_irq_id = 31, peri = Ioc, channel_id = 0)) |
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| 27 | for j in range(16, 31): |
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| 28 | hd.add(Irq(cluster_id = 0, proc_id = 0, icu_irq_id = j, peri = Tty, channel_id = j - 16)) |
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| 29 | |
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| 30 | for cl in range(nb_cluster): |
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| 31 | for p in xrange(nb_proc): |
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| 32 | hd.add(Irq(cluster_id = cl, proc_id = p, icu_irq_id = p + 8, peri = Dma, channel_id = p)) |
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| 33 | hd.add(Irq(cluster_id = cl, proc_id = p, icu_irq_id = p, peri = Xicu, channel_id = p)) |
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| 34 | |
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| 35 | |
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| 36 | ############# ROM ############ |
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| 37 | hd.add(ROM("PSEG_ROM", pbase = 0xbfc00000, size = 0x00100000)) |
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| 38 | |
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| 39 | return hd |
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| 40 | |
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