source: trunk/softs/test_llsc/top.cpp@ 571

Last change on this file since 571 was 571, checked in by meunier, 13 years ago

Correction of the "double barrier" problem from the user point of view for the generated llsc tests (use of 2 distinct barriers)
File size: 39.1 KB
Line 
1/////////////////////////////////////////////////////////////////////////
2// File: top.cpp
3// Author: Alain Greiner
4// Copyright: UPMC/LIP6
5// Date : may 2013
6// This program is released under the GNU public license
7/////////////////////////////////////////////////////////////////////////
8// This file define a generic TSAR architecture.
9// The physical address space is 40 bits.
10//
11// The number of clusters cannot be larger than 256.
12// The number of processors per cluster cannot be larger than 8.
13//
14// - It uses four dspin_local_crossbar per cluster as local interconnect
15// - It uses two virtual_dspin routers per cluster as global interconnect
16// - It uses the vci_cc_vcache_wrapper
17// - It uses the vci_mem_cache
18// - It contains one vci_xicu per cluster.
19// - It contains one vci_multi_dma per cluster.
20// - It contains one vci_simple_ram per cluster to model the L3 cache.
21//
22// The communication between the MemCache and the Xram is 64 bits.
23//
24// All clusters are identical, but the cluster 0 (called io_cluster),
25// contains 6 extra components:
26// - the boot rom (BROM)
27// - the disk controller (BDEV)
28// - the multi-channel network controller (MNIC)
29// - the multi-channel chained buffer dma controller (CDMA)
30// - the multi-channel tty controller (MTTY)
31// - the frame buffer controller (FBUF)
32//
33// It is build with one single component implementing a cluster,
34// defined in files tsar_xbar_cluster.* (with * = cpp, h, sd)
35//
36// The IRQs are connected to XICUs as follow:
37// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters.
38// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters.
39// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster.
40// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster.
41//
42// Some hardware parameters are used when compiling the OS, and are used
43// by this top.cpp file. They must be defined in the hard_config.h file :
44// - CLUSTER_X : number of clusters in a row (power of 2)
45// - CLUSTER_Y : number of clusters in a column (power of 2)
46// - CLUSTER_SIZE : size of the segment allocated to a cluster
47// - NB_PROCS_MAX : number of processors per cluster (power of 2)
48// - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9)
49// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16)
50// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9)
51//
52// Some other hardware parameters are not used when compiling the OS,
53// and can be directly defined in this top.cpp file:
54// - XRAM_LATENCY : external ram latency
55// - MEMC_WAYS : L2 cache number of ways
56// - MEMC_SETS : L2 cache number of sets
57// - L1_IWAYS
58// - L1_ISETS
59// - L1_DWAYS
60// - L1_DSETS
61// - FBUF_X_SIZE : width of frame buffer (pixels)
62// - FBUF_Y_SIZE : heigth of frame buffer (lines)
63// - BDEV_SECTOR_SIZE : block size for block drvice
64// - BDEV_IMAGE_NAME : file pathname for block device
65// - NIC_RX_NAME : file pathname for NIC received packets
66// - NIC_TX_NAME : file pathname for NIC transmited packets
67// - NIC_TIMEOUT : max number of cycles before closing a container
68/////////////////////////////////////////////////////////////////////////
69// General policy for 40 bits physical address decoding:
70// All physical segments base addresses are multiple of 1 Mbytes
71// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
72// The (x_width + y_width) MSB bits (left aligned) define
73// the cluster index, and the LADR bits define the local index:
74// | X_ID | Y_ID |---| LADR | OFFSET |
75// |x_width|y_width|---| 8 | 24 |
76/////////////////////////////////////////////////////////////////////////
77// General policy for 14 bits SRCID decoding:
78// Each component is identified by (x_id, y_id, l_id) tuple.
79// | X_ID | Y_ID |---| L_ID |
80// |x_width|y_width|---| 6 |
81/////////////////////////////////////////////////////////////////////////
82
83#include <systemc>
84#include <sys/time.h>
85#include <iostream>
86#include <sstream>
87#include <cstdlib>
88#include <cstdarg>
89#include <stdint.h>
90
91#include "gdbserver.h"
92#include "mapping_table.h"
93#include "tsar_xbar_cluster.h"
94#include "alloc_elems.h"
95
96///////////////////////////////////////////////////
97// OS
98///////////////////////////////////////////////////
99
100//#define USE_ALMOS
101#define USE_GIET
102
103#ifdef USE_ALMOS
104#ifdef USE_GIET
105#error "Can't use Two different OS"
106#endif
107#endif
108
109#ifndef USE_ALMOS
110#ifndef USE_GIET
111#error "You need to specify one OS"
112#endif
113#endif
114
115///////////////////////////////////////////////////
116// Parallelisation
117///////////////////////////////////////////////////
118#define USE_OPENMP 0
119
120#if USE_OPENMP
121#include <omp.h>
122#endif
123
124// cluster index (computed from x,y coordinates)
125#define cluster(x,y) (y + YMAX * x)
126
127#define min(x, y) (x < y ? x : y)
128
129///////////////////////////////////////////////////////////
130// DSPIN parameters
131///////////////////////////////////////////////////////////
132
133#define dspin_cmd_width 39
134#define dspin_rsp_width 32
135
136///////////////////////////////////////////////////////////
137// VCI parameters
138///////////////////////////////////////////////////////////
139
140#define vci_cell_width_int 4
141#define vci_cell_width_ext 8
142
143#ifdef USE_ALMOS
144#define vci_address_width 32
145#endif
146#ifdef USE_GIET
147#define vci_address_width 40
148#endif
149#define vci_plen_width 8
150#define vci_rerror_width 1
151#define vci_clen_width 1
152#define vci_rflag_width 1
153#define vci_srcid_width 14
154#define vci_pktid_width 4
155#define vci_trdid_width 4
156#define vci_wrplen_width 1
157
158////////////////////////////////////////////////////////////
159// Main Hardware Parameters values
160//////////////////////i/////////////////////////////////////
161
162#ifdef USE_ALMOS
163#include "almos/hard_config.h"
164#define PREFIX_OS "almos/"
165#endif
166#ifdef USE_GIET
167#include "scripts/soft/hard_config.h"
168#define PREFIX_OS "giet_vm/"
169#endif
170
171////////////////////////////////////////////////////////////
172// Secondary Hardware Parameters
173//////////////////////i/////////////////////////////////////
174
175#define XMAX CLUSTER_X
176#define YMAX CLUSTER_Y
177
178#define XRAM_LATENCY 0
179
180#define MEMC_WAYS 16
181#define MEMC_SETS 256
182
183#define L1_IWAYS 4
184#define L1_ISETS 64
185
186#define L1_DWAYS 4
187#define L1_DSETS 64
188
189#ifdef USE_ALMOS
190#define FBUF_X_SIZE 512
191#define FBUF_Y_SIZE 512
192#endif
193#ifdef USE_GIET
194#define FBUF_X_SIZE 128
195#define FBUF_Y_SIZE 128
196#endif
197
198#ifdef USE_GIET
199#define BDEV_SECTOR_SIZE 512
200#define BDEV_IMAGE_NAME PREFIX_OS"display/images.raw"
201#endif
202#ifdef USE_ALMOS
203#define BDEV_SECTOR_SIZE 4096
204#define BDEV_IMAGE_NAME PREFIX_OS"hdd-img.bin"
205#endif
206
207#define NIC_RX_NAME PREFIX_OS"nic/rx_packets.txt"
208#define NIC_TX_NAME PREFIX_OS"nic/tx_packets.txt"
209#define NIC_TIMEOUT 10000
210
211#define NORTH 0
212#define SOUTH 1
213#define EAST 2
214#define WEST 3
215
216////////////////////////////////////////////////////////////
217// Software to be loaded in ROM & RAM
218//////////////////////i/////////////////////////////////////
219
220#ifdef USE_ALMOS
221#define soft_name PREFIX_OS"bootloader.bin",\
222 PREFIX_OS"kernel-soclib.bin@0xbfc10000:D",\
223 PREFIX_OS"arch-info.bib@0xBFC08000:D"
224#endif
225#ifdef USE_GIET
226#define soft_pathname "scripts/soft/soft.elf"
227#endif
228
229////////////////////////////////////////////////////////////
230// DEBUG Parameters default values
231//////////////////////i/////////////////////////////////////
232
233#define MAX_FROZEN_CYCLES 100000000
234
235/////////////////////////////////////////////////////////
236// Physical segments definition
237/////////////////////////////////////////////////////////
238// There is 3 segments replicated in all clusters
239// and 5 specific segments in the "IO" cluster
240// (containing address 0xBF000000)
241/////////////////////////////////////////////////////////
242
243#ifdef USE_GIET
244 // specific segments in "IO" cluster : absolute physical address
245 #define BROM_BASE 0x00BFC00000
246 #define BROM_SIZE 0x0000100000 // 1 Mbytes
247
248 #define FBUF_BASE 0x00B2000000
249 #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2)
250
251 #define BDEV_BASE 0x00B3000000
252 #define BDEV_SIZE 0x0000001000 // 4 Kbytes
253
254 #define MTTY_BASE 0x00B4000000
255 #define MTTY_SIZE 0x0000001000 // 4 Kbytes
256
257 #define MNIC_BASE 0x00B5000000
258 #define MNIC_SIZE 0x0000080000 // 512 Kbytes (for 8 channels)
259
260 #define CDMA_BASE 0x00B6000000
261 #define CDMA_SIZE 0x0000004000 * NB_CMA_CHANNELS
262
263 // replicated segments : address is incremented by a cluster offset
264 // offset = cluster(x,y) << (address_width-x_width-y_width);
265
266 #define MEMC_BASE 0x0000000000
267 #define MEMC_SIZE 0x0010000000 // 256 Mbytes per cluster
268
269 #define XICU_BASE 0x00B0000000
270 #define XICU_SIZE 0x0000001000 // 4 Kbytes
271
272 #define MDMA_BASE 0x00B1000000
273 #define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel
274
275 #define SIMH_BASE 0x00B7000000
276 #define SIMH_SIZE 0x0000001000
277#endif
278
279#ifdef USE_ALMOS
280 #define CLUSTER_INC (0x80000000ULL / (XMAX * YMAX) * 2)
281
282 #define MEMC_BASE 0x0000000000
283 #define MEMC_SIZE min(0x02000000, (0x80000000 / (XMAX * YMAX)))
284
285 #define BROM_BASE 0x00BFC00000
286 #define BROM_SIZE 0x0000100000 // 1 Mbytes
287
288 #define XICU_BASE (MEMC_SIZE)
289 #define XICU_SIZE 0x0000001000 // 4 Kbytes
290
291 #define MDMA_BASE (XICU_BASE + XICU_SIZE)
292 #define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel
293
294 #define BDEV_BASE ((cluster_io_id * (CLUSTER_INC)) + MDMA_BASE + MDMA_SIZE)
295 #define BDEV_SIZE 0x0000001000 // 4 Kbytes
296
297 #define MTTY_BASE (BDEV_BASE + BDEV_SIZE)
298 #define MTTY_SIZE 0x0000001000 // 4 Kbytes
299
300 #define FBUF_BASE (MTTY_BASE + MTTY_SIZE)
301 #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) // Should be 0x80000
302
303 // Unused in almos
304 #define MNIC_BASE (FBUF_BASE + FBUF_SIZE)
305 #define MNIC_SIZE 0x0000001000
306
307 #define CDMA_BASE (MNIC_BASE + MNIC_SIZE)
308 #define CDMA_SIZE 0x0000004000 * NB_CMA_CHANNELS
309
310#endif
311
312
313////////////////////////////////////////////////////////////////////
314// TGTID definition in direct space
315// For all components: global TGTID = global SRCID = cluster_index
316////////////////////////////////////////////////////////////////////
317
318#define MEMC_TGTID 0
319#define XICU_TGTID 1
320#define MDMA_TGTID 2
321#define MTTY_TGTID 3
322#define FBUF_TGTID 4
323#define BDEV_TGTID 5
324#define MNIC_TGTID 6
325#define BROM_TGTID 7
326#define CDMA_TGTID 8
327#define SIMH_TGTID 9
328
329bool stop_called = false;
330
331/////////////////////////////////
332int _main(int argc, char *argv[])
333{
334 using namespace sc_core;
335 using namespace soclib::caba;
336 using namespace soclib::common;
337
338#ifdef USE_GIET
339 char soft_name[256] = soft_pathname; // pathname to binary code
340#endif
341 uint64_t ncycles = 0xFFFFFFFFFFFFFFFF; // simulated cycles
342 char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image
343 char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file
344 char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file
345 ssize_t threads_nr = 1; // simulator's threads number
346 bool debug_ok = false; // trace activated
347 size_t debug_period = 1; // trace period
348 size_t debug_memc_id = 0; // index of memc to be traced
349 size_t debug_proc_id = 0; // index of proc to be traced
350 uint32_t debug_from = 0; // trace start cycle
351 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor
352 size_t cluster_io_id; // index of cluster containing IOs
353 struct timeval t1,t2;
354 uint64_t ms1,ms2;
355
356 ////////////// command line arguments //////////////////////
357 if (argc > 1)
358 {
359 for (int n = 1; n < argc; n = n + 2)
360 {
361 if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc))
362 {
363 ncycles = atoi(argv[n + 1]);
364 }
365 else if ((strcmp(argv[n], "-SOFT") == 0) && (n + 1 < argc))
366 {
367#ifdef USE_ALMOS
368 assert( 0 && "Can't define almos soft name" );
369#endif
370#ifdef USE_GIET
371 strcpy(soft_name, argv[n + 1]);
372#endif
373 }
374 else if ((strcmp(argv[n],"-DISK") == 0) && (n + 1 < argc))
375 {
376 strcpy(disk_name, argv[n + 1]);
377 }
378 else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc))
379 {
380 debug_ok = true;
381 debug_from = atoi(argv[n + 1]);
382 }
383 else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc))
384 {
385 debug_memc_id = atoi(argv[n + 1]);
386 assert((debug_memc_id < (XMAX * YMAX)) &&
387 "debug_memc_id larger than XMAX * YMAX" );
388 }
389 else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc))
390 {
391 debug_proc_id = atoi(argv[n + 1]);
392 assert((debug_proc_id < (XMAX * YMAX * NB_PROCS_MAX)) &&
393 "debug_proc_id larger than XMAX * YMAX * NB_PROCS");
394 }
395 else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc))
396 {
397 threads_nr = atoi(argv[n + 1]);
398 threads_nr = (threads_nr < 1) ? 1 : threads_nr;
399 }
400 else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc))
401 {
402 frozen_cycles = atoi(argv[n + 1]);
403 }
404 else if ((strcmp(argv[n], "-PERIOD") == 0) && (n + 1 < argc))
405 {
406 debug_period = atoi(argv[n + 1]);
407 }
408 else
409 {
410 std::cout << " Arguments are (key,value) couples." << std::endl;
411 std::cout << " The order is not important." << std::endl;
412 std::cout << " Accepted arguments are :" << std::endl << std::endl;
413 std::cout << " -SOFT pathname_for_embedded_soft" << std::endl;
414 std::cout << " -DISK pathname_for_disk_image" << std::endl;
415 std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
416 std::cout << " -DEBUG debug_start_cycle" << std::endl;
417 std::cout << " -THREADS simulator's threads number" << std::endl;
418 std::cout << " -FROZEN max_number_of_lines" << std::endl;
419 std::cout << " -PERIOD number_of_cycles between trace" << std::endl;
420 std::cout << " -MEMCID index_memc_to_be_traced" << std::endl;
421 std::cout << " -PROCID index_proc_to_be_traced" << std::endl;
422 exit(0);
423 }
424 }
425 }
426
427 // checking hardware parameters
428 assert( ( (XMAX == 1) or (XMAX == 2) or (XMAX == 4) or
429 (XMAX == 8) or (XMAX == 16) ) and
430 "The XMAX parameter must be 1, 2, 4, 8 or 16" );
431
432 assert( ( (YMAX == 1) or (YMAX == 2) or (YMAX == 4) or
433 (YMAX == 8) or (YMAX == 16) ) and
434 "The YMAX parameter must be 1, 2, 4, 8 or 16" );
435
436 assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or
437 (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and
438 "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" );
439
440 assert( (NB_DMA_CHANNELS < 9) and
441 "The NB_DMA_CHANNELS parameter must be smaller than 9" );
442
443 assert( (NB_TTY_CHANNELS < 15) and
444 "The NB_TTY_CHANNELS parameter must be smaller than 15" );
445
446 assert( (NB_NIC_CHANNELS < 9) and
447 "The NB_NIC_CHANNELS parameter must be smaller than 9" );
448
449#ifdef USE_GIET
450 assert( (vci_address_width == 40) and
451 "VCI address width with the GIET must be 40 bits" );
452#endif
453
454#ifdef USE_ALMOS
455 assert( (vci_address_width == 32) and
456 "VCI address width with ALMOS must be 32 bits" );
457#endif
458
459
460 std::cout << std::endl;
461 std::cout << " - XMAX = " << XMAX << std::endl;
462 std::cout << " - YMAX = " << YMAX << std::endl;
463 std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl;
464 std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl;
465 std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl;
466 std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl;
467 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;
468 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;
469 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;
470 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;
471 std::cout << "[PROCS] " << NB_PROCS_MAX * XMAX * YMAX << std::endl;
472
473 std::cout << std::endl;
474 // Internal and External VCI parameters definition
475 typedef soclib::caba::VciParams<vci_cell_width_int,
476 vci_plen_width,
477 vci_address_width,
478 vci_rerror_width,
479 vci_clen_width,
480 vci_rflag_width,
481 vci_srcid_width,
482 vci_pktid_width,
483 vci_trdid_width,
484 vci_wrplen_width> vci_param_int;
485
486 typedef soclib::caba::VciParams<vci_cell_width_ext,
487 vci_plen_width,
488 vci_address_width,
489 vci_rerror_width,
490 vci_clen_width,
491 vci_rflag_width,
492 vci_srcid_width,
493 vci_pktid_width,
494 vci_trdid_width,
495 vci_wrplen_width> vci_param_ext;
496
497#if USE_OPENMP
498 omp_set_dynamic(false);
499 omp_set_num_threads(threads_nr);
500 std::cerr << "Built with openmp version " << _OPENMP << std::endl;
501#endif
502
503 // Define parameters depending on mesh size
504 size_t x_width;
505 size_t y_width;
506
507 if (XMAX == 1) x_width = 0;
508 else if (XMAX == 2) x_width = 1;
509 else if (XMAX <= 4) x_width = 2;
510 else if (XMAX <= 8) x_width = 3;
511 else x_width = 4;
512
513 if (YMAX == 1) y_width = 0;
514 else if (YMAX == 2) y_width = 1;
515 else if (YMAX <= 4) y_width = 2;
516 else if (YMAX <= 8) y_width = 3;
517 else y_width = 4;
518
519
520#ifdef USE_ALMOS
521 cluster_io_id = 0xbfc00000 >> (vci_address_width - x_width - y_width); // index of cluster containing IOs
522#else
523 cluster_io_id = 0;
524#endif
525
526 /////////////////////
527 // Mapping Tables
528 /////////////////////
529
530 // internal network
531 MappingTable maptabd(vci_address_width,
532 IntTab(x_width + y_width, 20 - x_width - y_width),
533 IntTab(x_width + y_width, vci_srcid_width - x_width - y_width),
534 0x00FF800000);
535
536 for (size_t x = 0; x < XMAX; x++)
537 {
538 for (size_t y = 0; y < YMAX; y++)
539 {
540 sc_uint<vci_address_width> offset;
541 offset = (sc_uint<vci_address_width>)cluster(x,y)
542 << (vci_address_width-x_width-y_width);
543
544 std::ostringstream si;
545 si << "seg_xicu_" << x << "_" << y;
546 maptabd.add(Segment(si.str(), XICU_BASE + offset, XICU_SIZE,
547 IntTab(cluster(x,y),XICU_TGTID), false));
548
549 std::ostringstream sd;
550 sd << "seg_mdma_" << x << "_" << y;
551 maptabd.add(Segment(sd.str(), MDMA_BASE + offset, MDMA_SIZE,
552 IntTab(cluster(x,y),MDMA_TGTID), false));
553
554 std::ostringstream sh;
555 sh << "seg_memc_" << x << "_" << y;
556 maptabd.add(Segment(sh.str(), MEMC_BASE + offset, MEMC_SIZE,
557 IntTab(cluster(x,y),MEMC_TGTID), true));
558
559 if ( cluster(x,y) == cluster_io_id )
560 {
561 maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE,
562 IntTab(cluster(x,y),MTTY_TGTID), false));
563 maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE,
564 IntTab(cluster(x,y),FBUF_TGTID), false));
565 maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE,
566 IntTab(cluster(x,y),BDEV_TGTID), false));
567 maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE,
568 IntTab(cluster(x,y),BROM_TGTID), true));
569 maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE,
570 IntTab(cluster(x,y),MNIC_TGTID), false));
571 maptabd.add(Segment("seg_cdma", CDMA_BASE, CDMA_SIZE,
572 IntTab(cluster(x,y),CDMA_TGTID), false));
573 maptabd.add(Segment("seg_simh", SIMH_BASE, SIMH_SIZE,
574 IntTab(cluster(x,y),SIMH_TGTID), false));
575 }
576 }
577 }
578 std::cout << maptabd << std::endl;
579
580 // external network
581 MappingTable maptabx(vci_address_width,
582 IntTab(x_width+y_width),
583 IntTab(x_width+y_width),
584 0xFFFF000000ULL);
585
586 for (size_t x = 0; x < XMAX; x++)
587 {
588 for (size_t y = 0; y < YMAX ; y++)
589 {
590
591 sc_uint<vci_address_width> offset;
592 offset = (sc_uint<vci_address_width>)cluster(x,y)
593 << (vci_address_width-x_width-y_width);
594
595 std::ostringstream sh;
596 sh << "x_seg_memc_" << x << "_" << y;
597
598 maptabx.add(Segment(sh.str(), MEMC_BASE + offset,
599 MEMC_SIZE, IntTab(cluster(x,y)), false));
600 }
601
602 }
603 std::cout << maptabx << std::endl;
604
605 ////////////////////
606 // Signals
607 ///////////////////
608
609 sc_clock signal_clk("clk");
610 sc_signal<bool> signal_resetn("resetn");
611
612 // Horizontal inter-clusters DSPIN signals
613 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_inc =
614 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX, 3);
615 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_dec =
616 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX, 3);
617 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_inc =
618 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", XMAX-1, YMAX, 2);
619 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_dec =
620 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", XMAX-1, YMAX, 2);
621
622 // Vertical inter-clusters DSPIN signals
623 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_inc =
624 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1, 3);
625 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_dec =
626 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1, 3);
627 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_inc =
628 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", XMAX, YMAX-1, 2);
629 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_dec =
630 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", XMAX, YMAX-1, 2);
631
632 // Mesh boundaries DSPIN signals
633 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_in =
634 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in" , XMAX, YMAX, 4, 3);
635 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_out =
636 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", XMAX, YMAX, 4, 3);
637 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_in =
638 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in" , XMAX, YMAX, 4, 2);
639 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_out =
640 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", XMAX, YMAX, 4, 2);
641
642
643 ////////////////////////////
644 // Loader
645 ////////////////////////////
646
647 soclib::common::Loader loader(soft_name);
648
649 typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
650 proc_iss::set_loader(loader);
651
652 ////////////////////////////
653 // Clusters construction
654 ////////////////////////////
655
656 TsarXbarCluster<dspin_cmd_width,
657 dspin_rsp_width,
658 vci_param_int,
659 vci_param_ext>* clusters[XMAX][YMAX];
660
661#if USE_OPENMP
662#pragma omp parallel
663 {
664#pragma omp for
665#endif
666 for (size_t i = 0; i < (XMAX * YMAX); i++)
667 {
668 size_t x = i / YMAX;
669 size_t y = i % YMAX;
670
671#if USE_OPENMP
672#pragma omp critical
673 {
674#endif
675 std::cout << std::endl;
676 std::cout << "Cluster_" << x << "_" << y << std::endl;
677 std::cout << std::endl;
678
679 std::ostringstream sc;
680 sc << "cluster_" << x << "_" << y;
681 clusters[x][y] = new TsarXbarCluster<dspin_cmd_width,
682 dspin_rsp_width,
683 vci_param_int,
684 vci_param_ext>
685 (
686 sc.str().c_str(),
687 NB_PROCS_MAX,
688 NB_TTY_CHANNELS,
689 NB_DMA_CHANNELS,
690 x,
691 y,
692 cluster(x,y),
693 maptabd,
694 maptabx,
695 x_width,
696 y_width,
697 vci_srcid_width - x_width - y_width, // l_id width,
698 MEMC_TGTID,
699 XICU_TGTID,
700 MDMA_TGTID,
701 FBUF_TGTID,
702 MTTY_TGTID,
703 BROM_TGTID,
704 MNIC_TGTID,
705 CDMA_TGTID,
706 BDEV_TGTID,
707 SIMH_TGTID,
708 MEMC_WAYS,
709 MEMC_SETS,
710 L1_IWAYS,
711 L1_ISETS,
712 L1_DWAYS,
713 L1_DSETS,
714 XRAM_LATENCY,
715 (cluster(x,y) == cluster_io_id),
716 FBUF_X_SIZE,
717 FBUF_Y_SIZE,
718 disk_name,
719 BDEV_SECTOR_SIZE,
720 NB_NIC_CHANNELS,
721 nic_rx_name,
722 nic_tx_name,
723 NIC_TIMEOUT,
724 NB_CMA_CHANNELS,
725 loader,
726 frozen_cycles,
727 debug_from,
728 debug_ok and (cluster(x,y) == debug_memc_id),
729 debug_ok and (cluster(x,y) == debug_proc_id)
730 );
731
732#if USE_OPENMP
733 } // end critical
734#endif
735 } // end for
736#if USE_OPENMP
737 }
738#endif
739
740 ///////////////////////////////////////////////////////////////
741 // Net-list
742 ///////////////////////////////////////////////////////////////
743
744 // Clock & RESET
745 for (size_t x = 0; x < (XMAX); x++){
746 for (size_t y = 0; y < YMAX; y++){
747 clusters[x][y]->p_clk (signal_clk);
748 clusters[x][y]->p_resetn (signal_resetn);
749 }
750 }
751
752 // Inter Clusters horizontal connections
753 if (XMAX > 1){
754 for (size_t x = 0; x < (XMAX-1); x++){
755 for (size_t y = 0; y < YMAX; y++){
756 for (size_t k = 0; k < 3; k++){
757 clusters[x][y]->p_cmd_out[EAST][k] (signal_dspin_h_cmd_inc[x][y][k]);
758 clusters[x+1][y]->p_cmd_in[WEST][k] (signal_dspin_h_cmd_inc[x][y][k]);
759 clusters[x][y]->p_cmd_in[EAST][k] (signal_dspin_h_cmd_dec[x][y][k]);
760 clusters[x+1][y]->p_cmd_out[WEST][k] (signal_dspin_h_cmd_dec[x][y][k]);
761 }
762
763 for (size_t k = 0; k < 2; k++){
764 clusters[x][y]->p_rsp_out[EAST][k] (signal_dspin_h_rsp_inc[x][y][k]);
765 clusters[x+1][y]->p_rsp_in[WEST][k] (signal_dspin_h_rsp_inc[x][y][k]);
766 clusters[x][y]->p_rsp_in[EAST][k] (signal_dspin_h_rsp_dec[x][y][k]);
767 clusters[x+1][y]->p_rsp_out[WEST][k] (signal_dspin_h_rsp_dec[x][y][k]);
768 }
769 }
770 }
771 }
772 std::cout << std::endl << "Horizontal connections established" << std::endl;
773
774 // Inter Clusters vertical connections
775 if (YMAX > 1) {
776 for (size_t y = 0; y < (YMAX-1); y++){
777 for (size_t x = 0; x < XMAX; x++){
778 for (size_t k = 0; k < 3; k++){
779 clusters[x][y]->p_cmd_out[NORTH][k] (signal_dspin_v_cmd_inc[x][y][k]);
780 clusters[x][y+1]->p_cmd_in[SOUTH][k] (signal_dspin_v_cmd_inc[x][y][k]);
781 clusters[x][y]->p_cmd_in[NORTH][k] (signal_dspin_v_cmd_dec[x][y][k]);
782 clusters[x][y+1]->p_cmd_out[SOUTH][k] (signal_dspin_v_cmd_dec[x][y][k]);
783 }
784
785 for (size_t k = 0; k < 2; k++){
786 clusters[x][y]->p_rsp_out[NORTH][k] (signal_dspin_v_rsp_inc[x][y][k]);
787 clusters[x][y+1]->p_rsp_in[SOUTH][k] (signal_dspin_v_rsp_inc[x][y][k]);
788 clusters[x][y]->p_rsp_in[NORTH][k] (signal_dspin_v_rsp_dec[x][y][k]);
789 clusters[x][y+1]->p_rsp_out[SOUTH][k] (signal_dspin_v_rsp_dec[x][y][k]);
790 }
791 }
792 }
793 }
794 std::cout << "Vertical connections established" << std::endl;
795
796 // East & West boundary cluster connections
797 for (size_t y = 0; y < YMAX; y++)
798 {
799 for (size_t k = 0; k < 3; k++)
800 {
801 clusters[0][y]->p_cmd_in[WEST][k] (signal_dspin_false_cmd_in[0][y][WEST][k]);
802 clusters[0][y]->p_cmd_out[WEST][k] (signal_dspin_false_cmd_out[0][y][WEST][k]);
803 clusters[XMAX-1][y]->p_cmd_in[EAST][k] (signal_dspin_false_cmd_in[XMAX-1][y][EAST][k]);
804 clusters[XMAX-1][y]->p_cmd_out[EAST][k] (signal_dspin_false_cmd_out[XMAX-1][y][EAST][k]);
805 }
806
807 for (size_t k = 0; k < 2; k++)
808 {
809 clusters[0][y]->p_rsp_in[WEST][k] (signal_dspin_false_rsp_in[0][y][WEST][k]);
810 clusters[0][y]->p_rsp_out[WEST][k] (signal_dspin_false_rsp_out[0][y][WEST][k]);
811 clusters[XMAX-1][y]->p_rsp_in[EAST][k] (signal_dspin_false_rsp_in[XMAX-1][y][EAST][k]);
812 clusters[XMAX-1][y]->p_rsp_out[EAST][k] (signal_dspin_false_rsp_out[XMAX-1][y][EAST][k]);
813 }
814 }
815
816 // North & South boundary clusters connections
817 for (size_t x = 0; x < XMAX; x++)
818 {
819 for (size_t k = 0; k < 3; k++)
820 {
821 clusters[x][0]->p_cmd_in[SOUTH][k] (signal_dspin_false_cmd_in[x][0][SOUTH][k]);
822 clusters[x][0]->p_cmd_out[SOUTH][k] (signal_dspin_false_cmd_out[x][0][SOUTH][k]);
823 clusters[x][YMAX-1]->p_cmd_in[NORTH][k] (signal_dspin_false_cmd_in[x][YMAX-1][NORTH][k]);
824 clusters[x][YMAX-1]->p_cmd_out[NORTH][k] (signal_dspin_false_cmd_out[x][YMAX-1][NORTH][k]);
825 }
826
827 for (size_t k = 0; k < 2; k++)
828 {
829 clusters[x][0]->p_rsp_in[SOUTH][k] (signal_dspin_false_rsp_in[x][0][SOUTH][k]);
830 clusters[x][0]->p_rsp_out[SOUTH][k] (signal_dspin_false_rsp_out[x][0][SOUTH][k]);
831 clusters[x][YMAX-1]->p_rsp_in[NORTH][k] (signal_dspin_false_rsp_in[x][YMAX-1][NORTH][k]);
832 clusters[x][YMAX-1]->p_rsp_out[NORTH][k] (signal_dspin_false_rsp_out[x][YMAX-1][NORTH][k]);
833 }
834 }
835 std::cout << "North, South, West, East connections established" << std::endl;
836 std::cout << std::endl;
837
838
839 ////////////////////////////////////////////////////////
840 // Simulation
841 ///////////////////////////////////////////////////////
842
843 sc_start(sc_core::sc_time(0, SC_NS));
844 signal_resetn = false;
845
846 // network boundaries signals
847 for (size_t x = 0; x < XMAX ; x++){
848 for (size_t y = 0; y < YMAX ; y++){
849 for (size_t a = 0; a < 4; a++){
850 for (size_t k = 0; k < 3; k++){
851 signal_dspin_false_cmd_in [x][y][a][k].write = false;
852 signal_dspin_false_cmd_in [x][y][a][k].read = true;
853 signal_dspin_false_cmd_out[x][y][a][k].write = false;
854 signal_dspin_false_cmd_out[x][y][a][k].read = true;
855 }
856
857 for (size_t k = 0; k < 2; k++){
858 signal_dspin_false_rsp_in [x][y][a][k].write = false;
859 signal_dspin_false_rsp_in [x][y][a][k].read = true;
860 signal_dspin_false_rsp_out[x][y][a][k].write = false;
861 signal_dspin_false_rsp_out[x][y][a][k].read = true;
862 }
863 }
864 }
865 }
866
867 sc_start(sc_core::sc_time(1, SC_NS));
868 signal_resetn = true;
869
870 if (gettimeofday(&t1, NULL) != 0)
871 {
872 perror("gettimeofday");
873 return EXIT_FAILURE;
874 }
875
876 for (uint64_t n = 1; n < ncycles && !stop_called; n++)
877 {
878 // Monitor a specific address for L1 & L2 caches
879 //clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL);
880 //clusters[1][0]->memc->copies_monitor(0x800002C000ULL);
881
882 if( (n % 5000000) == 0)
883 {
884
885 if (gettimeofday(&t2, NULL) != 0)
886 {
887 perror("gettimeofday");
888 return EXIT_FAILURE;
889 }
890
891 ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000;
892 ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000;
893 std::cerr << "platform clock frequency " << (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl;
894
895 if (gettimeofday(&t1, NULL) != 0)
896 {
897 perror("gettimeofday");
898 return EXIT_FAILURE;
899 }
900 }
901
902 if (debug_ok and (n > debug_from) and (n % debug_period == 0))
903 {
904 std::cout << "****************** cycle " << std::dec << n ;
905 std::cout << " ************************************************" << std::endl;
906
907 // trace proc[debug_proc_id]
908 size_t l = debug_proc_id % NB_PROCS_MAX ;
909 size_t y = (debug_proc_id / NB_PROCS_MAX) % YMAX ;
910 size_t x = debug_proc_id / (YMAX * NB_PROCS_MAX) ;
911
912 std::ostringstream proc_signame;
913 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
914 std::ostringstream p2m_signame;
915 p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ;
916 std::ostringstream m2p_signame;
917 m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ;
918 std::ostringstream p_cmd_signame;
919 p_cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ;
920 std::ostringstream p_rsp_signame;
921 p_rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ;
922
923 for (int _x = 0, _y = 0; _x != XMAX; (_y == YMAX - 1 ? _x++, _y = 0 : _y++)) {
924 for (int _l = 0; _l < NB_PROCS_MAX; _l++) {
925 clusters[_x][_y]->proc[_l]->print_trace();
926 }
927 }
928 //clusters[x][y]->wi_proc[l]->print_trace();
929 //clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str());
930 //clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str());
931 //clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str());
932 //clusters[x][y]->signal_dspin_cmd_proc_i[l].print_trace(p_cmd_signame.str());
933 //clusters[x][y]->signal_dspin_rsp_proc_i[l].print_trace(p_rsp_signame.str());
934
935 //clusters[x][y]->xbar_rsp_d->print_trace();
936 //clusters[x][y]->xbar_cmd_d->print_trace();
937 //clusters[x][y]->signal_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD");
938 //clusters[x][y]->signal_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD");
939 //clusters[x][y]->signal_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP");
940 //clusters[x][y]->signal_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP");
941
942 // trace memc[debug_memc_id]
943 x = debug_memc_id / YMAX;
944 y = debug_memc_id % YMAX;
945
946 std::ostringstream smemc;
947 smemc << "[SIG]MEMC_" << x << "_" << y;
948 std::ostringstream sxram;
949 sxram << "[SIG]XRAM_" << x << "_" << y;
950 std::ostringstream sm2p;
951 sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ;
952 std::ostringstream sp2m;
953 sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ;
954 std::ostringstream m_cmd_signame;
955 m_cmd_signame << "[SIG]MEMC_" << x << "_" << y << " CMD" ;
956 std::ostringstream m_rsp_signame;
957 m_rsp_signame << "[SIG]MEMC_" << x << "_" << y << " RSP" ;
958
959 clusters[x][y]->memc->print_trace();
960 //clusters[x][y]->wt_memc->print_trace();
961 //clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
962 //clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
963 //clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str());
964 //clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str());
965 //clusters[x][y]->signal_dspin_cmd_memc_t.print_trace(m_cmd_signame.str());
966 //clusters[x][y]->signal_dspin_rsp_memc_t.print_trace(m_rsp_signame.str());
967
968 // trace replicated peripherals
969 //clusters[1][1]->mdma->print_trace();
970 //clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1");
971 //clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1");
972
973
974 // trace external peripherals
975 //size_t io_x = cluster_io_id / YMAX;
976 //size_t io_y = cluster_io_id % YMAX;
977
978 //clusters[io_x][io_y]->brom->print_trace();
979 //clusters[io_x][io_y]->wt_brom->print_trace();
980 //clusters[io_x][io_y]->signal_vci_tgt_brom.print_trace("[SIG]BROM");
981 //clusters[io_x][io_y]->signal_dspin_cmd_brom_t.print_trace("[SIG]BROM CMD");
982 //clusters[io_x][io_y]->signal_dspin_rsp_brom_t.print_trace("[SIG]BROM RSP");
983
984 //clusters[io_x][io_y]->bdev->print_trace();
985 //clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT");
986 //clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI");
987 }
988
989 sc_start(sc_core::sc_time(1, SC_NS));
990 }
991
992
993 // Free memory
994 for (size_t i = 0; i < (XMAX * YMAX); i++)
995 {
996 size_t x = i / YMAX;
997 size_t y = i % YMAX;
998 delete clusters[x][y];
999 }
1000
1001 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_inc, XMAX - 1, YMAX, 3);
1002 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_dec, XMAX - 1, YMAX, 3);
1003 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_inc, XMAX - 1, YMAX, 2);
1004 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_dec, XMAX - 1, YMAX, 2);
1005 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_inc, XMAX, YMAX - 1, 3);
1006 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_dec, XMAX, YMAX - 1, 3);
1007 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_inc, XMAX, YMAX - 1, 2);
1008 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_dec, XMAX, YMAX - 1, 2);
1009 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_false_cmd_in, XMAX, YMAX, 4, 3);
1010 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_false_cmd_out, XMAX, YMAX, 4, 3);
1011 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_false_rsp_in, XMAX, YMAX, 4, 2);
1012 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_false_rsp_out, XMAX, YMAX, 4, 2);
1013
1014 return EXIT_SUCCESS;
1015}
1016
1017
1018void handler(int dummy = 0) {
1019 stop_called = true;
1020 sc_stop();
1021}
1022
1023void voidhandler(int dummy = 0) {}
1024
1025int sc_main (int argc, char *argv[])
1026{
1027 signal(SIGINT, handler);
1028 signal(SIGPIPE, voidhandler);
1029
1030 try {
1031 return _main(argc, argv);
1032 } catch (std::exception &e) {
1033 std::cout << e.what() << std::endl;
1034 } catch (...) {
1035 std::cout << "Unknown exception occured" << std::endl;
1036 throw;
1037 }
1038 return 1;
1039}
1040
1041
1042// Local Variables:
1043// tab-width: 3
1044// c-basic-offset: 3
1045// c-file-offsets:((innamespace . 0)(inline-open . 0))
1046// indent-tabs-mode: nil
1047// End:
1048
1049// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
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