|
Last change
on this file since 950 was
836,
checked in by meunier, 10 years ago
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|
Trunk:
- Cosmetic in mem_cache_directory.h and xram_transaction.h
- Renamed mem_cache param dspin_in_width and dspin_out_width to memc_dspin_in_width
and memc_dspin_out_width (because of a bug in soclib-cc ?). Should have updated these
names in the .sd or .py files of all platforms
- Updated the scripts for tsar_generic_xbar to take into account the ideal write-through +
added a graph in create_graphs.py
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File size:
149 bytes
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| Line | |
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| 1 | SIMUL="../../../platforms/tsar_mono_mmu/simul.x" |
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| 2 | |
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| 3 | #SIMUL=../../../../soclib-svn-june-2009/soclib/soclib/platform/topcells/caba_vgsb_almo_mmu/simul.x |
|---|
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