| [520] | 1 | /* cop2/vcache definitions */ |
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| 2 | #define VC_PTPR $0 /* set Page Table Pointer Register */ |
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| 3 | #define VC_TLB_EN $1 /* set Data & Inst TLBs Mode Register */ |
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| 4 | #define VC_TLB_EN_ITLB 0x8 /* enable instruction TLB */ |
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| 5 | #define VC_TLB_EN_DTLB 0x4 /* enable data TLB */ |
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| 6 | #define VC_TLB_EN_ICACHE 0x2 /* enable instruction cache */ |
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| 7 | #define VC_TLB_EN_DCACHE 0x1 /* enable data cache */ |
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| 8 | #define VC_ICACHE_FLUSH $2 /* Instruction Cache flush */ |
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| 9 | #define VC_DCACHE_FLUSH $3 /* Data Cache flush */ |
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| 10 | #define VC_ITLB_INVAL $4 /* Instruction TLB line invalidate */ |
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| 11 | #define VC_DTLB_INVAL $5 /* Data TLB line invalidate */ |
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| 12 | #define VC_ICACHE_INVAL $6 /* Instruction Cache line invalidate */ |
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| 13 | #define VC_DCACHE_INVAL $7 /* Data Cache line invalidate */ |
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| 14 | #define VC_ICACHE_PREFETCH $8 /* Instruction Cache line prefetch */ |
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| 15 | #define VC_DCACHE_PREFETCH $9 /* Data Cache line prefetch */ |
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| 16 | #define VC_SYNC $10 /* Complete pending writes */ |
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| 17 | #define VC_IERR_TYPE $11 /* Instruction Exception type Register */ |
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| 18 | #define VC_DERR_TYPE $12 /* Data Exception type Register */ |
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| 19 | #define VC_DATA_LO $17 /* misc register low */ |
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| 20 | #define VC_DATA_HI $18 /* misc register hight */ |
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| 21 | #define VC_ICACHE_INVAL_PA $19 /* misc register hight */ |
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| 22 | #define VC_DCACHE_INVAL_PA $20 /* misc register hight */ |
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| 23 | #define VC_ERR_PT1_UNMAPPED 0x001 /* Page fault on Table1 (invalid PTE) */ |
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| 24 | #define VC_ERR_PT2_UNMAPPED 0x002 /* Page fault on Table 2 (invalid PTE) */ |
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| 25 | #define VC_ERR_PRIVILEGE_VIOLATION 0x004 /* Protected access in user mode */ |
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| 26 | #define VC_ERR_WRITE_VIOLATION 0x008 /* Write access to a non write page */ |
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| 27 | #define VC_ERR_EXEC_VIOLATION 0x010 /* Exec access to a non exec page */ |
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| 28 | #define VC_ERR_UNDEFINED_XTN 0x020 /* Undefined external access address */ |
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| 29 | #define VC_ERR_PT1_ILLEGAL_ACCESS 0x040 /* Bus Error in Table1 access */ |
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| 30 | #define VC_ERR_PT2_ILLEGAL_ACCESS 0x080 /* Bus Error in Table2 access */ |
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| 31 | #define VC_ERR_CACHE_ILLEGAL_ACCESS 0x100 /* Bus Error during the cache access */ |
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| 32 | #define VC_I_BAD_VADDR $13 /* Instruction Bad Virtual Address Register */ |
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| 33 | #define VC_D_BAD_VADDR $14 /* Data Bad Virtual Address Register */ |
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| 34 | #define VC_DATA_L $17 /* cache parameters */ |
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| 35 | #define VC_DATA_H $18 /* cache parameters */ |
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| 36 | #define VC_ICACHE_INVAL_PA $19 /* icache inval per physical address */ |
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| 37 | #define VC_DCACHE_INVAL_PA $20 /* dcache inval per physical address */ |
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| 38 | |
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| 39 | /* vcache page level 1 format */ |
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| 40 | #define PTE1_V (1 << 31) /* entry valid */ |
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| 41 | #define PTE1_T (1 << 30) /* 0 == entry is a PTE1 (maps a 2M page) */ |
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| 42 | #define PTE1_L (1 << 29) /* accessed by local CPU */ |
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| 43 | #define PTE1_R (1 << 28) /* accessed by remote CPU */ |
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| 44 | #define PTE1_C (1 << 27) /* cachable */ |
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| 45 | #define PTE1_W (1 << 26) /* writable */ |
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| 46 | #define PTE1_X (1 << 25) /* executable */ |
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| 47 | #define PTE1_U (1 << 24) /* user-accessible */ |
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| 48 | #define PTE1_G (1 << 23) /* global */ |
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| 49 | #define PTE1_D (1 << 22) /* dirty */ |
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| 50 | |
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| 51 | /* vcache page level 2 format: same as level 1, PTE1_T */ |
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| 52 | #define PTE2_V (1 << 31) /* entry valid */ |
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| 53 | /* reserved, 0 */ |
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| 54 | #define PTE2_L (1 << 29) /* accessed by local CPU */ |
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| 55 | #define PTE2_R (1 << 28) /* accessed by remote CPU */ |
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| 56 | #define PTE2_C (1 << 27) /* cachable */ |
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| 57 | #define PTE2_W (1 << 26) /* writable */ |
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| 58 | #define PTE2_X (1 << 25) /* executable */ |
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| 59 | #define PTE2_U (1 << 24) /* user-accessible */ |
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| 60 | #define PTE2_G (1 << 23) /* global */ |
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| 61 | #define PTE2_D (1 << 22) /* dirty */ |
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| 62 | #define PTE2_os 0xff /* OS-reserved bits */ |
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| 63 | |
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| 64 | #define PTE2_SHIFT 12 |
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| 65 | #define PTE2_MASK 0x0001ff000 |
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| 66 | #define VADDR_TO_PTE2I(va) (((va) & PTE2_MASK) >> PTE2_SHIFT) |
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