| 1 | #define XICU_BASE 0xd8200000 |
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| 2 | #define __XICU_FUNC_SHIFT 7 |
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| 3 | #define __XICU_IDX_SHIFT 2 |
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| 4 | #define __XICU_RIDX(func, idx) \ |
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| 5 | ((((func) & 0x1f) << __XICU_FUNC_SHIFT) + \ |
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| 6 | (((idx) & 0x1f) << __XICU_IDX_SHIFT)) |
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| 7 | |
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| 8 | /* triggers the wtiidx interrupt. R/W */ |
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| 9 | #define XICU_WTI_REG_FUNC 0x00 |
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| 10 | #define XICU_WTI_REG(wtiidx) __XICU_RIDX(XICU_WTI_REG_FUNC, wtiidx) |
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| 11 | |
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| 12 | /* Timer period R/W */ |
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| 13 | #define XICU_PTI_PER_FUNC 0x01 |
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| 14 | #define XICU_PTI_PER(ptiidx) __XICU_RIDX(XICU_PTI_PER_FUNC, ptiidx) |
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| 15 | |
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| 16 | /* timer value R/W */ |
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| 17 | #define XICU_PTI_VAL_FUNC 0x02 |
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| 18 | #define XICU_PTI_VAL(ptiidx) __XICU_RIDX(XICU_PTI_VAL_FUNC, ptiidx) |
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| 19 | |
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| 20 | /* Timer interrupt acknowledge. R */ |
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| 21 | #define XICU_PTI_ACK_FUNC 0x03 |
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| 22 | #define XICU_PTI_ACK(ptiidx) __XICU_RIDX(XICU_PTI_ACK_FUNC, ptiidx) |
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| 23 | |
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| 24 | /* |
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| 25 | * remaining registers define the way interrupt sources are mutiplexed to |
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| 26 | * the output lines. Indexed by output line number. |
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| 27 | */ |
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| 28 | /* |
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| 29 | * Multiplex timers to output lines: |
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| 30 | * XICU_MSK_PTI mask register for outidx line (bit to 1 enable interrupt) |
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| 31 | * XICU_MSK_PTI_E atomically add a set of bits to XICU_MSK_PTI |
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| 32 | * XICU_MSK_PTI_D atomically clear a set of bits from XICU_MSK_PTI |
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| 33 | * XICU_PTI_ACT get active PTI lines for this output line |
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| 34 | */ |
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| 35 | #define XICU_MSK_PTI_FUNC 0x04 /* R/W */ |
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| 36 | #define XICU_MSK_PTI(outidx) __XICU_RIDX(XICU_MSK_PTI_FUNC, outidx) |
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| 37 | |
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| 38 | #define XICU_MSK_PTI_E_FUNC 0x05 /* W */ |
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| 39 | #define XICU_MSK_PTI_E(outidx) __XICU_RIDX(XICU_MSK_PTI_E_FUNC, outidx) |
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| 40 | |
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| 41 | #define XICU_MSK_PTI_D_FUNC 0x06 /* W */ |
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| 42 | #define XICU_MSK_PTI_D(outidx) __XICU_RIDX(XICU_MSK_PTI_D_FUNC, outidx) |
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| 43 | |
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| 44 | #define XICU_PTI_ACT_FUNC 0x06 /* R */ |
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| 45 | #define XICU_PTI_ACT(outidx) __XICU_RIDX(XICU_PTI_ACT_FUNC, outidx) |
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| 46 | |
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| 47 | /* |
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| 48 | * Multiplex hardware input lines to output lines: |
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| 49 | * XICU_MSK_HWI mask register for outidx line (bit to 1 enable interrupt) |
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| 50 | * XICU_MSK_HWI_E atomically add a set of bits to XICU_MSK_HWI |
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| 51 | * XICU_MSK_HWI_D atomically clear a set of bits from XICU_MSK_HWI |
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| 52 | * XICU_HWI_ACT get active HWI lines for this output line |
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| 53 | */ |
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| 54 | #define XICU_MSK_HWI_FUNC 0x08 /* R/W */ |
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| 55 | #define XICU_MSK_HWI(outidx) __XICU_RIDX(XICU_MSK_HWI_FUNC, outidx) |
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| 56 | |
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| 57 | #define XICU_MSK_HWI_E_FUNC 0x09 /* W */ |
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| 58 | #define XICU_MSK_HWI_E(outidx) __XICU_RIDX(XICU_MSK_HWI_E_FUNC, outidx) |
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| 59 | |
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| 60 | #define XICU_MSK_HWI_D_FUNC 0x0a /* W */ |
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| 61 | #define XICU_MSK_HWI_D(outidx) __XICU_RIDX(XICU_MSK_HWI_D_FUNC, outidx) |
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| 62 | |
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| 63 | #define XICU_HWI_ACT_FUNC 0x0a /* R */ |
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| 64 | #define XICU_HWI_ACT(outidx) __XICU_RIDX(XICU_HWI_ACT_FUNC, outidx) |
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| 65 | |
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| 66 | /* |
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| 67 | * Multiplex hardware input lines to output lines: |
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| 68 | * XICU_MSK_WTI mask register for outidx line (bit to 1 enable interrupt) |
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| 69 | * XICU_MSK_WTI_E atomically add a set of bits to XICU_MSK_WTI |
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| 70 | * XICU_MSK_WTI_D atomically clear a set of bits from XICU_MSK_WTI |
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| 71 | * XICU_WTI_ACT get active WTI lines for this output line |
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| 72 | */ |
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| 73 | #define XICU_MSK_WTI_FUNC 0x0c /* R/W */ |
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| 74 | #define XICU_MSK_WTI(outidx) __XICU_RIDX(XICU_MSK_WTI_FUNC, outidx) |
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| 75 | |
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| 76 | #define XICU_MSK_WTI_E_FUNC 0x0d /* W */ |
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| 77 | #define XICU_MSK_WTI_E(outidx) __XICU_RIDX(XICU_MSK_WTI_E_FUNC, outidx) |
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| 78 | |
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| 79 | #define XICU_MSK_WTI_D_FUNC 0x0e /* W */ |
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| 80 | #define XICU_MSK_WTI_D(outidx) __XICU_RIDX(XICU_MSK_WTI_D_FUNC, outidx) |
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| 81 | |
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| 82 | #define XICU_WTI_ACT_FUNC 0x0e /* R */ |
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| 83 | #define XICU_WTI_ACT(outidx) __XICU_RIDX(XICU_WTI_ACT_FUNC, outidx) |
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| 84 | |
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| 85 | /* source priority encoder for outpout lines */ |
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| 86 | #define XICU_PRIO_FUNC 0x0f |
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| 87 | #define XICU_PRIO(outidx) __XICU_RIDX(XICU_PRIO_FUNC, outidx) |
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| 88 | |
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| 89 | #define XICU_PRIO_PTI 0x00000001 /* Timer interrrupt pending */ |
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| 90 | #define XICU_PRIO_PTII(val) ((val) >> 8 & 0x1f) /* first PTI pending */ |
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| 91 | #define XICU_PRIO_HWI 0x00000002 /* Hardware interrrupt pending */ |
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| 92 | #define XICU_PRIO_HWII(val) ((val) >> 16 & 0x1f) /* first HWI pending */ |
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| 93 | #define XICU_PRIO_WTI 0x00000004 /* write-triggered interrrupt pending */ |
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| 94 | #define XICU_PRIO_WTII(val) ((val) >> 24 & 0x1f) /* first WTI pending */ |
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| 95 | |
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| 96 | #define XICU_PRIO_PENDING (XICU_PRIO_PTI|XICU_PRIO_HWI|XICU_PRIO_WTI) |
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