1 | /* |
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2 | * cache inval test: check that VC_DCACHE_INVAL_PA does the job |
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3 | * on a cc_vcache, the cache invalidation/update should be done by hardware |
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4 | * and VC_DCACHE_INVAL_PA should not be needed. |
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5 | */ |
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6 | #include <registers.h> |
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7 | #include <misc.h> |
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8 | #include <vcache.h> |
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9 | .text |
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10 | .globl _start |
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11 | _start: |
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12 | .set noreorder |
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13 | la k0, TTY_BASE |
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14 | la k1, EXIT_BASE |
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15 | |
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16 | PRINT(startstr) |
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17 | |
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18 | /* reset cop0 status (keep BEV) */ |
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19 | lui a0, 0x0040; |
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20 | mtc0 a0, COP0_STATUS |
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21 | |
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22 | la a0, pte1_a |
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23 | srl a0, a0, 13 |
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24 | mtc2 a0, VC_PTPR |
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25 | nop |
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26 | |
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27 | li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE |
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28 | mtc2 a0, VC_TLB_EN |
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29 | |
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30 | PRINT(mmustr_a) |
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31 | la t0, testval |
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32 | lw a0, 0(t0); |
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33 | PRINTX |
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34 | PUTCHAR('\n') |
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35 | la a1, DMA_BASE |
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36 | la a0, testval2 |
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37 | sw a0, DMA_SRC(a1) |
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38 | la a0, testval |
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39 | sw a0, DMA_DST(a1) |
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40 | li a0, 4 |
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41 | sw a0, DMA_LEN(a1) /* start DMA */ |
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42 | loop: |
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43 | lw a0, DMA_LEN(a1) |
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44 | bne a0, zero, loop; |
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45 | nop |
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46 | |
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47 | PRINT(mmustr_b) |
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48 | la t0, testval |
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49 | lw a0, 0(t0); |
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50 | PRINTX |
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51 | PUTCHAR('\n') |
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52 | |
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53 | la a0, testval |
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54 | mtc2 a0, VC_DATA_LO |
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55 | mtc2 zero, VC_DATA_HI |
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56 | mtc2 zero, VC_DCACHE_INVAL_PA |
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57 | nop |
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58 | |
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59 | PRINT(mmustr_c) |
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60 | la t0, testval |
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61 | lw a0, 0(t0); |
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62 | PRINTX |
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63 | PUTCHAR('\n') |
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64 | |
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65 | /* we should get there */ |
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66 | EXIT(0) |
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67 | |
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68 | .globl excep |
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69 | excep: |
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70 | .set noreorder |
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71 | PRINT(statusstr) |
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72 | mfc0 a0, COP0_STATUS |
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73 | PRINTX |
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74 | |
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75 | PRINT(causestr) |
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76 | mfc0 a0, COP0_CAUSE |
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77 | PRINTX |
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78 | |
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79 | PRINT(pcstr) |
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80 | mfc0 a0, COP0_EXPC |
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81 | PRINTX |
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82 | |
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83 | PRINT(badvastr) |
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84 | mfc0 a0, COP_0_BADVADDR |
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85 | PRINTX |
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86 | |
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87 | PUTCHAR('\n') |
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88 | /* we should not get there */ |
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89 | EXIT(3) |
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90 | |
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91 | .rodata: |
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92 | statusstr: .ascii "status \0" |
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93 | causestr: .ascii " cause \0" |
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94 | pcstr: .ascii " pc \0" |
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95 | badvastr: .ascii " badva \0" |
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96 | mmustr_a: .ascii "mmu started before DMA \0" |
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97 | mmustr_b: .ascii "mmu started after DMA \0" |
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98 | mmustr_c: .ascii "mmu started after FLUSH \0" |
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99 | startstr: .ascii "start\n\0" |
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100 | |
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101 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
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102 | .globl evect |
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103 | evect: |
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104 | j excep |
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105 | nop |
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106 | |
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107 | .data |
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108 | data_a: |
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109 | .word MAGIC1 |
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110 | testval: |
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111 | .word MAGIC2 |
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112 | data_b: |
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113 | .word MAGIC3 |
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114 | testval2: |
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115 | .word MAGIC4 |
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116 | .globl pte2_a |
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117 | |
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118 | pte2_a: |
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119 | .align 12 |
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120 | .word PTE2_V | PTE2_C | PTE2_X |
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121 | .word 0x0000 >> 12 /* check real value of data_a */ |
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122 | .org pte2_a + 4092 |
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123 | .word 0 |
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124 | .globl pte1_a |
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125 | pte1_a: |
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126 | .align 13 |
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127 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
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128 | .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ |
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129 | .org pte1_a + (BOOT_ADDRESS >> 21) * 4 |
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130 | .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ |
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131 | .org pte1_a + (TTY_BASE >> 21) * 4 |
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132 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
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133 | .org pte1_a + (EXIT_BASE >> 21) * 4 |
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134 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
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135 | .org pte1_a + (DMA_BASE >> 21) * 4 |
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136 | .word PTE1_V | PTE1_W | (DMA_BASE >> 21) /* map PA 0xe8000000 at VA 0xe0000000 */ |
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