[520] | 1 | /* |
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| 2 | * dtlb inval: a write to VC_DTLB_INVAL should invalidate the corresponding |
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| 3 | * dtlb entry. On a ccvcache, VC_DTLB_INVAL should not be needed, and |
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| 4 | * the first access after clearing pte2_a should fail |
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| 5 | */ |
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| 6 | #include <registers.h> |
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| 7 | #include <misc.h> |
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| 8 | #include <vcache.h> |
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| 9 | .text |
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| 10 | .globl _start |
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| 11 | _start: |
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| 12 | .set noreorder |
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| 13 | la k0, TTY_BASE |
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| 14 | la k1, EXIT_BASE |
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| 15 | |
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| 16 | PRINT(startstr) |
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| 17 | |
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| 18 | /* reset cop0 status (keep BEV) */ |
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| 19 | lui a0, 0x0040; |
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| 20 | mtc0 a0, COP0_STATUS |
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| 21 | |
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| 22 | la a0, pte1_a |
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| 23 | srl a0, a0, 13 |
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| 24 | mtc2 a0, VC_PTPR |
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| 25 | nop |
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| 26 | |
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| 27 | li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE |
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| 28 | mtc2 a0, VC_TLB_EN |
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| 29 | |
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| 30 | PRINT(mmustr) |
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| 31 | la t0, testval + 0x00200000 |
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| 32 | lw a0, 0(t0); |
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| 33 | PRINTX |
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| 34 | PUTCHAR(' ') |
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| 35 | la a0, pte2_a |
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| 36 | sw zero, 0(a0) /* invalidate PTE2 entry */ |
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| 37 | sync |
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| 38 | la t0, testval + 0x00200000 |
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| 39 | lw a0, 0(t0); /* TLB entry not invalidated yet, we can do this */ |
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| 40 | PRINTX |
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| 41 | PUTCHAR('\n') |
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| 42 | la t0, testval + 0x00200000 |
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| 43 | mtc2 t0, VC_DTLB_INVAL /* invalidate VA */ |
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| 44 | lw a0, 0(t0); /* now this should fail */ |
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| 45 | PRINTX |
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| 46 | PUTCHAR('\n') |
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| 47 | |
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| 48 | /* we should not get there */ |
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| 49 | EXIT(1) |
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| 50 | |
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| 51 | .globl excep |
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| 52 | excep: |
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| 53 | .set noreorder |
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| 54 | PRINT(statusstr) |
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| 55 | mfc0 a0, COP0_STATUS |
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| 56 | PRINTX |
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| 57 | |
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| 58 | PRINT(causestr) |
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| 59 | mfc0 a0, COP0_CAUSE |
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| 60 | PRINTX |
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| 61 | |
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| 62 | PRINT(pcstr) |
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| 63 | mfc0 a0, COP0_EXPC |
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| 64 | PRINTX |
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| 65 | |
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| 66 | PRINT(badvastr) |
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| 67 | mfc0 a0, COP_0_BADVADDR |
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| 68 | PRINTX |
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| 69 | |
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| 70 | PUTCHAR('\n') |
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| 71 | /* we should get there */ |
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| 72 | EXIT(0) |
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| 73 | |
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| 74 | .rodata: |
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| 75 | statusstr: .ascii "status \0" |
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| 76 | causestr: .ascii " cause \0" |
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| 77 | pcstr: .ascii " pc \0" |
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| 78 | badvastr: .ascii " badva \0" |
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| 79 | mmustr: .ascii "mmu started \0" |
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| 80 | startstr: .ascii "start\n\0" |
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| 81 | |
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| 82 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
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| 83 | .globl evect |
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| 84 | evect: |
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| 85 | j excep |
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| 86 | nop |
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| 87 | |
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| 88 | .data |
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| 89 | /* first 2 pages is data that will be switched my mmu switch */ |
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| 90 | data_a: |
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| 91 | .word MAGIC1 |
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| 92 | testval: |
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| 93 | .word MAGIC2 |
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| 94 | .globl pte2_a |
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| 95 | /* |
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| 96 | * one PD with a level 2 PTP: we invalidate an entry in the PTP and |
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| 97 | * check that the VA is no longer accessible |
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| 98 | */ |
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| 99 | pte2_a: |
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| 100 | .align 12 |
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| 101 | .word PTE2_V | PTE2_C | PTE2_X |
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| 102 | .word 0x0000 >> 12 /* check real value of data_a */ |
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| 103 | .org pte2_a + 4092 |
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| 104 | .word 0 |
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| 105 | .globl pte2_b |
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| 106 | .globl pte1_a |
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| 107 | pte1_a: |
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| 108 | .align 13 |
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| 109 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
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| 110 | .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ |
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| 111 | .org pte1_a + (BOOT_ADDRESS >> 21) * 4 |
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| 112 | .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ |
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| 113 | .org pte1_a + (TTY_BASE >> 21) * 4 |
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| 114 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
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| 115 | .org pte1_a + (EXIT_BASE >> 21) * 4 |
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| 116 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
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| 117 | .org pte1_a + 8192 |
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