| 1 | /* |
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| 2 | * dtlb inval: a write to a PTE2 should invalidate the corresponding |
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| 3 | * dtlb entry. |
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| 4 | */ |
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| 5 | #include <registers.h> |
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| 6 | #include <misc.h> |
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| 7 | #include <vcache.h> |
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| 8 | .text |
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| 9 | .globl _start |
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| 10 | _start: |
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| 11 | .set noreorder |
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| 12 | la k0, TTY_BASE |
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| 13 | la k1, EXIT_BASE |
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| 14 | |
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| 15 | PRINT(startstr) |
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| 16 | |
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| 17 | /* reset cop0 status (keep BEV) */ |
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| 18 | lui a0, 0x0040; |
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| 19 | mtc0 a0, COP0_STATUS |
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| 20 | |
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| 21 | la a0, pte1_a |
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| 22 | srl a0, a0, 13 |
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| 23 | mtc2 a0, VC_PTPR |
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| 24 | nop |
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| 25 | |
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| 26 | li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE |
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| 27 | mtc2 a0, VC_TLB_EN |
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| 28 | |
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| 29 | PRINT(mmustr) |
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| 30 | la t0, testval + 0x00200000 |
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| 31 | lw a0, 0(t0); |
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| 32 | PRINTX |
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| 33 | PUTCHAR(' ') |
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| 34 | la t0, pte2_a |
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| 35 | la a0, 0x1000 >> 12 |
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| 36 | sw a0, 4(t0) /* swap PTE2 entry */ |
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| 37 | 1: |
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| 38 | ll a0, 0(t0) |
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| 39 | la a0, PTE2_V | PTE2_C | PTE2_X |
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| 40 | sc a0, 0(t0) |
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| 41 | beqz a0, 1b |
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| 42 | nop |
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| 43 | |
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| 44 | la t0, testval + 0x00200000 |
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| 45 | lw a0, 0(t0); /* should get MAGIC1 */ |
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| 46 | PRINTX |
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| 47 | PUTCHAR('\n') |
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| 48 | |
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| 49 | /* we should get there */ |
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| 50 | EXIT(0) |
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| 51 | |
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| 52 | .globl excep |
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| 53 | excep: |
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| 54 | .set noreorder |
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| 55 | PRINT(statusstr) |
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| 56 | mfc0 a0, COP0_STATUS |
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| 57 | PRINTX |
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| 58 | |
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| 59 | PRINT(causestr) |
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| 60 | mfc0 a0, COP0_CAUSE |
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| 61 | PRINTX |
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| 62 | |
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| 63 | PRINT(pcstr) |
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| 64 | mfc0 a0, COP0_EXPC |
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| 65 | PRINTX |
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| 66 | |
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| 67 | PRINT(badvastr) |
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| 68 | mfc0 a0, COP_0_BADVADDR |
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| 69 | PRINTX |
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| 70 | |
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| 71 | PUTCHAR('\n') |
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| 72 | /* we should not get there */ |
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| 73 | EXIT(1) |
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| 74 | |
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| 75 | .rodata: |
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| 76 | statusstr: .ascii "status \0" |
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| 77 | causestr: .ascii " cause \0" |
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| 78 | pcstr: .ascii " pc \0" |
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| 79 | badvastr: .ascii " badva \0" |
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| 80 | mmustr: .ascii "mmu started \0" |
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| 81 | startstr: .ascii "start\n\0" |
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| 82 | |
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| 83 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
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| 84 | .globl evect |
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| 85 | evect: |
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| 86 | j excep |
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| 87 | nop |
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| 88 | |
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| 89 | .data |
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| 90 | /* first 2 pages is data that will be switched my mmu switch */ |
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| 91 | data_a: |
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| 92 | .word MAGIC1 |
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| 93 | testval: |
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| 94 | .word MAGIC2 |
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| 95 | .align 12 |
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| 96 | .word MAGIC2 |
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| 97 | .word MAGIC1 |
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| 98 | .globl pte2_a |
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| 99 | /* |
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| 100 | * one PD with a level 2 PTP: we switch an entry in the PTP and |
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| 101 | * check that the dtlb is invalidated |
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| 102 | */ |
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| 103 | pte2_a: |
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| 104 | .align 12 |
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| 105 | .word PTE2_V | PTE2_C | PTE2_X |
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| 106 | .word 0x0000 >> 12 /* check real value of data_a */ |
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| 107 | .org pte2_a + 4092 |
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| 108 | .word 0 |
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| 109 | .globl pte2_b |
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| 110 | .globl pte1_a |
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| 111 | pte1_a: |
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| 112 | .align 13 |
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| 113 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
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| 114 | .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ |
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| 115 | .org pte1_a + (BOOT_ADDRESS >> 21) * 4 |
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| 116 | .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ |
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| 117 | .org pte1_a + (TTY_BASE >> 21) * 4 |
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| 118 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
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| 119 | .org pte1_a + (EXIT_BASE >> 21) * 4 |
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| 120 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
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| 121 | .org pte1_a + 8192 |
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