[520] | 1 | /* |
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| 2 | * Check interrupt while in trap handler. |
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| 3 | * Cache is enabled so we have one instruction/cycle |
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| 4 | */ |
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| 5 | #include <registers.h> |
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| 6 | #include <misc.h> |
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| 7 | #include <vcache.h> |
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| 8 | #include <xicu.h> |
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| 9 | |
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| 10 | #define DOLOAD_ADDR 0x80000000 |
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| 11 | |
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| 12 | .text |
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| 13 | .globl _start |
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| 14 | _start: |
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| 15 | .set noreorder |
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| 16 | la k0, TTY_BASE |
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| 17 | la k1, EXIT_BASE |
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| 18 | la sp, 0x00200000 - 16 |
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| 19 | |
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| 20 | /* reset cause, make sure IV is off */ |
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| 21 | mtc0 zero, COP0_CAUSE |
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| 22 | |
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| 23 | la a0, pte1 |
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| 24 | srl a0, a0, 13 |
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| 25 | mtc2 a0, VC_PTPR |
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| 26 | nop |
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| 27 | nop |
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| 28 | |
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| 29 | li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE |
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| 30 | mtc2 a0, VC_TLB_EN |
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| 31 | |
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| 32 | PRINT(startstr) |
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| 33 | |
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| 34 | /* program xicu */ |
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| 35 | la t0, XICU_BASE |
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| 36 | /* clear pending interrupt */ |
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| 37 | lw a0, XICU_PTI_ACK(0)(t0) |
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| 38 | /* route PTI0 to irq 0 */ |
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| 39 | li a0, 1 << 0 |
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| 40 | sw a0, XICU_MSK_PTI_E(0)(t0) |
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| 41 | /* init s0 */ |
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| 42 | li s0, MAGIC2 |
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| 43 | /* |
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| 44 | * interrupt in INTERRUPT_DELAY cycles. |
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| 45 | */ |
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| 46 | li a0, INTERRUPT_DELAY |
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| 47 | sw a0, XICU_PTI_PER(0)(t0) |
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| 48 | /* clear pending interrupt */ |
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| 49 | lw a0, XICU_PTI_ACK(0)(t0) |
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| 50 | /* reset cop0 status (keep BEV), enable interrupt 0 */ |
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| 51 | lui a0, 0x0040; |
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| 52 | addiu a0, 0x0401; |
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| 53 | mtc0 a0, COP0_STATUS |
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| 54 | nop |
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| 55 | nop |
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| 56 | nop |
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| 57 | nop |
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| 58 | nop |
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| 59 | |
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| 60 | nop |
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| 61 | move a1, zero |
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| 62 | la s0, DOLOAD_ADDR |
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| 63 | jalr s0 |
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| 64 | nop |
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| 65 | j end |
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| 66 | nop |
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| 67 | /* we should not end there */ |
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| 68 | EXIT(1) |
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| 69 | |
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| 70 | end: |
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| 71 | PRINT(endstr) |
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| 72 | move a0, a1 |
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| 73 | PRINTX |
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| 74 | PUTCHAR(' ') |
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| 75 | la a0, myvar |
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| 76 | lw a0, 0(a0) |
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| 77 | PRINTX |
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| 78 | PUTCHAR('\n') |
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| 79 | EXIT(0) |
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| 80 | |
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| 81 | .globl excep |
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| 82 | excep: |
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| 83 | .set noreorder |
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| 84 | /* don't clobber a0 and ra */ |
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| 85 | addiu sp, sp, -8 |
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| 86 | sw a0, 4(sp) |
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| 87 | sw ra, 8(sp) |
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| 88 | |
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| 89 | PRINT(statusstr) |
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| 90 | mfc0 a0, COP0_STATUS |
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| 91 | PRINTX |
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| 92 | |
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| 93 | PRINT(causestr) |
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| 94 | mfc0 a0, COP0_CAUSE |
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| 95 | move s0, a0 |
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| 96 | PRINTX |
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| 97 | |
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| 98 | PRINT(pcstr) |
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| 99 | mfc0 a0, COP0_EXPC |
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| 100 | PRINTX |
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| 101 | |
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| 102 | PRINT(badvastr) |
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| 103 | mfc0 a0, COP_0_BADVADDR |
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| 104 | PRINTX |
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| 105 | |
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| 106 | PRINT(xicustr) |
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| 107 | la t0, XICU_BASE |
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| 108 | lw a0, XICU_PRIO(0)(t0) |
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| 109 | PRINTX |
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| 110 | PUTCHAR('\n') |
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| 111 | /* map VA DOLOAD_ADDR at PA 0xbfc01000 */ |
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| 112 | la t0, pte22 + VADDR_TO_PTE2I(DOLOAD_ADDR) * 8 |
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| 113 | la a0, (0xbfc01000 >> PTE2_SHIFT) |
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| 114 | sw a0, 4(t0) |
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| 115 | la a0, (PTE2_V | PTE2_C | PTE2_X) |
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| 116 | sw a0, 0(t0) |
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| 117 | mtc2 zero, VC_DCACHE_FLUSH /* flush the whole data cache */ |
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| 118 | |
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| 119 | andi a0, s0, 0xff00 |
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| 120 | beq a0, zero, notintr |
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| 121 | nop |
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| 122 | |
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| 123 | /* disable timer0 */ |
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| 124 | la t0, XICU_BASE |
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| 125 | sw zero, XICU_PTI_PER(0)(t0) |
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| 126 | notintr: |
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| 127 | la a1, myvar |
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| 128 | la a0, 0(a1) |
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| 129 | beq a0, zero, noex |
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| 130 | nop |
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| 131 | EXIT(2) |
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| 132 | noex: |
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| 133 | li a0, 1 |
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| 134 | sw a0, 0(a1) |
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| 135 | lw a0, 4(sp) |
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| 136 | lw ra, 8(sp) |
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| 137 | addiu sp, sp, 8 |
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| 138 | eret |
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| 139 | /* we should not end there */ |
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| 140 | EXIT(1) |
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| 141 | |
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| 142 | .rodata: |
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| 143 | statusstr: .ascii "status \0" |
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| 144 | causestr: .ascii " cause \0" |
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| 145 | pcstr: .ascii " pc \0" |
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| 146 | badvastr: .ascii " badva \0" |
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| 147 | xicustr: .ascii " xicu \0" |
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| 148 | startstr: .ascii "start\n\0" |
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| 149 | endstr: .ascii "end \0" |
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| 150 | |
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| 151 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
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| 152 | .globl evect |
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| 153 | evect: |
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| 154 | j excep |
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| 155 | nop |
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| 156 | /* |
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| 157 | * we use a ldscript trick here, to load this function at |
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| 158 | * the appropriate address |
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| 159 | */ |
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| 160 | .section .text2, "ax" |
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| 161 | .globl doload |
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| 162 | doload: |
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| 163 | la s0, testval |
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| 164 | jr ra |
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| 165 | lw a1, 0(s0) /* this should trigger the exception */ |
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| 166 | /* we should not get there */ |
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| 167 | EXIT(1) |
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| 168 | nop |
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| 169 | .data |
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| 170 | myvar: .word 0 |
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| 171 | testval: |
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| 172 | .word MAGIC2 |
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| 173 | .globl pte2 |
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| 174 | pte2: |
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| 175 | .align 12 |
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| 176 | .word PTE2_V | PTE2_C | PTE2_X |
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| 177 | .word BOOT_ADDRESS >> 12 |
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| 178 | .org pte2 + 4092 |
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| 179 | .globl pte22 |
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| 180 | pte22: |
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| 181 | .align 12 |
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| 182 | .word 0 |
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| 183 | .word 0 |
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| 184 | .org pte22 + 4092 |
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| 185 | .globl pte1 |
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| 186 | pte1: |
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| 187 | .align 13 |
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| 188 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
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| 189 | .org pte1 + (DOLOAD_ADDR >> 21) * 4 |
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| 190 | .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map VA DOLOAD_ADDR with 4k page: check real address of PTE22 !!! */ |
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| 191 | .org pte1 + (BOOT_ADDRESS >> 21) * 4 |
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| 192 | .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */ |
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| 193 | .org pte1 + (TTY_BASE >> 21) * 4 |
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| 194 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
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| 195 | .org pte1 + (XICU_BASE >> 21) * 4 |
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| 196 | .word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */ |
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| 197 | .org pte1 + (EXIT_BASE >> 21) * 4 |
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| 198 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
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| 199 | .org pte1 + 8192 |
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| 200 | .word 0 |
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| 201 | |
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