| 1 | /* |
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| 2 | * itlb inval: a write to a PTE2 should invalidate the corresponding |
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| 3 | * itlb and dtlb entries. |
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| 4 | */ |
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| 5 | #include <registers.h> |
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| 6 | #include <misc.h> |
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| 7 | #include <vcache.h> |
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| 8 | |
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| 9 | .text |
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| 10 | .globl _start |
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| 11 | _start: |
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| 12 | .set noreorder |
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| 13 | la k0, TTY_BASE |
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| 14 | la k1, EXIT_BASE |
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| 15 | |
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| 16 | PRINT(startstr) |
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| 17 | |
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| 18 | /* reset cop0 status (keep BEV) */ |
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| 19 | lui a0, 0x0040; |
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| 20 | mtc0 a0, COP0_STATUS |
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| 21 | |
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| 22 | la a0, pte1_a |
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| 23 | srl a0, a0, 13 |
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| 24 | mtc2 a0, VC_PTPR |
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| 25 | nop |
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| 26 | |
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| 27 | li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE |
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| 28 | mtc2 a0, VC_TLB_EN |
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| 29 | |
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| 30 | PRINT(mmustr) |
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| 31 | /* cause a DTLB miss */ |
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| 32 | la t0, roval |
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| 33 | lw a0, 0(t0) |
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| 34 | PRINTX |
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| 35 | PUTCHAR(' ') |
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| 36 | |
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| 37 | /* cause a itlb miss */ |
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| 38 | jal doload |
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| 39 | nop |
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| 40 | PRINTX |
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| 41 | PUTCHAR(' ') |
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| 42 | |
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| 43 | la t0, pte2_a |
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| 44 | mtc2 t0, VC_DATA_L /* force dcache miss on write */ |
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| 45 | mtc2 zero, VC_DATA_H |
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| 46 | mtc2 zero, VC_DCACHE_INVAL_PA |
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| 47 | la a0, (BOOT_ADDRESS+0x2000) >> 12 |
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| 48 | sw a0, 12(t0) /* change PTE2 */ |
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| 49 | sync |
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| 50 | 1: |
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| 51 | ll a0, 8(t0) |
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| 52 | mtc2 t0, VC_DTLB_INVAL /* force tlb miss on write */ |
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| 53 | la a0, PTE2_V | PTE2_C | PTE2_X |
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| 54 | sc a0, 8(t0) |
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| 55 | beqz a0, 1b |
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| 56 | nop |
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| 57 | |
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| 58 | /* now we should get the second values */ |
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| 59 | la t0, roval |
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| 60 | lw a0, 0(t0) |
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| 61 | PRINTX |
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| 62 | PUTCHAR(' ') |
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| 63 | |
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| 64 | jal doload |
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| 65 | nop |
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| 66 | PRINTX |
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| 67 | PUTCHAR('\n') |
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| 68 | /* we should get there */ |
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| 69 | EXIT(0) |
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| 70 | |
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| 71 | .globl excep |
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| 72 | excep: |
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| 73 | .set noreorder |
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| 74 | PRINT(statusstr) |
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| 75 | mfc0 a0, COP0_STATUS |
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| 76 | PRINTX |
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| 77 | |
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| 78 | PRINT(causestr) |
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| 79 | mfc0 a0, COP0_CAUSE |
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| 80 | PRINTX |
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| 81 | |
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| 82 | PRINT(pcstr) |
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| 83 | mfc0 a0, COP0_EXPC |
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| 84 | PRINTX |
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| 85 | |
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| 86 | PRINT(badvastr) |
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| 87 | mfc0 a0, COP_0_BADVADDR |
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| 88 | PRINTX |
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| 89 | |
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| 90 | PUTCHAR('\n') |
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| 91 | /* we should not get there */ |
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| 92 | EXIT(1) |
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| 93 | |
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| 94 | .rodata: |
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| 95 | statusstr: .ascii "status \0" |
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| 96 | causestr: .ascii " cause \0" |
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| 97 | pcstr: .ascii " pc \0" |
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| 98 | badvastr: .ascii " badva \0" |
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| 99 | mmustr: .ascii "mmu started \0" |
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| 100 | startstr: .ascii "start\n\0" |
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| 101 | |
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| 102 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
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| 103 | .globl evect |
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| 104 | evect: |
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| 105 | j excep |
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| 106 | nop |
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| 107 | |
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| 108 | /* |
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| 109 | * code that will be switched by MMU switch. |
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| 110 | * we use a ldscript trick here, to load this function at |
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| 111 | * the appropriate address |
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| 112 | */ |
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| 113 | .section .text2, "ax" |
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| 114 | .globl doload |
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| 115 | doload: |
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| 116 | jr ra |
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| 117 | li a0, MAGIC1 |
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| 118 | /* we should not get there */ |
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| 119 | EXIT(1) |
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| 120 | nop |
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| 121 | roval: .word MAGIC2 |
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| 122 | .align 12 |
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| 123 | .globl doload2 |
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| 124 | doload2: |
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| 125 | jr ra |
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| 126 | li a0, MAGIC2 |
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| 127 | /* we should not get there */ |
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| 128 | EXIT(1) |
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| 129 | nop |
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| 130 | roval2: .word MAGIC1 |
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| 131 | |
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| 132 | .data |
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| 133 | .word MAGIC1 |
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| 134 | testval: |
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| 135 | .word MAGIC2 |
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| 136 | .globl pte2_a |
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| 137 | |
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| 138 | /* |
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| 139 | * one PD with a level 2 PTP: we change an entry in the PTP and |
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| 140 | * check that the ITLB has been invalidated |
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| 141 | */ |
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| 142 | pte2_a: |
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| 143 | .align 12 |
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| 144 | .word PTE2_V | PTE2_C | PTE2_X |
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| 145 | .word BOOT_ADDRESS >> 12 |
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| 146 | .word PTE2_V | PTE2_C | PTE2_X |
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| 147 | .word (BOOT_ADDRESS+0x1000) >> 12 |
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| 148 | .org pte2_a + 4092 |
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| 149 | .word 0 |
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| 150 | .globl pte2_b |
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| 151 | .globl pte1_a |
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| 152 | pte1_a: |
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| 153 | .align 13 |
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| 154 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
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| 155 | .word 0x0 |
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| 156 | .org pte1_a + (BOOT_ADDRESS >> 21) * 4 |
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| 157 | .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ |
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| 158 | .org pte1_a + (TTY_BASE >> 21) * 4 |
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| 159 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
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| 160 | .org pte1_a + (EXIT_BASE >> 21) * 4 |
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| 161 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
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| 162 | .org pte1_a + 8192 |
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