1 | /* |
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2 | * itlb inval: a write to a PTD1 should invalidate the corresponding |
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3 | * itlb and dtlb entries. |
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4 | */ |
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5 | #include <registers.h> |
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6 | #include <misc.h> |
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7 | #include <vcache.h> |
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8 | |
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9 | .text |
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10 | .globl _start |
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11 | _start: |
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12 | .set noreorder |
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13 | la k0, TTY_BASE |
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14 | la k1, EXIT_BASE |
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15 | |
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16 | PRINT(startstr) |
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17 | |
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18 | /* reset cop0 status (keep BEV) */ |
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19 | lui a0, 0x0040; |
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20 | mtc0 a0, COP0_STATUS |
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21 | |
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22 | la a0, pte1_a |
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23 | srl a0, a0, 13 |
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24 | mtc2 a0, VC_PTPR |
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25 | nop |
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26 | |
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27 | li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE |
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28 | mtc2 a0, VC_TLB_EN |
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29 | |
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30 | PRINT(mmustr) |
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31 | /* cause a DTLB miss */ |
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32 | la t0, roval |
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33 | lw a0, 0(t0) |
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34 | PRINTX |
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35 | PUTCHAR(' ') |
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36 | |
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37 | /* cause a itlb miss */ |
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38 | jal doload |
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39 | nop |
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40 | PRINTX |
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41 | PUTCHAR(' ') |
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42 | |
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43 | la t0, pte1_ac |
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44 | 1: |
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45 | ll a0, 0(t0) |
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46 | la a0, (0x2000 >> 12) | PTE1_V | PTE1_T /* check real address of pet2_b */ |
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47 | sc a0, 0(t0) /* change PTD1 */ |
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48 | beqz a0, 1b |
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49 | nop |
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50 | |
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51 | /* now we should get the second values */ |
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52 | la t0, roval |
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53 | lw a0, 0(t0) |
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54 | PRINTX |
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55 | PUTCHAR(' ') |
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56 | |
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57 | jal doload |
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58 | nop |
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59 | PRINTX |
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60 | PUTCHAR('\n') |
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61 | /* we should get there */ |
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62 | EXIT(0) |
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63 | |
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64 | .globl excep |
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65 | excep: |
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66 | .set noreorder |
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67 | PRINT(statusstr) |
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68 | mfc0 a0, COP0_STATUS |
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69 | PRINTX |
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70 | |
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71 | PRINT(causestr) |
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72 | mfc0 a0, COP0_CAUSE |
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73 | PRINTX |
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74 | |
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75 | PRINT(pcstr) |
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76 | mfc0 a0, COP0_EXPC |
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77 | PRINTX |
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78 | |
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79 | PRINT(badvastr) |
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80 | mfc0 a0, COP_0_BADVADDR |
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81 | PRINTX |
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82 | |
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83 | PUTCHAR('\n') |
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84 | /* we should not get there */ |
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85 | EXIT(1) |
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86 | |
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87 | .rodata: |
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88 | statusstr: .ascii "status \0" |
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89 | causestr: .ascii " cause \0" |
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90 | pcstr: .ascii " pc \0" |
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91 | badvastr: .ascii " badva \0" |
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92 | mmustr: .ascii "mmu started \0" |
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93 | startstr: .ascii "start\n\0" |
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94 | |
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95 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
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96 | .globl evect |
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97 | evect: |
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98 | j excep |
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99 | nop |
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100 | |
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101 | /* |
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102 | * code that will be switched by MMU switch. |
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103 | * we use a ldscript trick here, to load this function at |
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104 | * the appropriate address |
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105 | */ |
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106 | .section .text2, "ax" |
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107 | .globl doload |
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108 | doload: |
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109 | jr ra |
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110 | li a0, MAGIC1 |
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111 | /* we should not get there */ |
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112 | EXIT(1) |
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113 | nop |
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114 | roval: .word MAGIC2 |
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115 | .align 12 |
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116 | .globl doload2 |
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117 | doload2: |
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118 | jr ra |
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119 | li a0, MAGIC2 |
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120 | /* we should not get there */ |
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121 | EXIT(1) |
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122 | nop |
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123 | roval2: .word MAGIC1 |
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124 | |
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125 | .data |
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126 | .word MAGIC1 |
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127 | testval: |
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128 | .word MAGIC2 |
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129 | .globl pte2_a |
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130 | |
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131 | /* |
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132 | * one PD with a level 2 PTP: we change an entry in the PD and |
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133 | * check that the TLBs has been invalidated |
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134 | */ |
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135 | pte2_a: |
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136 | .align 12 |
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137 | .word PTE2_V | PTE2_C | PTE2_X |
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138 | .word BOOT_ADDRESS >> 12 |
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139 | .word PTE2_V | PTE2_C | PTE2_X |
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140 | .word (BOOT_ADDRESS+0x1000) >> 12 /* address of doload */ |
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141 | .org pte2_a + 4092 |
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142 | .word 0 |
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143 | .globl pte2_b |
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144 | .globl pte1_a |
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145 | pte2_b: |
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146 | .align 12 |
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147 | .word PTE2_V | PTE2_C | PTE2_X |
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148 | .word BOOT_ADDRESS >> 12 |
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149 | .word PTE2_V | PTE2_C | PTE2_X |
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150 | .word (BOOT_ADDRESS+0x2000) >> 12 /* address of doload2 */ |
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151 | .org pte2_b + 4092 |
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152 | .word 0 |
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153 | .globl pte2_b |
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154 | .globl pte1_a |
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155 | pte1_a: |
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156 | .align 13 |
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157 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
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158 | .word 0x0 |
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159 | .org pte1_a + (BOOT_ADDRESS >> 21) * 4 |
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160 | pte1_ac: |
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161 | .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ |
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162 | .org pte1_a + (TTY_BASE >> 21) * 4 |
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163 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
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164 | .org pte1_a + (EXIT_BASE >> 21) * 4 |
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165 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
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166 | .org pte1_a + 8192 |
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