[520] | 1 | /* |
---|
| 2 | * Check interrupt/return with interrup occuring at various points in |
---|
| 3 | * the software. Cache is enabled to we have on interrupt/cycle |
---|
| 4 | */ |
---|
| 5 | #include <registers.h> |
---|
| 6 | #include <misc.h> |
---|
| 7 | #include <vcache.h> |
---|
| 8 | #include <xicu.h> |
---|
| 9 | |
---|
| 10 | .text |
---|
| 11 | .globl _start |
---|
| 12 | _start: |
---|
| 13 | .set noreorder |
---|
| 14 | la k0, TTY_BASE |
---|
| 15 | la k1, EXIT_BASE |
---|
| 16 | |
---|
| 17 | /* reset cause, make sure IV is off */ |
---|
| 18 | mtc0 zero, COP0_CAUSE |
---|
| 19 | |
---|
| 20 | la a0, pte1 |
---|
| 21 | srl a0, a0, 13 |
---|
| 22 | mtc2 a0, VC_PTPR |
---|
| 23 | nop |
---|
| 24 | nop |
---|
| 25 | |
---|
| 26 | li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE |
---|
| 27 | mtc2 a0, VC_TLB_EN |
---|
| 28 | |
---|
| 29 | PRINT(startstr) |
---|
| 30 | |
---|
| 31 | /* program xicu */ |
---|
| 32 | la t0, XICU_BASE |
---|
| 33 | /* clear pending interrupt */ |
---|
| 34 | lw a0, XICU_PTI_ACK(0)(t0) |
---|
| 35 | /* route PTI0 to irq 0 */ |
---|
| 36 | li a0, 1 << 0 |
---|
| 37 | sw a0, XICU_MSK_PTI_E(0)(t0) |
---|
| 38 | /* init s0 */ |
---|
| 39 | li s0, MAGIC2 |
---|
| 40 | |
---|
| 41 | /* reset cop0 status (keep BEV), enable soft interrupt 0 */ |
---|
| 42 | lui a0, 0x0040; |
---|
| 43 | addiu a0, 0x0101; |
---|
| 44 | mtc0 a0, COP0_STATUS |
---|
| 45 | #if 1 |
---|
| 46 | /* trigger soft interrupt, so that exept is in cache */ |
---|
| 47 | mfc0 a0, COP0_CAUSE |
---|
| 48 | ori a0, 0x0100 |
---|
| 49 | mtc0 a0, COP0_CAUSE |
---|
| 50 | nop |
---|
| 51 | #endif |
---|
| 52 | |
---|
| 53 | /* |
---|
| 54 | * interrupt in INTERRUPT_DELAY cycles. |
---|
| 55 | */ |
---|
| 56 | la t0, XICU_BASE |
---|
| 57 | li a0, INTERRUPT_DELAY |
---|
| 58 | sw a0, XICU_PTI_PER(0)(t0) |
---|
| 59 | /* clear pending interrupt */ |
---|
| 60 | lw a0, XICU_PTI_ACK(0)(t0) |
---|
| 61 | /* reset cop0 status (keep BEV), enable interrupt 0 */ |
---|
| 62 | lui a0, 0x0040; |
---|
| 63 | addiu a0, 0x0401; |
---|
| 64 | mtc0 a0, COP0_STATUS |
---|
| 65 | |
---|
| 66 | li s0, MAGIC1 |
---|
| 67 | li s1, MAGIC2 |
---|
| 68 | addiu s0, s0, -1 |
---|
| 69 | jal incr |
---|
| 70 | nop |
---|
| 71 | addiu s0, s0, -1 |
---|
| 72 | jal incr |
---|
| 73 | nop |
---|
| 74 | addiu s0, s0, -1 |
---|
| 75 | jal incr |
---|
| 76 | nop |
---|
| 77 | addiu s0, s0, -1 |
---|
| 78 | jal incr |
---|
| 79 | nop |
---|
| 80 | j end |
---|
| 81 | addiu s1, s1, 5 |
---|
| 82 | nop |
---|
| 83 | /* we should not end there */ |
---|
| 84 | EXIT(1) |
---|
| 85 | |
---|
| 86 | .align 6 |
---|
| 87 | nop |
---|
| 88 | incr: |
---|
| 89 | addiu s1, s1, -1 |
---|
| 90 | j ra |
---|
| 91 | addiu s0, s0, 1 |
---|
| 92 | |
---|
| 93 | .align 6 |
---|
| 94 | end: |
---|
| 95 | PRINT(endstr) |
---|
| 96 | move a0, s0 |
---|
| 97 | PRINTX |
---|
| 98 | PUTCHAR(' ') |
---|
| 99 | move a0, s1 |
---|
| 100 | PRINTX |
---|
| 101 | PUTCHAR('\n') |
---|
| 102 | EXIT(0) |
---|
| 103 | fail: |
---|
| 104 | EXIT(4) |
---|
| 105 | |
---|
| 106 | |
---|
| 107 | .rodata: |
---|
| 108 | statusstr: .ascii "status \0" |
---|
| 109 | causestr: .ascii " cause \0" |
---|
| 110 | pcstr: .ascii " pc \0" |
---|
| 111 | badvastr: .ascii " badva \0" |
---|
| 112 | xicustr: .ascii " xicu \0" |
---|
| 113 | startstr: .ascii "start\n\0" |
---|
| 114 | endstr: .ascii "end \0" |
---|
| 115 | |
---|
| 116 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
---|
| 117 | .globl excep |
---|
| 118 | excep: |
---|
| 119 | .set noreorder |
---|
| 120 | move s2, ra |
---|
| 121 | mfc0 a0, COP0_CAUSE |
---|
| 122 | andi a0, a0, 0x0400 |
---|
| 123 | beq a0, zero, softint |
---|
| 124 | nop |
---|
| 125 | /* disable timer0 */ |
---|
| 126 | la t0, XICU_BASE |
---|
| 127 | sw zero, XICU_PTI_PER(0)(t0) |
---|
| 128 | |
---|
| 129 | PRINT(statusstr) |
---|
| 130 | mfc0 a0, COP0_STATUS |
---|
| 131 | PRINTX |
---|
| 132 | |
---|
| 133 | PRINT(causestr) |
---|
| 134 | mfc0 a0, COP0_CAUSE |
---|
| 135 | PRINTX |
---|
| 136 | |
---|
| 137 | PRINT(pcstr) |
---|
| 138 | mfc0 a0, COP0_EXPC |
---|
| 139 | PRINTX |
---|
| 140 | |
---|
| 141 | PRINT(badvastr) |
---|
| 142 | mfc0 a0, COP_0_BADVADDR |
---|
| 143 | PRINTX |
---|
| 144 | |
---|
| 145 | PRINT(xicustr) |
---|
| 146 | la t0, XICU_BASE |
---|
| 147 | lw a0, XICU_PRIO(0)(t0) |
---|
| 148 | PRINTX |
---|
| 149 | |
---|
| 150 | PUTCHAR('\n') |
---|
| 151 | softint: |
---|
| 152 | /* clear interrupt */ |
---|
| 153 | mfc0 a0, COP0_CAUSE |
---|
| 154 | andi t0, a0, 0xff00 |
---|
| 155 | xor a0, a0, t0 |
---|
| 156 | mtc0 a0, COP0_CAUSE |
---|
| 157 | /* fluch cache line of incr */ |
---|
| 158 | la a0, incr |
---|
| 159 | mtc2 a0, VC_ICACHE_INVAL |
---|
| 160 | //mtc2 a0, VC_ITLB_INVAL |
---|
| 161 | move ra, s2 |
---|
| 162 | la s2, fail |
---|
| 163 | eret |
---|
| 164 | /* we should not end there */ |
---|
| 165 | EXIT(3) |
---|
| 166 | .data |
---|
| 167 | myvar: .word 0 |
---|
| 168 | pte1: |
---|
| 169 | .align 13 |
---|
| 170 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
---|
| 171 | .org pte1 + (BOOT_ADDRESS >> 21) * 4 |
---|
| 172 | .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ |
---|
| 173 | .org pte1 + (TTY_BASE >> 21) * 4 |
---|
| 174 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
---|
| 175 | .org pte1 + (XICU_BASE >> 21) * 4 |
---|
| 176 | .word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */ |
---|
| 177 | .org pte1 + (EXIT_BASE >> 21) * 4 |
---|
| 178 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
---|
| 179 | .org pte1 + 8192 |
---|
| 180 | .word 0 |
---|
| 181 | |
---|