| 1 | /* |
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| 2 | * Check interrupt/return with interrup occuring at various points in |
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| 3 | * the software. Cache is enabled to we have on interrupt/cycle |
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| 4 | */ |
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| 5 | #include <registers.h> |
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| 6 | #include <misc.h> |
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| 7 | #include <vcache.h> |
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| 8 | #include <xicu.h> |
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| 9 | |
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| 10 | .text |
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| 11 | .globl _start |
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| 12 | _start: |
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| 13 | .set noreorder |
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| 14 | la k0, TTY_BASE |
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| 15 | la k1, EXIT_BASE |
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| 16 | |
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| 17 | /* reset cause, make sure IV is off */ |
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| 18 | mtc0 zero, COP0_CAUSE |
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| 19 | |
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| 20 | la a0, pte1 |
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| 21 | srl a0, a0, 13 |
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| 22 | mtc2 a0, VC_PTPR |
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| 23 | nop |
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| 24 | nop |
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| 25 | |
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| 26 | li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE |
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| 27 | mtc2 a0, VC_TLB_EN |
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| 28 | |
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| 29 | PRINT(startstr) |
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| 30 | |
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| 31 | /* program xicu */ |
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| 32 | la t0, XICU_BASE |
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| 33 | /* clear pending interrupt */ |
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| 34 | lw a0, XICU_PTI_ACK(0)(t0) |
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| 35 | /* route PTI0 to irq 0 */ |
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| 36 | li a0, 1 << 0 |
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| 37 | sw a0, XICU_MSK_PTI_E(0)(t0) |
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| 38 | /* init s0 */ |
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| 39 | li s0, MAGIC2 |
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| 40 | |
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| 41 | /* reset cop0 status (keep BEV), enable soft interrupt 0 */ |
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| 42 | lui a0, 0x0040; |
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| 43 | addiu a0, 0x0101; |
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| 44 | mtc0 a0, COP0_STATUS |
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| 45 | #if 1 |
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| 46 | /* trigger soft interrupt, so that exept is in cache */ |
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| 47 | mfc0 a0, COP0_CAUSE |
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| 48 | ori a0, 0x0100 |
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| 49 | mtc0 a0, COP0_CAUSE |
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| 50 | nop |
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| 51 | #endif |
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| 52 | |
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| 53 | /* |
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| 54 | * interrupt in INTERRUPT_DELAY cycles. |
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| 55 | */ |
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| 56 | la t0, XICU_BASE |
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| 57 | li a0, INTERRUPT_DELAY |
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| 58 | sw a0, XICU_PTI_PER(0)(t0) |
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| 59 | /* clear pending interrupt */ |
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| 60 | lw a0, XICU_PTI_ACK(0)(t0) |
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| 61 | /* reset cop0 status (keep BEV), enable interrupt 0 */ |
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| 62 | lui a0, 0x0040; |
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| 63 | addiu a0, 0x0401; |
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| 64 | mtc0 a0, COP0_STATUS |
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| 65 | |
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| 66 | li s0, MAGIC1 |
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| 67 | li s1, MAGIC2 |
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| 68 | addiu s0, s0, -1 |
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| 69 | jal incr |
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| 70 | nop |
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| 71 | addiu s0, s0, -1 |
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| 72 | jal incr |
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| 73 | nop |
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| 74 | addiu s0, s0, -1 |
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| 75 | jal incr |
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| 76 | nop |
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| 77 | addiu s0, s0, -1 |
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| 78 | jal incr |
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| 79 | nop |
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| 80 | j end |
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| 81 | addiu s1, s1, 5 |
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| 82 | nop |
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| 83 | /* we should not end there */ |
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| 84 | EXIT(1) |
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| 85 | |
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| 86 | .align 6 |
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| 87 | nop |
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| 88 | incr: |
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| 89 | addiu s1, s1, -1 |
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| 90 | j ra |
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| 91 | addiu s0, s0, 1 |
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| 92 | |
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| 93 | .align 6 |
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| 94 | end: |
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| 95 | PRINT(endstr) |
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| 96 | move a0, s0 |
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| 97 | PRINTX |
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| 98 | PUTCHAR(' ') |
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| 99 | move a0, s1 |
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| 100 | PRINTX |
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| 101 | PUTCHAR('\n') |
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| 102 | EXIT(0) |
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| 103 | fail: |
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| 104 | EXIT(4) |
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| 105 | |
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| 106 | |
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| 107 | .rodata: |
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| 108 | statusstr: .ascii "status \0" |
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| 109 | causestr: .ascii " cause \0" |
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| 110 | pcstr: .ascii " pc \0" |
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| 111 | badvastr: .ascii " badva \0" |
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| 112 | xicustr: .ascii " xicu \0" |
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| 113 | startstr: .ascii "start\n\0" |
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| 114 | endstr: .ascii "end \0" |
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| 115 | |
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| 116 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
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| 117 | .globl excep |
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| 118 | excep: |
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| 119 | .set noreorder |
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| 120 | move s2, ra |
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| 121 | mfc0 a0, COP0_CAUSE |
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| 122 | andi a0, a0, 0x0400 |
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| 123 | beq a0, zero, softint |
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| 124 | nop |
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| 125 | /* disable timer0 */ |
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| 126 | la t0, XICU_BASE |
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| 127 | sw zero, XICU_PTI_PER(0)(t0) |
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| 128 | |
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| 129 | PRINT(statusstr) |
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| 130 | mfc0 a0, COP0_STATUS |
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| 131 | PRINTX |
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| 132 | |
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| 133 | PRINT(causestr) |
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| 134 | mfc0 a0, COP0_CAUSE |
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| 135 | PRINTX |
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| 136 | |
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| 137 | PRINT(pcstr) |
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| 138 | mfc0 a0, COP0_EXPC |
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| 139 | PRINTX |
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| 140 | |
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| 141 | PRINT(badvastr) |
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| 142 | mfc0 a0, COP_0_BADVADDR |
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| 143 | PRINTX |
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| 144 | |
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| 145 | PRINT(xicustr) |
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| 146 | la t0, XICU_BASE |
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| 147 | lw a0, XICU_PRIO(0)(t0) |
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| 148 | PRINTX |
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| 149 | |
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| 150 | PUTCHAR('\n') |
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| 151 | softint: |
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| 152 | /* clear interrupt */ |
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| 153 | mfc0 a0, COP0_CAUSE |
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| 154 | andi t0, a0, 0xff00 |
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| 155 | xor a0, a0, t0 |
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| 156 | mtc0 a0, COP0_CAUSE |
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| 157 | /* fluch cache line of incr */ |
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| 158 | la a0, incr |
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| 159 | mtc2 a0, VC_ICACHE_INVAL |
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| 160 | //mtc2 a0, VC_ITLB_INVAL |
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| 161 | move ra, s2 |
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| 162 | la s2, fail |
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| 163 | eret |
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| 164 | /* we should not end there */ |
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| 165 | EXIT(3) |
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| 166 | .data |
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| 167 | myvar: .word 0 |
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| 168 | pte1: |
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| 169 | .align 13 |
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| 170 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
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| 171 | .org pte1 + (BOOT_ADDRESS >> 21) * 4 |
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| 172 | .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ |
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| 173 | .org pte1 + (TTY_BASE >> 21) * 4 |
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| 174 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
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| 175 | .org pte1 + (XICU_BASE >> 21) * 4 |
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| 176 | .word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */ |
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| 177 | .org pte1 + (EXIT_BASE >> 21) * 4 |
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| 178 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
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| 179 | .org pte1 + 8192 |
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| 180 | .word 0 |
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| 181 | |
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