1 | /* |
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2 | * Check interrupt/return with interrup occuring at various points in |
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3 | * the software. Cache is enabled to we have on interrupt/cycle |
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4 | */ |
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5 | #include <registers.h> |
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6 | #include <misc.h> |
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7 | #include <vcache.h> |
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8 | #include <xicu.h> |
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9 | |
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10 | .text |
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11 | .globl _start |
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12 | _start: |
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13 | .set noreorder |
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14 | la k0, TTY_BASE |
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15 | la k1, EXIT_BASE |
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16 | |
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17 | /* reset cause, make sure IV is off */ |
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18 | mtc0 zero, COP0_CAUSE |
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19 | |
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20 | la a0, pte1 |
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21 | srl a0, a0, 13 |
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22 | mtc2 a0, VC_PTPR |
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23 | nop |
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24 | |
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25 | li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE |
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26 | mtc2 a0, VC_TLB_EN |
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27 | |
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28 | PRINT(startstr) |
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29 | |
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30 | /* program xicu */ |
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31 | la t0, XICU_BASE |
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32 | /* clear pending interrupt */ |
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33 | lw a0, XICU_PTI_ACK(0)(t0) |
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34 | /* route PTI0 to irq 0 */ |
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35 | li a0, 1 << 0 |
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36 | sw a0, XICU_MSK_PTI_E(0)(t0) |
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37 | /* init s0 */ |
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38 | li s0, MAGIC2 |
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39 | /* |
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40 | * interrupt in INTERRUPT_DELAY cycles. |
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41 | */ |
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42 | li s2, 1 |
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43 | sw s2, XICU_PTI_PER(0)(t0) |
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44 | /* clear pending interrupt */ |
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45 | lw a0, XICU_PTI_ACK(0)(t0) |
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46 | /* reset cop0 status (keep BEV), enable interrupt 0 */ |
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47 | lui a0, 0x0040; |
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48 | addiu a0, 0x0401; |
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49 | mtc0 a0, COP0_STATUS |
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50 | |
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51 | nop |
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52 | li s0, MAGIC1 |
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53 | addiu s0, s0, -1 |
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54 | loop: |
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55 | addiu s0, s0, -1 |
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56 | addiu s0, s0, -1 |
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57 | addiu s0, s0, -1 |
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58 | j bla |
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59 | addiu s0, s0, 5 |
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60 | EXIT(1) |
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61 | addiu s0, s0, -1 |
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62 | .align 6 |
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63 | bla: |
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64 | addiu s0, s0, -1 |
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65 | li s1, MAGIC1 |
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66 | beq s0, s1, loop |
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67 | addiu s0, s0, -1 |
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68 | |
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69 | /* we should not end there */ |
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70 | EXIT(1) |
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71 | |
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72 | .align 6 |
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73 | end: |
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74 | PRINT(endstr) |
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75 | move a0, s0 |
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76 | PRINTX |
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77 | PUTCHAR('\n') |
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78 | EXIT(0) |
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79 | |
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80 | .rodata: |
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81 | statusstr: .ascii "status \0" |
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82 | causestr: .ascii " cause \0" |
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83 | pcstr: .ascii " pc \0" |
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84 | badvastr: .ascii " badva \0" |
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85 | xicustr: .ascii " xicu \0" |
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86 | startstr: .ascii "start\n\0" |
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87 | perstr: .ascii " period \0" |
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88 | endstr: .ascii "end \0" |
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89 | |
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90 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
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91 | .globl excep |
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92 | excep: |
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93 | .set noreorder |
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94 | addiu s0, s0, -10 |
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95 | /* disable timer0 */ |
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96 | la t0, XICU_BASE |
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97 | sw zero, XICU_PTI_PER(0)(t0) |
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98 | PRINT(statusstr) |
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99 | mfc0 a0, COP0_STATUS |
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100 | PRINTX |
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101 | |
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102 | PRINT(pcstr) |
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103 | mfc0 a0, COP0_EXPC |
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104 | PRINTX |
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105 | |
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106 | PRINT(causestr) |
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107 | mfc0 a0, COP0_CAUSE |
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108 | PRINTX |
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109 | |
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110 | PRINT(badvastr) |
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111 | mfc0 a0, COP_0_BADVADDR |
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112 | PRINTX |
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113 | |
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114 | PRINT(xicustr) |
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115 | la t0, XICU_BASE |
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116 | lw a0, XICU_PRIO(0)(t0) |
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117 | PRINTX |
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118 | |
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119 | // PRINT(perstr) |
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120 | // move a0, s2 |
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121 | // PRINTX |
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122 | // |
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123 | PUTCHAR('\n') |
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124 | |
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125 | #if 0 |
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126 | andi s3, s2, 1 |
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127 | beqz s3, noflush |
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128 | #endif |
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129 | addiu s0, s0, 10 |
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130 | |
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131 | #if 1 |
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132 | // Flush cache of jump routine |
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133 | la s3, bla |
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134 | mtc2 s3, VC_ICACHE_INVAL |
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135 | mtc2 s3, VC_ITLB_INVAL |
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136 | #endif |
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137 | |
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138 | noflush: |
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139 | addiu s2, s2, 1 |
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140 | li s3, 194*2 |
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141 | beq s2, s3, end2 |
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142 | srl s3, s2, 1 |
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143 | la t0, XICU_BASE |
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144 | sw s3, XICU_PTI_PER(0)(t0) |
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145 | eret |
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146 | /* we should not end there */ |
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147 | EXIT(1) |
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148 | end2: |
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149 | EXIT(0) |
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150 | |
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151 | .data |
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152 | myvar: .word 0 |
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153 | pte1: |
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154 | .align 13 |
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155 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
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156 | .org pte1 + (BOOT_ADDRESS >> 21) * 4 |
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157 | .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ |
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158 | .org pte1 + (TTY_BASE >> 21) * 4 |
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159 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
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160 | .org pte1 + (XICU_BASE >> 21) * 4 |
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161 | .word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */ |
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162 | .org pte1 + (EXIT_BASE >> 21) * 4 |
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163 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
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164 | .org pte1 + 8192 |
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165 | .word 0 |
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166 | |
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