[520] | 1 | /* |
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| 2 | * itlb inval: a write to VC_ITLB_INVAL should invalidate the corresponding |
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| 3 | * itlb entry. On a ccvcache, VC_ITLB_INVAL should not be needed, and |
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| 4 | * the first access after clearing pte2_a should fail |
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| 5 | */ |
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| 6 | #include <registers.h> |
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| 7 | #include <misc.h> |
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| 8 | #include <vcache.h> |
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| 9 | |
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| 10 | .text |
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| 11 | .globl _start |
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| 12 | _start: |
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| 13 | .set noreorder |
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| 14 | la k0, TTY_BASE |
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| 15 | la k1, EXIT_BASE |
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| 16 | |
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| 17 | PRINT(startstr) |
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| 18 | |
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| 19 | /* reset cop0 status (keep BEV) */ |
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| 20 | lui a0, 0x0040; |
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| 21 | mtc0 a0, COP0_STATUS |
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| 22 | |
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| 23 | la a0, pte1_a |
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| 24 | srl a0, a0, 13 |
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| 25 | mtc2 a0, VC_PTPR |
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| 26 | nop |
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| 27 | |
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| 28 | li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE |
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| 29 | mtc2 a0, VC_TLB_EN |
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| 30 | |
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| 31 | PRINT(mmustr) |
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| 32 | jal doload |
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| 33 | nop |
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| 34 | PRINTX |
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| 35 | PUTCHAR(' ') |
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| 36 | la a0, pte2_a |
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| 37 | sw zero, 8(a0) /* invalidate PTE2 */ |
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| 38 | sync |
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| 39 | la a0, pte2_a /* make the sync synchronous */ |
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| 40 | jal doload /* TLB entry not invalidated yet, we can do this */ |
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| 41 | nop |
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| 42 | PRINTX |
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| 43 | PUTCHAR('\n') |
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| 44 | la a0, doload |
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| 45 | mtc2 a0, VC_ITLB_INVAL /* invalidate VA */ |
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| 46 | jal doload /* this should fail now */ |
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| 47 | nop |
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| 48 | PRINTX |
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| 49 | PUTCHAR('\n') |
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| 50 | |
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| 51 | /* we should not get there */ |
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| 52 | EXIT(1) |
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| 53 | |
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| 54 | .globl excep |
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| 55 | excep: |
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| 56 | .set noreorder |
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| 57 | PRINT(statusstr) |
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| 58 | mfc0 a0, COP0_STATUS |
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| 59 | PRINTX |
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| 60 | |
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| 61 | PRINT(causestr) |
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| 62 | mfc0 a0, COP0_CAUSE |
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| 63 | PRINTX |
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| 64 | |
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| 65 | PRINT(pcstr) |
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| 66 | mfc0 a0, COP0_EXPC |
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| 67 | PRINTX |
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| 68 | |
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| 69 | PRINT(badvastr) |
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| 70 | mfc0 a0, COP_0_BADVADDR |
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| 71 | PRINTX |
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| 72 | |
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| 73 | PUTCHAR('\n') |
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| 74 | /* we should get there */ |
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| 75 | EXIT(0) |
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| 76 | |
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| 77 | .rodata: |
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| 78 | statusstr: .ascii "status \0" |
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| 79 | causestr: .ascii " cause \0" |
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| 80 | pcstr: .ascii " pc \0" |
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| 81 | badvastr: .ascii " badva \0" |
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| 82 | mmustr: .ascii "mmu started \0" |
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| 83 | startstr: .ascii "start\n\0" |
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| 84 | |
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| 85 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
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| 86 | .globl evect |
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| 87 | evect: |
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| 88 | j excep |
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| 89 | nop |
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| 90 | |
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| 91 | /* |
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| 92 | * code that will be switched by MMU switch. |
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| 93 | * we use a ldscript trick here, to load this function at |
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| 94 | * the appropriate address |
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| 95 | */ |
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| 96 | .section .text2, "ax" |
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| 97 | .globl doload |
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| 98 | doload: |
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| 99 | jr ra |
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| 100 | li a0, MAGIC1 |
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| 101 | /* we should not get there */ |
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| 102 | EXIT(1) |
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| 103 | nop |
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| 104 | |
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| 105 | .data |
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| 106 | .word MAGIC1 |
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| 107 | testval: |
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| 108 | .word MAGIC2 |
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| 109 | .globl pte2_a |
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| 110 | |
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| 111 | /* |
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| 112 | * one PD with a level 2 PTP: we invalidate an entry in the PTP and |
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| 113 | * check that the VA is no longer accessible |
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| 114 | */ |
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| 115 | pte2_a: |
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| 116 | .align 12 |
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| 117 | .word PTE2_V | PTE2_C | PTE2_X |
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| 118 | .word BOOT_ADDRESS >> 12 |
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| 119 | .word PTE2_V | PTE2_C | PTE2_X |
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| 120 | .word (BOOT_ADDRESS+0x1000) >> 12 |
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| 121 | .org pte2_a + 4092 |
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| 122 | .word 0 |
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| 123 | .globl pte2_b |
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| 124 | .globl pte1_a |
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| 125 | pte1_a: |
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| 126 | .align 13 |
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| 127 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
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| 128 | .word 0x0 |
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| 129 | .org pte1_a + (BOOT_ADDRESS >> 21) * 4 |
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| 130 | .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ |
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| 131 | .org pte1_a + (TTY_BASE >> 21) * 4 |
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| 132 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
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| 133 | .org pte1_a + (EXIT_BASE >> 21) * 4 |
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| 134 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
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| 135 | .org pte1_a + 8192 |
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