source: trunk/softs/tests_cc_vcache/test_itlb_inval/test.S @ 540

Last change on this file since 540 was 520, checked in by bouyer, 11 years ago

Re-add the tests; reverting previous which was done at the wrong level (sorry)
File size: 2.7 KB
Line 
1/*
2 * itlb inval: a write to VC_ITLB_INVAL should invalidate the corresponding
3 * itlb entry. On a ccvcache, VC_ITLB_INVAL should not be needed, and
4 * the first access after clearing pte2_a should fail
5 */
6#include <registers.h>
7#include <misc.h>
8#include <vcache.h>
9
10        .text
11        .globl  _start
12_start:
13        .set noreorder
14        la      k0, TTY_BASE
15        la      k1, EXIT_BASE
16
17        PRINT(startstr)
18
19        /* reset cop0 status (keep BEV) */
20        lui     a0, 0x0040;
21        mtc0    a0, COP0_STATUS
22
23        la      a0, pte1_a
24        srl     a0, a0, 13
25        mtc2    a0, VC_PTPR
26        nop
27
28        li      a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
29        mtc2    a0, VC_TLB_EN
30
31        PRINT(mmustr)
32        jal     doload
33        nop
34        PRINTX
35        PUTCHAR(' ')
36        la      a0, pte2_a
37        sw      zero, 8(a0) /* invalidate PTE2 */
38        sync
39        la      a0, pte2_a /* make the sync synchronous */
40        jal     doload /* TLB entry not invalidated yet, we can do this */
41        nop
42        PRINTX
43        PUTCHAR('\n')
44        la      a0, doload
45        mtc2    a0, VC_ITLB_INVAL /* invalidate VA */
46        jal     doload /* this should fail now */
47        nop
48        PRINTX
49        PUTCHAR('\n')
50
51        /* we should not get there */
52        EXIT(1)
53
54        .globl excep
55excep:
56        .set noreorder
57        PRINT(statusstr)
58        mfc0    a0, COP0_STATUS
59        PRINTX
60
61        PRINT(causestr)
62        mfc0    a0, COP0_CAUSE
63        PRINTX
64
65        PRINT(pcstr)
66        mfc0    a0, COP0_EXPC
67        PRINTX
68
69        PRINT(badvastr)
70        mfc0    a0, COP_0_BADVADDR
71        PRINTX
72
73        PUTCHAR('\n')
74        /* we should get there */
75        EXIT(0)
76
77        .rodata:
78statusstr: .ascii "status \0"
79causestr: .ascii " cause \0"
80pcstr: .ascii " pc \0"
81badvastr: .ascii " badva \0"
82mmustr: .ascii "mmu started \0"
83startstr: .ascii "start\n\0"
84
85        .org EXCEP_ADDRESS - BOOT_ADDRESS
86        .globl evect
87evect:
88        j       excep
89        nop
90
91        /*
92         * code that will be switched by MMU switch.
93         * we use a ldscript trick here, to load this function at
94         * the appropriate address
95         */
96        .section .text2, "ax"
97        .globl doload
98doload:
99        jr      ra
100        li      a0, MAGIC1
101        /* we should not get there */
102        EXIT(1)
103        nop
104
105        .data
106        .word MAGIC1
107testval:
108        .word MAGIC2
109        .globl pte2_a
110
111/*
112 * one PD with a level 2 PTP: we invalidate an entry in the PTP and
113 * check that the VA is no longer accessible
114 */
115pte2_a:
116        .align 12
117        .word PTE2_V | PTE2_C | PTE2_X
118        .word BOOT_ADDRESS >> 12
119        .word PTE2_V | PTE2_C | PTE2_X
120        .word (BOOT_ADDRESS+0x1000) >> 12
121        .org pte2_a + 4092
122        .word 0
123        .globl pte2_b
124        .globl pte1_a
125pte1_a:
126        .align 13
127        .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
128        .word 0x0
129        .org pte1_a + (BOOT_ADDRESS >> 21) * 4
130        .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
131        .org pte1_a + (TTY_BASE >> 21) * 4
132        .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
133        .org pte1_a + (EXIT_BASE >> 21) * 4
134        .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
135        .org pte1_a + 8192
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