source: trunk/softs/tests_cc_vcache/test_itlb_ptprinval/test.S @ 445

Last change on this file since 445 was 232, checked in by alain, 12 years ago

Introducing the elementary tests for a TSAR mono-cluster
mono-processor platform with MMU using the vci_cc_vcache_v4
such as the "tsarv4_mono_mmu".
(assemby level tests written by Manuel Bouyer)
File size: 3.4 KB
Line 
1/*
2 * itlb inval on PTPR write: check that no stale entry exists in the itlb
3 * after MMU context swicth
4 */
5#include <registers.h>
6#include <misc.h>
7#include <vcache.h>
8        .text
9        .globl  _start
10_start:
11        .set noreorder
12        la      k0, TTY_BASE
13        la      k1, EXIT_BASE
14
15        PRINT(startstr)
16
17        /* reset cop0 status (keep BEV) */
18        lui     a0, 0x0040;
19        mtc0    a0, COP0_STATUS
20
21        la      a0, pte1_b
22        srl     a0, a0, 13
23        mtc2    a0, VC_PTPR
24        nop
25
26        li      a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
27        mtc2    a0, VC_TLB_EN
28
29        PRINT(mmustr_b)
30        jal     doload
31        nop
32        PRINTX
33        PUTCHAR('\n')
34        la      a0, pte1_a
35        srl     a0, a0, 13
36        mtc2    a0, VC_PTPR
37        nop
38#if 0 /* works with this - this shows the old pte2 address is cached */
39        la      a0, pte2_a
40        lw      a1, 12(a0)
41        la      a0, pte2_b
42        sw      a1, 12(a0)
43#endif
44        PRINT(mmustr_a)
45        jal     doload
46        nop
47        PRINTX
48        PUTCHAR('\n')
49
50        /* we should get there */
51        EXIT(0)
52
53        .globl excep
54excep:
55        .set noreorder
56        PRINT(statusstr)
57        mfc0    a0, COP0_STATUS
58        PRINTX
59
60        PRINT(causestr)
61        mfc0    a0, COP0_CAUSE
62        PRINTX
63
64        PRINT(pcstr)
65        mfc0    a0, COP0_EXPC
66        PRINTX
67
68        PRINT(badvastr)
69        mfc0    a0, COP_0_BADVADDR
70        PRINTX
71
72        PUTCHAR('\n')
73        /* we should not get there */
74        EXIT(3)
75
76        .rodata:
77statusstr: .ascii "status \0"
78causestr: .ascii " cause \0"
79pcstr: .ascii " pc \0"
80badvastr: .ascii " badva \0"
81mmustr_a: .ascii "mmu started ptpr_a \0"
82mmustr_b: .ascii "mmu started ptpr_b \0"
83startstr: .ascii "start\n\0"
84
85        .org EXCEP_ADDRESS - BOOT_ADDRESS
86        .globl evect
87evect:
88        j       excep
89        nop
90
91        /*
92         * code that will be switched by MMU switch.
93         * we use a ldscript trick here, to load this function at
94         * the appropriate address
95         */
96        .section .text2, "ax"
97        .globl doload
98doload:
99        jr      ra
100        li      a0, MAGIC1
101        /* we should not get there */
102        EXIT(1)
103        nop
104        .org doload + 0x1000 /* in the second page, mapped by pte1_b */
105        jr ra
106        li      a0, MAGIC2
107        /* we should not get there */
108        EXIT(2)
109        nop
110
111        .data
112        .word MAGIC1
113testval:
114        .word MAGIC2
115        .globl pte2_a
116
117/*
118 * two PD with two different PTE2 for code: check that itlb points to
119 * the right one by executing 2 different code at the same address
120 */
121pte2_a:
122        .align 12
123        .word PTE2_V | PTE2_C | PTE2_X
124        .word BOOT_ADDRESS >> 12
125        .word PTE2_V | PTE2_C | PTE2_X
126        .word (BOOT_ADDRESS+0x1000) >> 12
127        .org pte2_a + 4092
128        .word 0
129        .globl pte2_b
130pte2_b:
131        .align 12
132        .word PTE2_V | PTE2_C | PTE2_X
133        .word BOOT_ADDRESS >> 12
134        .word PTE2_V | PTE2_C | PTE2_X
135        .word (BOOT_ADDRESS+0x2000) >> 12
136        .org pte2_b + 4092
137        .word 0
138        .globl pte1_a
139pte1_a:
140        .align 13
141        .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
142        .word 0x0
143        .org pte1_a + (BOOT_ADDRESS >> 21) * 4
144        .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
145        .org pte1_a + (TTY_BASE >> 21) * 4
146        .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
147        .org pte1_a + (EXIT_BASE >> 21) * 4
148        .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
149        .org pte1_a + 8192
150        .globl pte1_b
151pte1_b:
152        .align 13
153        .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
154        .word 0x0
155        .org pte1_b + (BOOT_ADDRESS >> 21) * 4
156        .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_b !!! */
157        .org pte1_b + (TTY_BASE >> 21) * 4
158        .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
159        .org pte1_b + (EXIT_BASE >> 21) * 4
160        .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
161        .org pte1_b + 8188
162        .word 0
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