| 1 | /* |
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| 2 | * itlb inval on PTPR write: check that no stale entry exists in the itlb |
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| 3 | * after MMU context swicth |
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| 4 | */ |
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| 5 | #include <registers.h> |
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| 6 | #include <misc.h> |
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| 7 | #include <vcache.h> |
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| 8 | .text |
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| 9 | .globl _start |
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| 10 | _start: |
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| 11 | .set noreorder |
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| 12 | la k0, TTY_BASE |
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| 13 | la k1, EXIT_BASE |
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| 14 | |
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| 15 | PRINT(startstr) |
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| 16 | |
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| 17 | /* reset cop0 status (keep BEV) */ |
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| 18 | lui a0, 0x0040; |
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| 19 | mtc0 a0, COP0_STATUS |
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| 20 | |
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| 21 | la a0, pte1_b |
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| 22 | srl a0, a0, 13 |
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| 23 | mtc2 a0, VC_PTPR |
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| 24 | nop |
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| 25 | |
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| 26 | li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE |
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| 27 | mtc2 a0, VC_TLB_EN |
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| 28 | |
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| 29 | PRINT(mmustr_b) |
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| 30 | jal doload |
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| 31 | nop |
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| 32 | PRINTX |
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| 33 | PUTCHAR('\n') |
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| 34 | la a0, pte1_a |
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| 35 | srl a0, a0, 13 |
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| 36 | mtc2 a0, VC_PTPR |
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| 37 | nop |
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| 38 | #if 0 /* works with this - this shows the old pte2 address is cached */ |
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| 39 | la a0, pte2_a |
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| 40 | lw a1, 12(a0) |
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| 41 | la a0, pte2_b |
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| 42 | sw a1, 12(a0) |
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| 43 | #endif |
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| 44 | PRINT(mmustr_a) |
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| 45 | jal doload |
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| 46 | nop |
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| 47 | PRINTX |
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| 48 | PUTCHAR('\n') |
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| 49 | |
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| 50 | /* we should get there */ |
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| 51 | EXIT(0) |
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| 52 | |
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| 53 | .globl excep |
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| 54 | excep: |
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| 55 | .set noreorder |
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| 56 | PRINT(statusstr) |
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| 57 | mfc0 a0, COP0_STATUS |
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| 58 | PRINTX |
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| 59 | |
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| 60 | PRINT(causestr) |
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| 61 | mfc0 a0, COP0_CAUSE |
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| 62 | PRINTX |
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| 63 | |
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| 64 | PRINT(pcstr) |
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| 65 | mfc0 a0, COP0_EXPC |
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| 66 | PRINTX |
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| 67 | |
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| 68 | PRINT(badvastr) |
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| 69 | mfc0 a0, COP_0_BADVADDR |
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| 70 | PRINTX |
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| 71 | |
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| 72 | PUTCHAR('\n') |
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| 73 | /* we should not get there */ |
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| 74 | EXIT(3) |
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| 75 | |
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| 76 | .rodata: |
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| 77 | statusstr: .ascii "status \0" |
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| 78 | causestr: .ascii " cause \0" |
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| 79 | pcstr: .ascii " pc \0" |
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| 80 | badvastr: .ascii " badva \0" |
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| 81 | mmustr_a: .ascii "mmu started ptpr_a \0" |
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| 82 | mmustr_b: .ascii "mmu started ptpr_b \0" |
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| 83 | startstr: .ascii "start\n\0" |
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| 84 | |
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| 85 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
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| 86 | .globl evect |
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| 87 | evect: |
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| 88 | j excep |
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| 89 | nop |
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| 90 | |
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| 91 | /* |
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| 92 | * code that will be switched by MMU switch. |
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| 93 | * we use a ldscript trick here, to load this function at |
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| 94 | * the appropriate address |
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| 95 | */ |
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| 96 | .section .text2, "ax" |
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| 97 | .globl doload |
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| 98 | doload: |
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| 99 | jr ra |
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| 100 | li a0, MAGIC1 |
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| 101 | /* we should not get there */ |
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| 102 | EXIT(1) |
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| 103 | nop |
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| 104 | .org doload + 0x1000 /* in the second page, mapped by pte1_b */ |
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| 105 | jr ra |
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| 106 | li a0, MAGIC2 |
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| 107 | /* we should not get there */ |
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| 108 | EXIT(2) |
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| 109 | nop |
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| 110 | |
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| 111 | .data |
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| 112 | .word MAGIC1 |
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| 113 | testval: |
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| 114 | .word MAGIC2 |
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| 115 | .globl pte2_a |
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| 116 | |
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| 117 | /* |
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| 118 | * two PD with two different PTE2 for code: check that itlb points to |
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| 119 | * the right one by executing 2 different code at the same address |
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| 120 | */ |
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| 121 | pte2_a: |
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| 122 | .align 12 |
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| 123 | .word PTE2_V | PTE2_C | PTE2_X |
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| 124 | .word BOOT_ADDRESS >> 12 |
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| 125 | .word PTE2_V | PTE2_C | PTE2_X |
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| 126 | .word (BOOT_ADDRESS+0x1000) >> 12 |
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| 127 | .org pte2_a + 4092 |
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| 128 | .word 0 |
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| 129 | .globl pte2_b |
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| 130 | pte2_b: |
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| 131 | .align 12 |
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| 132 | .word PTE2_V | PTE2_C | PTE2_X |
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| 133 | .word BOOT_ADDRESS >> 12 |
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| 134 | .word PTE2_V | PTE2_C | PTE2_X |
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| 135 | .word (BOOT_ADDRESS+0x2000) >> 12 |
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| 136 | .org pte2_b + 4092 |
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| 137 | .word 0 |
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| 138 | .globl pte1_a |
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| 139 | pte1_a: |
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| 140 | .align 13 |
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| 141 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
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| 142 | .word 0x0 |
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| 143 | .org pte1_a + (BOOT_ADDRESS >> 21) * 4 |
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| 144 | .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ |
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| 145 | .org pte1_a + (TTY_BASE >> 21) * 4 |
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| 146 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
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| 147 | .org pte1_a + (EXIT_BASE >> 21) * 4 |
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| 148 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
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| 149 | .org pte1_a + 8192 |
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| 150 | .globl pte1_b |
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| 151 | pte1_b: |
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| 152 | .align 13 |
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| 153 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
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| 154 | .word 0x0 |
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| 155 | .org pte1_b + (BOOT_ADDRESS >> 21) * 4 |
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| 156 | .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_b !!! */ |
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| 157 | .org pte1_b + (TTY_BASE >> 21) * 4 |
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| 158 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
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| 159 | .org pte1_b + (EXIT_BASE >> 21) * 4 |
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| 160 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
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| 161 | .org pte1_b + 8188 |
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| 162 | .word 0 |
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