1 | /* |
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2 | * instruction fetch causes the PTE_L bit to be set |
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3 | */ |
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4 | #include <registers.h> |
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5 | #include <misc.h> |
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6 | #include <vcache.h> |
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7 | |
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8 | .text |
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9 | .globl _start |
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10 | _start: |
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11 | .set noreorder |
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12 | la k0, TTY_BASE |
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13 | la k1, EXIT_BASE |
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14 | |
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15 | PRINT(startstr) |
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16 | |
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17 | /* reset cop0 status (keep BEV) */ |
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18 | lui a0, 0x0040; |
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19 | mtc0 a0, COP0_STATUS |
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20 | |
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21 | la a0, pte1_a |
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22 | srl a0, a0, 13 |
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23 | mtc2 a0, VC_PTPR |
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24 | nop |
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25 | |
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26 | li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE |
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27 | mtc2 a0, VC_TLB_EN |
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28 | |
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29 | PRINT(mmustr) |
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30 | la s0, pte2_a |
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31 | lw s1, 8(s0) |
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32 | move a0, s1 |
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33 | PRINTX |
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34 | PUTCHAR(' ') |
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35 | la a1, PTE2_L |
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36 | and a0, s1, a1 |
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37 | beq a0, a1, fail /* PTE2_L already set, not good */ |
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38 | nop |
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39 | jal doload /* cause page to be referenced */ |
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40 | nop |
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41 | lw s1, 8(s0) |
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42 | move a0, s1 |
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43 | PRINTX |
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44 | PUTCHAR(' ') |
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45 | la a1, PTE2_L |
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46 | and a0, s1, a1 |
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47 | bne a0, a1, fail /* PTE2_L not set not good */ |
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48 | nop |
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49 | /* check again, using ll */ |
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50 | ll s1, 8(s0) |
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51 | move a0, s1 |
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52 | PRINTX |
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53 | PUTCHAR('\n') |
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54 | la a1, PTE2_L |
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55 | and a0, s1, a1 |
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56 | bne a0, a1, fail /* PTE2_L not set not good */ |
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57 | nop |
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58 | EXIT(0) |
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59 | fail: |
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60 | /* we should not get there */ |
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61 | EXIT(1) |
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62 | |
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63 | .globl excep |
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64 | excep: |
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65 | .set noreorder |
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66 | PRINT(statusstr) |
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67 | mfc0 a0, COP0_STATUS |
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68 | PRINTX |
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69 | |
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70 | PRINT(causestr) |
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71 | mfc0 a0, COP0_CAUSE |
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72 | PRINTX |
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73 | |
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74 | PRINT(pcstr) |
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75 | mfc0 a0, COP0_EXPC |
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76 | PRINTX |
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77 | |
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78 | PRINT(badvastr) |
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79 | mfc0 a0, COP_0_BADVADDR |
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80 | PRINTX |
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81 | |
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82 | PUTCHAR('\n') |
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83 | /* we should get there */ |
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84 | EXIT(0) |
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85 | |
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86 | .rodata: |
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87 | statusstr: .ascii "status \0" |
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88 | causestr: .ascii " cause \0" |
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89 | pcstr: .ascii " pc \0" |
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90 | badvastr: .ascii " badva \0" |
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91 | mmustr: .ascii "mmu started \0" |
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92 | startstr: .ascii "start\n\0" |
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93 | |
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94 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
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95 | .globl evect |
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96 | evect: |
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97 | j excep |
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98 | nop |
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99 | |
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100 | /* |
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101 | * code that will be switched by MMU switch. |
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102 | * we use a ldscript trick here, to load this function at |
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103 | * the appropriate address |
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104 | */ |
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105 | .section .text2, "ax" |
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106 | .globl doload |
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107 | doload: |
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108 | jr ra |
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109 | li a0, MAGIC1 |
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110 | /* we should not get there */ |
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111 | EXIT(1) |
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112 | nop |
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113 | |
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114 | .data |
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115 | .word MAGIC1 |
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116 | testval: |
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117 | .word MAGIC2 |
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118 | .globl pte2_a |
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119 | |
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120 | /* |
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121 | * one PD with a level 2 PTP: we invalidate an entry in the PTP and |
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122 | * check that the VA is no longer accessible |
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123 | */ |
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124 | pte2_a: |
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125 | .align 12 |
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126 | .word PTE2_V | PTE2_C | PTE2_X |
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127 | .word BOOT_ADDRESS >> 12 |
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128 | .word PTE2_V | PTE2_C | PTE2_X |
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129 | .word (BOOT_ADDRESS+0x1000) >> 12 |
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130 | .org pte2_a + 4092 |
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131 | .word 0 |
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132 | .globl pte2_b |
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133 | .globl pte1_a |
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134 | pte1_a: |
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135 | .align 13 |
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136 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
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137 | .word 0x0 |
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138 | .org pte1_a + (BOOT_ADDRESS >> 21) * 4 |
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139 | .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ |
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140 | .org pte1_a + (TTY_BASE >> 21) * 4 |
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141 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
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142 | .org pte1_a + (EXIT_BASE >> 21) * 4 |
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143 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
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144 | .org pte1_a + 8192 |
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