| 1 | /* |
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| 2 | * pte2d_ref: a sc to data should set the dirty bits in PTE |
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| 3 | */ |
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| 4 | #include <registers.h> |
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| 5 | #include <misc.h> |
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| 6 | #include <vcache.h> |
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| 7 | .text |
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| 8 | .globl _start |
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| 9 | _start: |
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| 10 | .set noreorder |
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| 11 | la k0, TTY_BASE |
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| 12 | la k1, EXIT_BASE |
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| 13 | |
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| 14 | PRINT(startstr) |
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| 15 | |
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| 16 | /* reset cop0 status (keep BEV) */ |
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| 17 | lui a0, 0x0040; |
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| 18 | mtc0 a0, COP0_STATUS |
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| 19 | |
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| 20 | la a0, pte1_a |
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| 21 | srl a0, a0, 13 |
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| 22 | mtc2 a0, VC_PTPR |
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| 23 | nop |
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| 24 | |
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| 25 | li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE |
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| 26 | mtc2 a0, VC_TLB_EN |
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| 27 | |
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| 28 | PRINT(mmustr) |
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| 29 | la s0, pte2_a |
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| 30 | lw s1, 0(s0) /* get PTE */ |
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| 31 | move a0, s1 |
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| 32 | PRINTX |
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| 33 | PUTCHAR(' ') |
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| 34 | la a1, (PTE2_L | PTE2_D) |
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| 35 | and a0, s1, a1 |
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| 36 | bne a0, zero, fail /* PTE2_L or PTE2_D already set, not good */ |
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| 37 | nop |
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| 38 | |
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| 39 | la t0, testval + 0x00200000 |
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| 40 | la a1, MAGIC3 |
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| 41 | 1: |
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| 42 | ll a0, 0(t0) |
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| 43 | sc a1, 0(t0); /* cause page to be referenced and dirty */ |
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| 44 | beqz a1, 1b |
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| 45 | nop |
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| 46 | |
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| 47 | lw s1, 0(s0) /* get PTE */ |
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| 48 | move a0, s1 |
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| 49 | PRINTX |
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| 50 | PUTCHAR(' ') |
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| 51 | la a1, (PTE2_L | PTE2_D) |
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| 52 | and a0, s1, a1 |
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| 53 | bne a0, a1, fail /* PTE2_L not set, not good */ |
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| 54 | nop |
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| 55 | |
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| 56 | /* check again, using ll */ |
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| 57 | ll s1, 0(s0) /* get PTE */ |
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| 58 | move a0, s1 |
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| 59 | PRINTX |
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| 60 | PUTCHAR('\n') |
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| 61 | la a1, (PTE2_L | PTE2_D) |
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| 62 | and a0, s1, a1 |
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| 63 | bne a0, a1, fail /* PTE2_L not set, not good */ |
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| 64 | nop |
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| 65 | |
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| 66 | EXIT(0) |
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| 67 | fail: |
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| 68 | /* we should not get there */ |
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| 69 | EXIT(1) |
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| 70 | |
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| 71 | .globl excep |
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| 72 | excep: |
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| 73 | .set noreorder |
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| 74 | PRINT(statusstr) |
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| 75 | mfc0 a0, COP0_STATUS |
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| 76 | PRINTX |
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| 77 | |
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| 78 | PRINT(causestr) |
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| 79 | mfc0 a0, COP0_CAUSE |
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| 80 | PRINTX |
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| 81 | |
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| 82 | PRINT(pcstr) |
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| 83 | mfc0 a0, COP0_EXPC |
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| 84 | PRINTX |
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| 85 | |
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| 86 | PRINT(badvastr) |
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| 87 | mfc0 a0, COP_0_BADVADDR |
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| 88 | PRINTX |
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| 89 | |
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| 90 | PUTCHAR('\n') |
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| 91 | /* we should get there */ |
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| 92 | EXIT(0) |
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| 93 | |
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| 94 | .rodata: |
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| 95 | statusstr: .ascii "status \0" |
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| 96 | causestr: .ascii " cause \0" |
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| 97 | pcstr: .ascii " pc \0" |
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| 98 | badvastr: .ascii " badva \0" |
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| 99 | mmustr: .ascii "mmu started \0" |
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| 100 | startstr: .ascii "start\n\0" |
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| 101 | |
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| 102 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
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| 103 | .globl evect |
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| 104 | evect: |
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| 105 | j excep |
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| 106 | nop |
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| 107 | |
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| 108 | .data |
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| 109 | /* first 2 pages is data that will be switched my mmu switch */ |
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| 110 | data_a: |
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| 111 | .word MAGIC1 |
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| 112 | testval: |
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| 113 | .word MAGIC2 |
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| 114 | .globl pte2_a |
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| 115 | /* |
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| 116 | * one PD with a level 2 PTP: we invalidate an entry in the PTP and |
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| 117 | * check that the VA is no longer accessible |
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| 118 | */ |
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| 119 | pte2_a: |
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| 120 | .align 12 |
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| 121 | .word PTE2_V | PTE2_C | PTE2_X | PTE2_W |
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| 122 | .word 0x0000 >> 12 /* check real value of data_a */ |
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| 123 | .org pte2_a + 4092 |
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| 124 | .word 0 |
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| 125 | .globl pte2_b |
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| 126 | .globl pte1_a |
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| 127 | pte1_a: |
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| 128 | .align 13 |
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| 129 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
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| 130 | .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ |
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| 131 | .org pte1_a + (BOOT_ADDRESS >> 21) * 4 |
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| 132 | .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ |
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| 133 | .org pte1_a + (TTY_BASE >> 21) * 4 |
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| 134 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
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| 135 | .org pte1_a + (EXIT_BASE >> 21) * 4 |
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| 136 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
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| 137 | .org pte1_a + 8192 |
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