[520] | 1 | /* |
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| 2 | * Check that the MMU doens't clobber the OS bits in PTEs, and interraction |
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| 3 | * with ll/sc |
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| 4 | */ |
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| 5 | #include <registers.h> |
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| 6 | #include <misc.h> |
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| 7 | #include <vcache.h> |
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| 8 | |
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| 9 | .text |
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| 10 | .globl _start |
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| 11 | _start: |
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| 12 | .set noreorder |
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| 13 | la k0, TTY_BASE |
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| 14 | la k1, EXIT_BASE |
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| 15 | |
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| 16 | /* reset cop0 status (keep BEV) */ |
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| 17 | lui a0, 0x0040; |
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| 18 | mtc0 a0, COP0_STATUS |
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| 19 | |
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| 20 | la a0, pte1 |
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| 21 | srl a0, a0, 13 |
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| 22 | mtc2 a0, VC_PTPR |
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| 23 | nop |
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| 24 | |
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| 25 | li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE |
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| 26 | mtc2 a0, VC_TLB_EN |
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| 27 | |
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| 28 | /* do a swap of pte2[0] to make the entry valid */ |
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| 29 | la s0, pte2 + 0x00200000 |
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| 30 | 1: la a1, PTE2_V | PTE2_C | PTE2_W | PTE2_os |
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| 31 | ll a0, 0(s0) |
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| 32 | sc a1, 0(s0) |
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| 33 | beqz a1, 1b |
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| 34 | nop |
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| 35 | PRINTX |
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| 36 | PUTCHAR(' ') |
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| 37 | /* now write to myvar via pte2[0] */ |
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| 38 | li a0, MAGIC2 |
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| 39 | la s1, myvar + 0x00200000 |
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| 40 | sw a0, 0(s1) |
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| 41 | /* |
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| 42 | * and invalidate pte2[0], again using a swap |
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| 43 | * check that we get the same value with lw and ll |
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| 44 | */ |
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| 45 | lw s1, 0(s0) |
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| 46 | 2: |
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| 47 | move a1, zero |
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| 48 | ll a0, 0(s0) |
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| 49 | sc a1, 0(s0) |
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| 50 | beqz a1, 2b |
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| 51 | PRINTX |
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| 52 | PUTCHAR(' ') |
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| 53 | move a0, s1 |
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| 54 | PRINTX |
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| 55 | PUTCHAR(' ') |
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| 56 | /* finally check what lw tells us now */ |
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| 57 | lw a0, 0(s0) |
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| 58 | PRINTX |
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| 59 | PUTCHAR('\n') |
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| 60 | |
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| 61 | EXIT(0) |
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| 62 | |
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| 63 | .globl excep |
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| 64 | excep: |
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| 65 | .set noreorder |
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| 66 | PRINT(statusstr) |
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| 67 | mfc0 a0, COP0_STATUS |
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| 68 | PRINTX |
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| 69 | |
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| 70 | PRINT(causestr) |
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| 71 | mfc0 a0, COP0_CAUSE |
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| 72 | PRINTX |
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| 73 | |
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| 74 | PRINT(pcstr) |
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| 75 | mfc0 a0, COP0_EXPC |
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| 76 | PRINTX |
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| 77 | |
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| 78 | PRINT(badvastr) |
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| 79 | mfc0 a0, COP_0_BADVADDR |
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| 80 | PRINTX |
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| 81 | |
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| 82 | PUTCHAR('\n') |
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| 83 | /* we should not get there */ |
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| 84 | EXIT(1) |
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| 85 | |
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| 86 | .rodata: |
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| 87 | statusstr: .ascii "status \0" |
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| 88 | causestr: .ascii " cause \0" |
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| 89 | pcstr: .ascii " pc \0" |
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| 90 | badvastr: .ascii " badva \0" |
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| 91 | value: .word 0x1234abcd |
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| 92 | string: .ascii "hello world \0" |
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| 93 | |
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| 94 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
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| 95 | .globl evect |
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| 96 | evect: |
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| 97 | j excep |
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| 98 | nop |
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| 99 | |
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| 100 | .data |
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| 101 | myvar: .word MAGIC1 |
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| 102 | .globl pte1 |
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| 103 | pte2: |
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| 104 | .align 12 |
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| 105 | .word 0 /* invalid for now */ |
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| 106 | .word 0x0000 >> 12 /* check real value of myvar */ |
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| 107 | .word PTE2_V | PTE2_C | PTE2_W | PTE2_os /* map pte2 too */ |
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| 108 | .word 0x1000 >> 12 /* check real address of pte2 */ |
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| 109 | .org pte2 + 4092 |
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| 110 | .word 0 |
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| 111 | .globl pte1 |
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| 112 | pte1: |
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| 113 | .align 13 |
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| 114 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
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| 115 | .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2 */ |
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| 116 | .org pte1 + (BOOT_ADDRESS >> 21) * 4 |
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| 117 | .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ |
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| 118 | .org pte1 + (TTY_BASE >> 21) * 4 |
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| 119 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
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| 120 | .org pte1 + (EXIT_BASE >> 21) * 4 |
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| 121 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
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| 122 | .org pte1 + 8192 |
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| 123 | .word 0 |
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| 124 | |
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